AO4840E

AO4840E 40V Dual N-Channel AlphaMOS General Description Product Summary VDS • Advanced trench technology • Low RDS(ON) • Low Gate Charge • ESD protected • RoHS and Halogen-Free Compliant Applications ID (at VGS=10V) 40V 6A RDS(ON) (at VGS=10V) < 28mΩ RDS(ON) (at VGS=4.5V) < 35mΩ Typical ESD protection HBM Class 2 100% UIS Tested 100% Rg Tested • Buck Converter • DC motor drive • Load switch SOIC-8 Top View Bottom View D1 Top View S2 G2 S1 G1 1 2 3 4 8 7 6 5 D2 D2 D1 D1 G1 D2 G2 S1 S2 Pin1 Orderable Part Number Package Type Form Minimum Order Quantity AO4840E SO-8 Tape & Reel 3000 Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Drain-Source Voltage Symbol VDS Gate-Source Voltage VGS TA=25°C Continuous Drain Current Pulsed Drain Current C Avalanche energy L=0.1mH VDS Spike 10µs TA=25°C Power Dissipation B C Junction and Storage Temperature Range Thermal Characteristics Parameter Maximum Junction-to-Ambient A Maximum Junction-to-Ambient A D Maximum Junction-to-Lead Rev.1.0: September 2015 Steady-State Steady-State A IAS 14 A EAS 10 mJ VSPIKE 48 V 2 W 1.2 TJ, TSTG Symbol t ≤ 10s V 30 PD TA=70°C ±20 5 IDM Avalanche Current C Units V 6 ID TA=70°C Maximum 40 RθJA RθJL -55 to 150 Typ 48 74 32 www.aosmd.com °C Max 62.5 90 40 Units °C/W °C/W °C/W Page 1 of 5 AO4840E Electrical Characteristics (TJ=25°C unless otherwise noted) Symbol Parameter STATIC PARAMETERS BVDSS Drain-Source Breakdown Voltage Conditions Min ID=250µA, VGS=0V Typ Zero Gate Voltage Drain Current IGSS VGS(th) Gate-Body leakage current VDS=0V, VGS=±20V Gate Threshold Voltage VDS=VGS, ID=250µA V 1 TJ=55°C 1.7 ±10 µA 2.1 2.6 V 23 28 39 47 35 RDS(ON) Static Drain-Source On-Resistance VGS=4.5V, ID=5A 28 gFS Forward Transconductance VDS=5V, ID=6A 29 VSD Diode Forward Voltage IS=1A, VGS=0V 0.75 IS Maximum Body-Diode Continuous Current TJ=125°C DYNAMIC PARAMETERS Input Capacitance Ciss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate resistance µA 5 VGS=10V, ID=6A Coss Units 40 VDS=40V, VGS=0V IDSS Max VGS=0V, VDS=20V, f=1MHz mΩ mΩ S 1 V 3 A 520 pF 65 pF 32 pF 4.2 6.5 Ω SWITCHING PARAMETERS Qg(10V) Total Gate Charge 9 15 nC Qg(4.5V) Total Gate Charge 4.5 10 f=1MHz VGS=10V, VDS=20V, ID=6A 2 nC Qgs Gate Source Charge 2 nC Qgd tD(on) Gate Drain Charge 1.5 nC Turn-On DelayTime 5.5 ns tr Turn-On Rise Time tD(off) Turn-Off DelayTime tf trr Turn-Off Fall Time 7 ns IF=6A, di/dt=500A/µs 8 Qrr Body Diode Reverse Recovery Charge IF=6A, di/dt=500A/µs 13 ns nC Body Diode Reverse Recovery Time VGS=10V, VDS=20V, RL=3.3Ω, RGEN=3Ω 2.5 ns 20.5 ns A. The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The value in any given application depends on the user's specific board design. B. The power dissipation PD is based on TJ(MAX)=150°C, using ≤ 10s junction-to-ambient thermal resistance. C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initialTJ=25°C. D. The RθJA is the sum of the thermal impedance from junction to lead RθJL and lead to ambient. E. The static characteristics in Figures 1 to 6 are obtained using or equal to 4.5V Figure 9: Maximum Forward Biased Safe Operating Area (Note F) 100 1 1E-05 0.001 0.1 10 1000 Pulse Width (s) Figure 10: Single Pulse Power Rating Junction-toAmbient (Note F) Zθ JA Normalized Transient Thermal Resistance 10 D=Ton/T TJ,PK=TA+PDM.ZθJA.RθJA 1 In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse RθJA=90°C/W 0.1 PDM 0.01 0.001 1E-05 Single Pulse Ton T 0.0001 0.001 0.01 0.1 1 10 100 Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance (Note F) Rev.1.0: September 2015 www.aosmd.com Page 4 of 5 AO4840E Figure A: Charge Gate Charge Test Circuit & Waveforms Gate Test Circuit & Waveform Vgs Qg 10V + + Vds VDC - Qgs Qgd VDC - DUT Vgs Ig Charge Figure B:Resistive ResistiveSwitching Switching Test Test Circuit Circuit&&Waveforms Waveforms RL Vds Vds DUT Vgs 90% + Vdd VDC - Rg 10% Vgs Vgs td(on) tr td(off) ton tf toff Figure C: UnclampedInductive InductiveSwitching Switching (UIS) Test Unclamped Test Circuit Circuit&&Waveforms Waveforms L 2 EAR= 1/2 LIAR Vds BVDSS Vds Id + Vdd Vgs Vgs I AR VDC - Rg Id DUT Vgs Vgs Figure D: Recovery Diode Recovery Test Circuit & Waveforms Diode Test Circuit & Waveforms Q rr = - Idt Vds + DUT Vgs Vds Isd Vgs Ig Rev.1.0: September 2015 L Isd + Vdd t rr dI/dt I RM Vdd VDC - IF Vds www.aosmd.com Page 5 of 5