AOZ1031AI_3

AOZ1031AI EZBuck™ 3A Synchronous Buck Regulator General Description Features The AOZ1031A is a high efficiency, easy to use, 3A synchronous buck regulator. The AOZ1031A works from 4.5V to 18V input voltage range, and provides up to 3A of continuous output current with an output voltage adjustable down to 0.8V. z 4.5V to 18V operating input voltage range The AOZ1031A comes in a SO-8 package and is rated over a -40°C to +85°C operating ambient temperature range. z Internal soft start z Synchronous Buck: 80mΩ internal high-side switch and 30mΩ internal low-side switch with integrated schottky diode z High efficiency: up to 95% z Output voltage adjustable to 0.8V z 3A continuous output current z Fixed 600kHz PWM operation z Pulse skipping at light load for high efficiency over entire load range z Cycle-by-cycle current limit z Pre-bias start-up z Short-circuit protection z Thermal shutdown z SO-8 package Applications z Point of load DC/DC converters z LCD TV z Set top boxes z DVD/Blu-ray players/recorders z Cable modems z PCIe graphics cards z Telecom/Networking/Datacom equipment Typical Application VIN C1 22µF VIN L1 4.7µH EN AOZ1031 R1 COMP RC CC VOUT LX C2, C3 22µF FB AGND PGND R2 Figure 1. 3.3V 3A Synchronous Buck Regulator Rev. 1.6 March 2010 www.aosmd.com Page 1 of 15 AOZ1031AI Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ1031AI -40°C to +85°C SO-8 RoHS Compliant Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration PGND 1 8 LX VIN 2 7 LX AGND 3 6 EN FB 4 5 COMP SO-8 (Top View) Pin Description Pin Number Pin Name 1 PGND 2 VIN 3 AGND 4 FB 5 COMP 6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. Do not leave it open. 7, 8 LX Switching node. PWM output connection to inductor. Rev. 1.6 March 2010 Pin Function Power ground. PGND needs to be electrically connected to AGND. Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the device starts up. Analog ground. AGND is the reference point for controller section. AGND needs to be electrically connected to PGND. Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider between the output and AGND. External loop compensation pin. Connect a RC network between COMP and AGND to compensate the control loop. www.aosmd.com Page 2 of 15 AOZ1031AI Block Diagram VIN UVLO & POR EN Internal +5V 5V LDO Regulator OTP + ISen – Reference & Bias Softstart Q1 ILimit + + 0.8V EAmp FB – – PWM Comp PWM Control Logic + Level Shifter + FET Driver LX Q2 COMP + 0.2V 600kHz – + 0.96V Frequency Foldback Comparator Over-Voltage Protection Comparator – AGND Absolute Maximum Ratings Recommend Operating Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter PGND The device is not guaranteed to operate beyond the Maximum Operating Ratings. Rating Supply Voltage (VIN) 20V LX to AGND -0.7V to VIN+0.3V LX to AGND -3V for 20 nS EN to AGND -0.3V to VIN+0.3V FB to AGND -0.3V to 6V COMP to AGND -0.3V to 6V PGND to AGND -0.3V to +0.3V Junction Temperature (TJ) +150°C Storage Temperature (TS) -65°C to +150°C ESD Rating(1) 2.0kV Parameter Rating Supply Voltage (VIN) 4.5V to 18V Output Voltage Range 0.8V to VIN Ambient Temperature (TA) -40°C to +85°C Package Thermal Resistance SO-8 (ΘJA) SO-8 (ΘJC) 87°C/W 30°C/W Package Power Dissipation (PD) @ 25°C Ambient SO-8 1.15W Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5kΩ in series with 100pF. Rev. 1.6 March 2010 www.aosmd.com Page 3 of 15 AOZ1031AI Electrical Characteristics TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3) Symbol VIN Parameter Conditions Supply Voltage Min. Typ. 4.5 Max. Units 18 V VUVLO Input under-voltage lockout threshold VIN rising VIN falling 4.1 3.7 IIN Supply current (Quiescent) IOUT = 0, VFB = 1.2V, VEN >1.2V 1.6 2.5 mA Shutdown supply current VEN = 0V 1 10 μA Feedback Voltage TA = 25°C 0.8 0.812 IOFF VFB V Load regulation 0.5 % Line regulation 1 % IFB Feedback voltage input current VEN EN input threshold VHYS 0.788 V V Off threshold On threshold 200 nA 0.6 V V 2 EN input hysteresis 100 mV MODULATOR Frequency 500 DMAX Maximum Duty Cycle 100 DMIN Minimum Duty Cycle fO 600 700 kHz % 9 % Error amplifier voltage gain 500 V/V Error amplifier transconductance 200 μA / V PROTECTION ILIM VOVP tSS Current Limit 4.0 5.0 A Over-Voltage Protection Off threhsold On threshold 960 860 mV mV Over-temperature shutdown limit TJ rising TJ falling 150 100 °C °C 2.2 ms Soft Start Interval OUTPUT STAGE High-side switch on-resistance VIN = 12V VIN = 5V 80 130 100 180 mΩ mΩ Low-side switch on-resistance VIN = 12V VIN = 5V 30 56 36 70 mΩ mΩ Notes: 3. The device is not guaranteed to operate beyond the Maximum Operating ratings. Rev. 1.6 March 2010 www.aosmd.com Page 4 of 15 AOZ1031AI Typical Performance Characteristics Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Light Load (DCM) Operation Full Load (CCM) Operation 1us/div 1us/div Start Up to Full Load Short Circuit Protection 1ms/div 4ms/div 50% to 100% Load Transient Short Circuit Recovery 10ms/div 100us/div Rev. 1.6 March 2010 www.aosmd.com Page 5 of 15 AOZ1031AI Efficiency AOZ1031AI Efficiency Efficiency (VIN = 12V) vs. Load Current 90 90 80 80 70 70 VO = 1.2V VO = 1.8V VO = 3.3V VO = 5V 60 50 40 Efficiency (VIN = 5V) vs. Load Current 100 Efficiency (%) Efficiency (%) 100 30 VO = 1.2V VO = 1.8V VO = 3.3V 60 50 40 30 20 20 10 10 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 IOUT (A) 2.0 2.5 3.0 IOUT (A) Thermal Derating Thermal de-rating curves for SO-8 package part under typical input and output condition based on the evaluation board. 25°C ambient temperature and natural convection (air speed < 50LFM) unless otherwise specified. Derating Curves at 12V Input 5 4 4 1.2V, 1.8V Output 3 3.3V Output 2 1 0 Output Current (IO) Output Current (IO) Derating Curves at 5V/6V Input 5 1.2V, 1.8V, 3.3V, 5.0V Output 3 2 1 0 25 35 45 55 65 75 85 25 Ambient Temperature (TA) Rev. 1.6 March 2010 35 45 55 65 75 85 Ambient Temperature (TA) www.aosmd.com Page 6 of 15 AOZ1031AI Detailed Description The AOZ1031A is a current-mode step down regulator with integrated high-side PMOS switch and a low-side NMOS switch. It operates from a 4.5V to 18V input voltage range and supplies up to 3A of load current. The duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. Features include enable control, Power-On Reset, input under voltage lockout, output over voltage protection, active high power good state, fixed internal soft-start and thermal shut down. The AOZ1031A is available in SO-8 package. Enable and Soft Start The AOZ1031A has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when the input voltage rises to 4.1V and voltage on EN pin is HIGH. In soft start process, the output voltage is ramped to regulation voltage in typically 2.2ms. The 2.2ms soft start time is set internally. Comparing with regulators using freewheeling Schottky diodes, the AOZ1031A uses freewheeling NMOSFET to realize synchronous rectification. It greatly improves the converter efficiency and reduces power loss in the low-side switch. The AOZ1031A will enter the discontinuous conduction mode at light load. Several pulses may be skipped in between switching cycles at very light load, it further improving light load efficiency. The AOZ1031A uses a P-Channel MOSFET as the high-side switch. It saves the bootstrap capacitor normally seen in a circuit which is using an NMOS switch. It allows 100% turn-on of the high-side switch to achieve linear regulation mode of operation. The minimum voltage drop from VIN to VO is the load current times DC resistance of MOSFET plus DC resistance of buck inductor. It can be calculated by equation below: V O_MAX = V IN – I O × R DS ( ON ) where; The EN pin of the AOZ1031A is active high. Connect the EN pin to VIN if enable function is not used. Pull it to ground will disable the AOZ1031A. Do not leave it open. The voltage on EN pin must be above 2V to enable the AOZ1031A. When voltage on EN pin falls below 0.6V, the AOZ1031A is disabled. If an application circuit requires the AOZ1031A to be disabled, an open drain or open collector circuit should be used to interface to EN pin. Steady-State Operation Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1031A integrates an internal P-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the internal low-side N-MOSFET switch to output. The internal adaptive FET driver guarantees no turn on overlap of both high-side and low-side switch. Rev. 1.6 March 2010 VO_MAX is the maximum output voltage;, VIN is the input voltage from 4.5V to 18V, IO is the output current from 0A to 3A, and RDS(ON) is the on resistance of internal MOSFET. The value is between 97mΩ and 200mΩ depending on input voltage and junction temperature. Switching Frequency The AOZ1031A switching frequency is fixed and set by an internal oscillator. The practical switching frequency could range from 500kHz to 700kHz due to device variation. Output Voltage Programming Output voltage can be set by feeding back the output to the FB pin by using a resistor divider network. In the application circuit shown in Figure 1. The resistor divider network includes R1 and R2. Usually, a design is started by picking a fixed R2 value and calculating the required R1 with equation below. R 1⎞ ⎛ V O = 0.8 × ⎜ 1 + -------⎟ R 2⎠ ⎝ Some standard value of R1, R2 and most used output voltage values are listed in Table 1 on the next page. www.aosmd.com Page 7 of 15 AOZ1031AI Power-On Reset (POR) Table 1. Vo (V) R1 (kΩ) R2 (kΩ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4.1V, the converter starts operation. When input voltage falls below 3.7V, the converter will be shut down. Thermal Protection The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper PMOS and inductor. Protection Features The AOZ1031A has multiple protection features to prevent system circuit damage under abnormal conditions. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1031A employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. When the output is shorted to ground under fault conditions, the inductor current decays very slow during a switching cycle because of Vo=0V. To prevent catastrophic failure, AOZ1031A detects the duration the overcurrent condition occurs. If the over-current condition occurs for certain period, AOZ1013A totally turns off for a period of time, then restarts. If the fault is still there, then the chip will be off again. The converter will initiate a soft start once the over-current condition disappears. An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side PMOS if the junction temperature exceeds 150°C. The regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100°C. Application Information The basic AOZ1031A application circuit is show in Figure 1. Component selection is explained below. Input Capacitor The input capacitor must be connected to the VIN pin and PGND pin of AOZ1031A to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below: VO ⎞ VO IO ⎛ ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------f × C IN ⎝ V IN⎠ V IN Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by: VO ⎛ VO ⎞ - ⎜ 1 – --------⎟ I CIN_RMS = I O × -------V IN ⎝ V IN⎠ if we let m equal the conversion ratio: VO -------- = m V IN The relation between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 2 on the next page. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO. Rev. 1.6 March 2010 www.aosmd.com Page 8 of 15 AOZ1031AI The inductor takes the highest current in a buck circuit. The conduction loss on inductor need to be checked for thermal and efficiency requirements. 0.5 0.4 Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. ICIN_RMS(m) 0.3 IO 0.2 Output Capacitor 0.1 0 0 0.5 m 1 Figure 2. ICIN vs. Voltage Conversion Ratio For reliable operation and best performance, the input capacitors must have current rating higher than ICIN_RMS at worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high current rating. Depending on the application circuits, other low ESR tantalum capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures are based on certain amount of life time. Further de-rating may be necessary in practical design. The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: 1 ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞ ⎝ 8×f×C ⎠ O Inductor where; The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: CO is output capacitor value, and VO ⎛ VO ⎞ -⎟ ΔI L = ----------- × ⎜ 1 – -------f×L ⎝ V IN⎠ When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: 1 ΔV O = ΔI L × ------------------------8×f×C The peak inductor current is: ΔI L I Lpeak = I O + -------2 O High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. Rev. 1.6 March 2010 ESRCO is the Equivalent Series Resistor of output capacitor. If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: ΔV O = ΔI L × ESR CO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum are recommended to be used as output capacitors. www.aosmd.com Page 9 of 15 AOZ1031AI In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: ΔI L I CO_RMS = ---------12 where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage gain, which is 500 V/V, and C2 is compensation capacitor in Figure 1. Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. Loop Compensation The AOZ1031A employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole can be calculated by: 1 f P1 = ----------------------------------2π × C O × R L The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: 1 f Z1 = -----------------------------------------------2π × C O × ESR CO where; The zero given by the external compensation network, capacitor C2 and resistor R3, is located at: 1 f Z2 = ----------------------------------2π × C C × R C To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. The AOZ1031A operates at a frequency range from 500kHz to 700kHz. It is recommended to choose a crossover frequency equal or less than 40kHz. f C = 40kHz The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: VO 2π × C 2 R C = f C × ---------- × ----------------------------G ×G V CO is the output filter capacitor, FB RL is load resistor value, and EA CS ESRCO is the equivalent series resistance of output capacitor. where; The compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. Several different types of compensation network can be used for the AOZ1031A. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. fC is desired crossover frequency. For best performance, fC is set to be about 1/10 of switching frequency, GCS is the current sense circuit transconductance, which is 6.68 A/V. In the AOZ1031A, FB pin and COMP pin are the inverting input and the output of internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fP1 but lower than 1/5 of selected crossover frequency. CC can is selected by: G EA f P2 = ------------------------------------------2π × C C × G VEA 1.5 C C = ----------------------------------2π × R C × f P1 Rev. 1.6 March 2010 VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and www.aosmd.com Page 10 of 15 AOZ1031AI Equation above can also be simplified to: Please see the thermal de-rating curves for maximum load current of the AOZ1031A under different ambient temperature. CO × RL C C = --------------------RC An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com. Thermal Management and Layout Consideration In the AOZ1031A buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the low side NMOSFET. Current flows in the second loop when the low side NMOSFET is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is strongly recommended to connect input capacitor, output capacitor, and PGND pin of the AOZ1031A. In the AOZ1031A buck regulator circuit, the major power dissipating components are the AOZ1031A and the output inductor. The total power dissipation of converter circuit can be measured by input power minus output power. P total_loss = V IN × I IN – V O × I O The thermal performance of the AOZ1031A is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. The AOZ1031A is standard SO-8 package. Several layout tips are listed below for the best electric and thermal performance. Figure 3 on the next page illustrates a PCB layout example of AOZ1031A. 1. The LX pins are connected to internal PFET and NFET drains. They are low resistance thermal conduction path and most noisy switching node. Connected a large copper plane to LX pin to help thermal dissipation. 2. Do not use thermal relief connection to the VIN and the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 3. Input capacitor should be connected to the VIN pin and the PGND pin as close as possible. 4. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin. 5. Make the current trace from LX pins to L to Co to the PGND as short as possible. The power dissipation of inductor can be approximately calculated by output current and DCR of inductor. 6. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. P inductor_loss = IO2 × R inductor × 1.1 7. Keep sensitive signal trace far away form the LX pins. The actual junction temperature can be calculated with power dissipation in the AOZ1031A and thermal impedance from junction to ambient. T junction = ( P total_loss – P inductor_loss ) × Θ JA The maximum junction temperature of AOZ1031A is 150°C, which limits the maximum load current capability. Rev. 1.6 March 2010 www.aosmd.com Page 11 of 15 AOZ1031AI Figure 3. AOZ1031A (SO-8) PCB layout Rev. 1.6 March 2010 www.aosmd.com Page 12 of 15 AOZ1031AI Package Dimensions, SO-8L D Gauge Plane Seating Plane e 0.25 8 L E E1 h x 45° 1 C θ 7° (4x) A2 A 0.1 b A1 Dimensions in millimeters 2.20 5.74 1.27 0.80 Unit: mm Symbols A Min. 1.35 A1 A2 Dimensions in inches Max. 1.75 0.25 1.65 Symbols A Min. 0.053 Nom. 0.065 Max. 0.069 0.10 1.25 Nom. 1.65 — 1.50 A1 A2 0.004 0.049 — 0.059 0.010 0.065 b c D 0.31 0.17 4.80 — — 4.90 0.51 0.25 5.00 b c D 0.012 0.007 0.189 — — 0.193 0.020 0.010 0.197 E1 e E 3.80 3.90 4.00 1.27 BSC 0.150 h L 0.25 0.40 6.00 — — 6.20 0.50 1.27 E1 e E h L 0.010 0.016 — — 0.020 0.050 θ 0° — 8° θ 0° — 8° 5.80 0.154 0.157 0.050 BSC 0.228 0.236 0.244 Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating 3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils. 4. Dimension L is measured in gauge plane. 5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Rev. 1.6 March 2010 www.aosmd.com Page 13 of 15 AOZ1031AI Tape and Reel Dimensions SO-8 Carrier Tape P1 D1 See Note 3 P2 T See Note 5 E1 E2 E See Note 3 B0 K0 A0 D0 P0 Feeding Direction Unit: mm Package SO-8 (12mm) A0 6.40 ±0.10 B0 5.20 ±0.10 K0 2.10 ±0.10 D0 1.60 ±0.10 D1 1.50 ±0.10 E 12.00 ±0.10 SO-8 Reel E1 1.75 ±0.10 E2 5.50 ±0.10 P0 8.00 ±0.10 P1 4.00 ±0.10 P2 2.00 ±0.10 T 0.25 ±0.10 W1 S G N M K V R H W N Tape Size Reel Size M W 12mm ø330 ø330.00 ø97.00 13.00 ±0.10 ±0.30 ±0.50 W1 17.40 ±1.00 H K ø13.00 10.60 +0.50/-0.20 S 2.00 ±0.50 G — R — V — SO-8 Tape Leader/Trailer & Orientation Trailer Tape 300mm min. or 75 empty pockets Rev. 1.6 March 2010 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. or 125 empty pockets Page 14 of 15 AOZ1031AI AOZ1031 Package Marking Z1031AI FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.6 March 2010 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 15 of 15