AOZ2151TQI-19
28V/4A Synchronous EZBuckTM Regulator
General Description
Features
The AOZ2151TQI-19 is a high-efficiency, easy-to-use
DC/DC synchronous buck regulator that operates up to
28V. The device is capable of supplying 4A of continuous
output current with an output voltage adjustable down to
0.8V ±1%.
Wide input voltage range
– 6.5V to 28V
4A continuous output current
Output voltage adjustable down to 0.8V (±1.0%)
Low RDS(ON) internal NFETs
The AOZ2151TQI-19 integrates an internal linear
regulator to generate 5.3V VCC from input. If input
voltage is lower than 5.3V, the linear regulator operates
at low drop output mode, which allows the VCC voltage is
equal to input voltage minus the drop-output voltage of
the internal linear regulator.
– 28m high-side
– 28m low-side
Constant On-Time with input feed-forward
Ceramic capacitor stable
Adjustable soft start
A proprietary constant on-time PWM control with input
feed-forward results in ultra-fast transient response while
maintaining relatively constant switching frequency over
the entire input voltage range.
Power Good output
The device features multiple protection functions such as
VCC under-voltage lockout, cycle-by-cycle current limit,
output over-voltage protection, short-circuit protection,
and thermal shutdown.
Thermal shutdown
Integrated bootstrap diode
Cycle-by-cycle current limit
Short-circuit protection
Force PWM operation
Thermally enhanced 3mm x 3mm QFN-18L package
Applications
The AOZ2151TQI-19 is available in a 3mm×3mm QFN18L package and is rated over a -40°C to +85°C ambient
temperature range.
Compact desktop PCs
Graphics cards
Set-top boxes
LCD TVs
Cable modems
Point-of-load DC/DC converters
Telecom/Networking/Datacom equipment
Typical Application
Input V oltage
6.5V to 28 V
C2
22 µF
IN
5V
R3
100 kO hm
C4
4.7µF
P ow er G ood
O ff
VCC
A O Z 215 1T Q I-19
PGOOD
On
BST
EN
LX
C5
0 .1µF
L1
2.2 µH
O utput5 V ,
4A
R2
FB
R1
CSS
SS
C3
88 µF
AGND
PGND
A nalog G round
P ow er G round
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AOZ2151TQI-19
Output Voltage vs. Operating Frequency
Operating Frequency (kHz)
1,000
900
800
700
600
AOZ2152TQI-19
500
400
300
200
1
2
3
4
5
6
7
8
9
10
11
12
Output Voltage (V)
Recommended Start-up Sequence
VIN
EN
50µs
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Page 2 of 17
AOZ2151TQI-19
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ2151TQI-19
-40°C to +85°C
18-Pin 3mm x 3mm QFN
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
SS
VCC
BST
EN
18
17
16
15
PGOOD
1
14
LX
FB
2
13
LX
AGND
3
12
PGND
IN
4
11
PGND
IN
5
10
PGND
6
7
8
9
IN
IN
LX
LX
IN
IN
18-Pin 3mm x 3mm QFN
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1
PGOOD
Power Good Signal Output. PGOOD is an open-drain output used to indicate the status
of the output voltage. It is internally pulled low when the output voltage is 15% lower than
the nominal regulation voltage or 20% higher than the nominal regulation voltage.
PGOOD is pulled low during soft-start and shut down.
2
FB
Feedback Input. Adjust the output voltage with a resistive voltage-divider between the
regulator’s output and AGND.
3
AGND
4, 5, 6, 7, 8
IN
Supply Input. IN is the regulator input. All IN pins must be connected together.
9, 13, 14
LX
Switching Node.
10, 11, 12
PGND
Power Ground.
15
EN
Rev 1.0 August 2017
Analog Ground.
Enable Input. The AOZ2151TQI-19 is enabled when EN is pulled high. The device shuts
down when EN is pulled low.
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AOZ2151TQI-19
Pin Number
Pin Name
16
BST
Bootstrap Capacitor Connection. The AOZ2151TQI-19 includes an internal bootstrap
diode. Connect an external capacitor between BST and LX as shown in the Typical
Application diagram.
17
VCC
Supply Input for analog functions. Bypass VCC to AGND with a 4.7µF~10µF ceramic
capacitor. Place the capacitor close to VCC pin.
18
SS
Rev 1.0 August 2017
Pin Function
Soft-Start Time Setting Pin. Connect a capacitor between SS and AGND to set the
soft-start time.
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AOZ2151TQI-19
Absolute Maximum Ratings
Maximum Operating Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the
Maximum Operating ratings.
Parameter
Rating
IN to AGND
Parameter
-0.3V to 30V
Supply Voltage (VIN)
LX to AGND
-0.3V to 30V
Output Voltage Range
BST to AGND
-0.3V to 36V
Ambient Temperature (TA)
(1)
SS, PGOOD, FB, EN, VCC to AGND
-0.3V to +0.3V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating(2)
6.5V to 28V
0.8V to 0.85*VIN
-40°C to +85°C
Package Thermal Resistance
JA
JC
-0.3V to 6V
PGND to AGND
Rating
40°C/W
6°C/W
2kV
Notes:
1. LX to PGND
Transient (t 2V, PFM
IOFF
Shutdown Supply Current
VEN = 0V
VFB
Feedback Voltage
TA = 25°C
TA = 0°C to 85°C
IFB
Min.
3.2
0.792
0.788
4.0
3.7
Max
Units
28
V
4.4
V
0.16
mA
15
A
0.800
0.800
0.808
0.812
V
Load Regulation
0.5
%
Line Regulation
1
%
FB Input Bias Current
200
nA
Enable
Off threshold
On threshold
0.5
VEN
EN Input Threshold
VEN_HYS
EN Input Hysteresis
100
mV
TON_MIN
Minimum On Time
60
ns
TOFF_MIN
Minimum Off Time
300
ns
1.4
V
Modulator
Soft-Start
ISS_OUT
SS Source Current
Rev 1.0 August 2017
VSS = 0
CSS = 0.001F to 0.1F
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7
11
15
A
Page 5 of 17
AOZ2151TQI-19
Electrical Characteristics
TA = 25°C, VIN=12V, EN = 5V, unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
Power Good Signal
VPG_LOW
PGOOD Low Voltage
IOL = 1mA
PGOOD Leakage Current
0.5
V
±1
A
VPGH
PGOOD Threshold
(Low Level to High Level)
FB rising
90
VPGL
PGOOD Threshold
(High Level to Low Level)
FB rising
FB falling
120
85
%
5
%
PGOOD Threshold Hysteresis
%
Under Voltage and Over Voltage Protection
VPL
Under Voltage Threshold
TPL
Under Voltage Delay Time
VPH
Over Voltage Threshold
FB falling
70
%
32
s
FB rising
120
%
28
Power Stage Output
RDS(ON)
RDS(ON)
High-Side NFET On-Resistance
VIN = 12V
High-Side NFET Leakage
VEN = 0V, VLX = 0V
Low-Side NFET On-Resistance
VLX = 12V
Low-Side NFET Leakage
VEN = 0V
m
10
28
A
m
10
A
Over-current and Thermal Protection
ILIM
Current Limit
Thermal Shutdown Threshold
Rev 1.0 August 2017
6
TJ rising
TJ falling
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A
150
100
°C
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AOZ2151TQI-19
Functional Block Diagram
BST
IN
PGood
LDO
VCC
EN
UVLO
Reference
& Bias
TOFF_MIN
Q
Timer
Error Comp
0.8V
SS
FB
ISENSE
(AC)
PG Logic
S
Q
R
FB
Decode
LX
ILIM Comp
ILIM
Current
Information
Processing
ISENSE
OTP
Timer
Light Load
Comp
Light Load
Threshold
EN
ISENSE
PGND
Rev 1.0 August 2017
ISENSE (AC)
Vcc
TON
Q
ISENSE (DC)
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AGND
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AOZ2151TQI-19
Typical Performance Characteristics
Circuit of Typical Application. TA = 25°C, VIN = 19V, VOUT = 5V, unless otherwise specified.
Load Transient 0A to 4A
Normal Operation
VLX
(20V/div)
ILX
(5A/div)
ILX
(5A/div)
V O ripple
(50mV/div)
V O ripple
(200mV/div)
500µs/div
10µs/div
Full Load Start-up
Short Circuit Protection
VLX
(20V/div)
VLX
(20V/div)
EN
(5V/div)
ILX
(10A/div)
ILX
(10A/div)
VO
(2V/div)
VO
(5V/div)
10µs/div
1ms/div
Efficiency vs. Load Current
100
90
VOUT = 5V
80
Efficiency (%)
70
60
50
40
Vin = 6.5V
30
Vin = 12V
20
Vin = 19V
10
Vin = 24V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
Output Current (A)
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AOZ2151TQI-19
Detailed Description
The AOZ2151TQI-19 is a high-efficiency, easy-to-use,
synchronous buck regulator optimized for notebook
computers. The regulator is capable of supplying 4A of
continuous output current with an output voltage
adjustable down to 0.8V.
The input voltage of AOZ2151TQI-19 can be as low as
6.5V. The highest input voltage of AOZ2151TQI-19 can
be 28V. Constant on-time PWM with input feed-forward
control scheme results in ultra-fast transient response
while maintaining relatively constant switching frequency
over the entire input range. True AC current mode control
scheme guarantees the regulator can be stable with
ceramics output capacitor. Protection features include
VCC under-voltage lockout, current limit, output over
voltage and under voltage protection, short-circuit
protection, and thermal shutdown.
The AOZ2151TQI-19 is available in 18-pin 3mmx3mm
QFN package.
VOUT
VSS
VSS = 3.3V
VSS = 0.8V
PGOOD
Figure 1. Soft Start Sequence
Enable
The AOZ2151TQI-19 has an embedded discharge path,
including a 100kΩ resistor and an M1 NMOS device. This
discharge path is activated when VIN(Input Voltage) is
high and VEN(Enable Voltage) is low. The internal circuit
of EN pin is shown in Figure 2.
VS
Input Power Architecture
The AOZ2151TQI-19 integrates an internal linear
regulator to generate 5.3V (±5%) VCC from input. If input
voltage is lower than 5.3V, the linear regulator operates
at low drop-output mode; the VCC voltage is equal to
input voltage minus the drop-output voltage of internal
linear regulator.
R1
VEN
VIN
EN
Detection
EN
REN_PL
100k
R2
Soft Start
The AOZ2151TQI-19 has external soft start feature to
limit in-rush current and ensure the output voltage ramps
up smoothly to regulation voltage. A soft start process
begins when VCC rises to 4.5V and voltage on EN pin is
HIGH. An internal current source charges the external
soft-start capacitor; the FB voltage follows the voltage of
soft-start pin (VSS) when it is lower than 0.8V. When VSS
is higher than 0.8V, the FB voltage is regulated by
internal precise band-gap voltage (0.8V). When VSS is
higher than 3.3V, the PGOOD signal is high. The softstart time for PGOOD can be calculated by the following
formula:
TSS(s) = 330 x CSS(nF)
If CSS is 1nF, the soft-start time will be 330µ second; if
CSS is 10nF, the soft-start time will be 3.3m second.
EN1
EN Signal
EN1
M1
AGND
Figure 2. Enable Internal Circuit
There are two different enable control methods:
1. Connection to EN pin by an external resistor divider.
2. Direct connection to EN pin by an external power
source, Vs.
In the first condition, we must consider the internal pull
down resistance by using a divider circuit with an external
power source Vs and get VEN, the VEN can be calculated
by the following formula:
Ven
R2 // REN _ PL
R1 ( R2 // REN PL )
• Vs
When the VIN is high and VEN is high, the EN internal M1
is turned off, and then the pull down resistance is
removed for VEN, the VEN can be re-calculated by:
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AOZ2151TQI-19
Ven
R2
• Vs
R1 R2
In the second condition, the AOZ2151TQI-19 will be
turned on when the VEN is higher than 1.4V, and will be
turned off when the VEN is lower than 0.5V. The simplified
schematic and timing sequence are shown in Figure 3.
1.4V
Hysteresis
0. 3V
EN pin
0.5V
EN pin
EN
1.05V
EN
Figure 3. Enable Threshold Schematic and Timing
Sequence
Constant-On-Time PWM Control with Input
Feed-Forward
The control algorithm of AOZ2151TQI-19 is constant-ontime PWM control with input feed-forward. The simplified
control schematic is shown in Figure 4. The high-side
switch on-time is determined solely by a one-shot whose
pulse width is inversely proportional to input voltage (IN).
The one-shot is triggered when the internal 0.8V is higher
than the combined information of FB voltage and the AC
current information of inductor, which is processed and
obtained through the sensed lower-side MOSFET current
once it turns-on. The added AC current information can
help the stability of constant-on time control even with
pure ceramic output capacitors, which have very low
ESR. The AC current information has no DC offset, which
does not cause offset with output load change, which is
fundamentally different from other V2 constant-on time
control schemes.
–
Programmable
One-Shot
Current-Limit Protection
The AOZ2151TQI-19 has the current-limit protection by
using RDS(ON) of the low-side MOSFET to be as current
sensing. To detect real current information, a minimum
constant off (300ns typical) is implemented after a
constant-on time. If the current exceeds the current-limit
threshold, the PWM controller is not allowed to initiate a
new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit
characteristic and maximum load capability are a function
of the inductor value and input and output voltages. The
current limit will keep the low-side MOSFET on and will
not allow another high-side on-time, until the current in
the low-side MOSFET reduces below the current limit.
After 8 switching cycles, the AOZ2151TQI-19 considers
this is a true failed condition and thus turns-off both highside and low-side MOSFETs and shuts down. The
AOZ2151TQI-19 enters hiccup mode to periodically
restart the part. When the current limit protection is
removed, the AOZ2151TQI-19 exits hiccup mode.
Inductor Current
Feedback Voltage
LX Voltage
-0.7V
Output Voltage
IN
PWM
constant-on-time control is significantly improved even
without the help of output capacitor’s ESR; and thus, the
pure ceramic capacitor solution can be applicant. The
pure ceramic capacitor solution can significantly reduce
the output ripple (no ESR caused overshoot and
undershoot) and less board area design.
FB Voltage/AC
Current Information
Comp
+
0.8V
VCC Voltage
Figure 4. Simplified Control Schematic
True Current Mode Control
The constant-on-time control scheme is intrinsically
unstable if output capacitor’s ESR is not large enough as
an effective current-sense resistor. Ceramic capacitors
usually cannot be used as output capacitor.
The AOZ2151TQI-19 senses the low-side MOSFET
current and processes it into DC current and AC current
information using AOS proprietary technique. The AC
current information is decoded and added on the FB pin
on phase. With AC current information, the stability of
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Soft-Start Voltage
Figure 5. OCP Timing Chart
Page 10 of 17
AOZ2151TQI-19
Output Voltage Under-voltage Protection
Application Information
If the output voltage is lower than 70% by over-current or
short circuit, AOZ2151TQI-19 will wait for 32µs (typical)
and turns-off both high-side and low-side MOSFETs
shuts down. The AOZ2151TQI-19 enters hiccup mode to
periodically restart the part. When the current limit
protection is removed, the AOZ2151TQI-19 exits hiccup
mode.
The basic AOZ2151TQI-19 application circuit is shown in
the Typical Application section. The component selection
is explained below.
Output Voltage Over-voltage Protection
The threshold of OVP is set 20% higher than 800mV.
When the VFB voltage exceeds the OVP threshold, highside MOSFET is turned off and low-side MOSFET is
turned on until VFB voltage is lower than 800mV.
The input capacitor must be connected to the IN pins and
PGND pin of the AOZ2151TQI-19 to maintain steady
input voltage and filter out the pulsing input current. A
small decoupling capacitor, usually 4.7µF, should be
connected to the VCC pin and AGND pin for stable
operation of the AOZ2151TQI-19. The voltage rating of
input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
OVP Threshold
Feedback Voltage
VO VO
IO
V IN = ----------------- 1 – --------- --------V IN V IN
f C IN
Inductor Current
LX Voltage
Input capacitor
VIN+0.7V
Output Voltage
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
VO
VO
I CIN_RMS = I O --------- 1 – ---------
V IN
V IN
VCC Voltage
if let m equal the conversion ratio:
VO
-------- = m
V IN
Soft-Start Voltage
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 7. It can be seen that when VO is half of VIN, CIN it
is under the worst current stress. The worst current
stress on CIN is 0.5 x IO.
Figure 6. OVP Timing Chart
Power Good Output
0.5
The power good (PGOOD) output, which is an open
drain output, requires the pull-up resistor. When the
output voltage is 15% below than the nominal regulation
voltage for, the PGOOD is pulled low. When the output
voltage is 20% higher than the nominal regulation
voltage, the PGOOD is also pull low.
0.4
ICIN_RMS(m) 0.3
IO
0.2
0.1
When combined with the under-voltage-protection circuit,
this current-limit method is effective in almost every
circumstance.
0
0
0.5
m
1
Figure 7. ICIN vs. Voltage Conversion Ratio
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AOZ2151TQI-19
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN-RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used. When
selecting ceramic capacitors, X5R or X7R type dielectric
ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
VO
VO
I L = ----------- 1 – ---------
V IN
fL
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
V O = I L ESR CO + -------------------------
8fC
O
where, CO is output capacitor value and ESRCO is the
Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified to:
The peak inductor current is:
I L
I Lpeak = I O + -------2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 30% to
50% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
1
V O = I L ------------------------8fC
O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
V O = I L ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
I L
I CO_RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed.
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AOZ2151TQI-19
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor and
output current.
Thermal Management and Layout
Consideration
In the AOZ2151TQI-19 buck regulator circuit, high
pulsing current flows through two circuit loops. The first
loop starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low side switch.
Current flows in the second loop when the low side low
side switch is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ2151TQI-19.
In the AOZ2151TQI-19 buck regulator circuit, the major
power dissipating components are the AOZ2151TQI-19
and the output inductor. The total power dissipation of
converter circuit can be measured by input power minus
output power.
P inductor_loss = IO2 R inductor 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ2151TQI-19 and thermal
impedance from junction to ambient.
T junction ( Ptotal _ loss Pinductor _ loss ) JA TA
The maximum junction temperature of AOZ2151TQI-19
is 150ºC, which limits the maximum load current
capability.
The thermal performance of the AOZ2151TQI-19 is
strongly affected by the PCB layout. Extra care should be
taken by users during design process to ensure that the
IC will operate under the recommended environmental
conditions.
P total_loss = V IN I IN – V O I O
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AOZ2151TQI-19
3. Input capacitors should be connected to the IN pin
and the PGND pin as close as possible to reduce the
switching spikes.
Layout Considerations
Several layout tips are listed below for the best electric
and thermal performance.
4. Decoupling capacitor CVCC should be connected to
VCC and AGND as close as possible.
1. The LX pins and pad are connected to internal low
side switch drain. They are low resistance thermal
conduction path and most noisy switching node.
Connected a large copper plane to LX pin to help
thermal dissipation.
5. Voltage divider R1 and R2 should be placed as close
as possible to FB and AGND.
6. Keep sensitive signal traces such as feedback trace
far away from the LX pins.
2. The IN pins and pad are connected to internal high
side switch drain. They are also low resistance
thermal conduction path. Connected a large copper
plane to IN pins to help thermal dissipation.
7. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
CVCC
SS
VCC
BST
EN
18
17
16
15
1
14
LX
FB
2
13
LX
AGND
3
12
PGND
IN
4
11
PGND
IN
5
10
PGND
7
8
9
IN
IN
LX
LX
6
IN
IN
VOUT
PGOOD
VOUT
Cout
PGND
VIN
Cin
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AOZ2151TQI-19
Package Dimensions, QFN 3x3, 18 Lead EP2_S
TOP VIEW
BOTTOM VIEW
SIDE VIEW
SYMBOLS
RECOMMENDED LAND PATTERN
A
A1
A2
E
DIMENSIONS IN INCHES
MIN
NOM
MAX
MIN
NOM
MAX
0.45
0.10
0.55
0.15
0.9
0.25
0 .018
0.00
0.022
0.026
0 .008
2.90
0.020REF
3.00
3.10
0.114
0.001REF
0.118
0.122
E1
E2
1.82
1.92
2.02
0.072
0.076
0.080
1.74
1.84
1.94
0.069
0.072
0.076
E3
E4
0.17
0.21
0.31
0.007
0.008
0.012
0.17
0.21
0.31
0.007
0.008
0.012
E5
E6
0.75
0.35
0.85
0.40
0.95
0.45
0.030
0.014
0.033
0.016
0.037
0.018
E7
E8
1.10
0.49
1.20
0.54
1.30
0.59
0.043
0.019
0.047
0.021
0.051
0.023
E9
D
0.51
0.56
0.61
0.020
0.022
0.024
D1
2.90
0.15
3.00
0.20
3.10
0.25
0.114
0.006
0.118
0.008
0.122
0.010
D2
0.45
0.50
0.55
0.01
0.02
0.022
L
0.25
0.30
0.35
0.010
0.012
0.014
L1
0.90
1.00
1.10
0.035
0.039
0.043
L2
L3
0.35
0.40
0.45
0.014
0.016
0.018
0.80
1.26
0.90
1.36
1.00
1.46
0.031
0.05
0.035
0.05
0.039
0.057
L5
L6
0.64
0.69
0.74
0.025
0.027
0.029
0.35
0.40
0.45
0.014
0.016
0.018
L7
0.55
0.60
0.65
0.022
0.024
0.026
L8
b
0.35
0.27
0.40
0.32
0.45
0.37
0.014
0.011
0.016
0.013
0.018
0.015
L4
UNIT: mm
DIMENSIONS IN MILLIMETERS
NOTE
CONTROLLING DIMENSIONS IS MILLIMETER.
CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT.
Rev 1.0 August 2017
www.aosmd.com
Page 15 of 17
AOZ2151TQI-19
Tape and Reel Dimensions, QFN 3x3, 18 Lead EP2_S
Carrier Tape
Reel
Leader/Trailer & Orientation
Rev 1.0 August 2017
www.aosmd.com
Page 16 of 17
AOZ2151TQI-19
Part Marking
AOZ22151TQI-19
(QFN 3x3)
ABTL
Part Number Code
YWLT
Option Code
Assembly Lot Code
Year & Week Code
LEGAL DISCLAIMER
Applications or uses as critical components in life support devices or systems are not authorized. AOS does not
assume any liability arising out of such applications or uses of its products. AOS reserves the right to make
changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the
product for their intended application. Customer shall comply with applicable legal requirements, including all
applicable export control rules, regulations and limitations.
AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:
http://www.aosmd.com/terms_and_conditions_of_sale
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev 1.0 August 2017
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 17 of 17
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