PA119CEA

PA119CE • PA119CEA Video Power Operational Amplifier RoHS COMPLIANT FEATURES • • • • • Very Fast Slew Rate — 900 V/µs Power MOS Technology — 4A peak rating Low Internal Losses — 0.75 V at 2A Protected Output Stage — Thermal Shutoff Wide Supply Range — ±15 V to ±40 V APPLICATIONS • • • • • Video Distribution And Amplification High Speed Deflection Circuits Power Transducers up to 5 MHz Modulation of Rf Power Stages Power LED or Laser Diode Excitation DESCRIPTION The PA119 is a high voltage, high current operational amplifier optimized to drive a variety of loads from DC through the video frequency range. Excellent input accuracy is achieved with a dual monolithic FET input transistor which is cascaded by two high voltage transistors to provide outstanding common mode characteristics. All internal current and voltage levels are referenced to a zener diode biased on by a current source. As a result, the PA119 exhibits superior DC and AC stability over a wide supply and temperature range. High speed and freedom from second breakdown is assured by a complementary power MOS output stage. For optimum linearity, especially at low levels, the power MOS transistors are biased in a class A/B mode. Thermal shutoff provides full protection against overheating and limits the heatsink requirements to dissipate the internal power losses under normal operating conditions. A built-in current limit of 0.5A can be increased with the addition of two external resistors. Transient inductive load kickback protection is provided by two internal clamping diodes. External phase compensation allows the user maximum flexibility in obtaining the optimum slew rate and gain bandwidth product at all gain settings. A heatsink of proper rating is recommended. This hybrid circuit utilizes thick film (cermet) resistors, ceramic capacitors, and silicon semiconductor chips to maximize reliability, minimize size, and give top performance. Ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. The 8-pin TO-3 package is hermetically sealed and electrically isolated. The use of compressible thermal washers and/or improper mounting torque will void the product warranty. Please see Application Note 1 “General Operating Considerations.” www.apexanalog.com © Apex Microtechnology Inc. All rights reserved Aug 2021 PA119U Rev J PA119CE • PA119CEA Figure 1: Equivalent Schematic 3 Q1 Q2 Q4 Q3 2 Q7 Q5 Q8 8 Q9 Q10 Q11 Q15 Q13 Q12 Q16 1 D1 Q19 Q20 5 Q17A Q17B Q21 4 Q22 Q23 Q24 D2 7 Q25 6 2 PA119U Rev J PA119CE • PA119CEA TYPICAL CONNECTION Figure 2: Typical Connection PA119U Rev J 3 PA119CE • PA119CEA PINOUT AND DESCRIPTION TABLE Figure 3: External Connections 4 Pin Number Name Description 1 OUT 2 +CL The output. Connect this pin to load and to the feedback resistors. Connect to the sourcing current limit resistor, and then the +Vs pin. Power supply current flows into this pin through RCL+. 3 4 5 6 +Vs +IN -IN -Vs 7 -CL 8 CC The positive supply rail. The non-inverting input. The inverting input. The negative supply rail. Connect to the sinking current limit resistor, and then the -Vs pin. Power supply current flows out of this pin through RCL-. Compensation capacitor connection. Select value based on Phase Compensation. See applicable section. PA119U Rev J PA119CE • PA119CEA SPECIFICATIONS Unless otherwise noted: TC = 25°C, DC input specifications are ± value given. Power supply voltage is typical rating. RC = 100, CC = 220pF. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Max Units +Vs to -Vs 80 V Output Current, within SOA IO 5 A Power Dissipation, internal PD 75 W Input Voltage, differential VIN (Diff) 40 V +VS V 350 °C 175 °C -65 +150 °C -55 +125 °C Supply Voltage, total Min Vcm Input Voltage, common mode -VS Temperature, pin solder, 10s Temperature, junction Temperature, storage TJ 1 TC Operating Temperature Range, case 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF. CAUTION The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes. INPUT Parameter Test Conditions PA119 Min PA119A Typ Max ±0.5 Min Units Typ Max ±3 ±0.35 ±0.75 mV 30 5 15 µV/°C Offset Voltage, initial TC = 25°C Offset Voltage vs. temperature TC=25°C to 85°C 10 Offset Voltage vs. supply TC = 25°C 10 * µV/V Offset Voltage vs. power TC=25°C to 85°C 20 * µV/W Bias Current, initial TC = 25°C 10 Bias Current vs. supply TC = 25°C 0.01 Offset Current, initial TC = 25°C 5 Input Impedance, DC TC = 25°C 1011 * Ω Input Capacitance TC = 25°C 6 * pF Common Mode Voltage Range1 TC=25°C to 85°C ±VS–15 ±VS–12 * * V Common Mode Rejection, DC TC=25°C to 85°C VCM = ±20V * * dB 70 104 200 5 50 * 100 3 pA pA/V 25 pA 1. +VS and –VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to –VS. PA119U Rev J 5 PA119CE • PA119CEA GAIN Parameter Test Conditions Open Loop Gain at 10 Hz TC = 25°C, RL = 1 kΩ Open Loop Gain at 10 Hz TC = 25°C, RL = 15 Ω Gain Bandwidth Product @ 1 MHz TC = 25°C, CC = 2.2pF Power Bandwidth, AV = 100 Power Bandwidth, AV = 1 PA119 Min Typ PA119A Max Min 111 Typ Max Units * dB * dB 100 * MHz TC = 25°C, CC = 2.2pF 3.5 * MHz TC = 25°C, CC = 330pF 250 * kHz PA119 PA119A 74 88 * OUTPUT Parameter Test Conditions Min Typ Max Min Typ Max Units Voltage Swing 1 TC=25°C, IO = 4A ±VS–5 ±VS–1.5 * * V Voltage Swing 1 TC=25°C to 85°C, ±VS–3 ±VS–.75 IO = 2A * * V Voltage Swing 1 TC=25°C to 85°C, ±VS–1 IO = 78mA * * V Settling Time to 0.1% TC=25°C, 2V step 0.3 * µs Settling Time to 0.01% TC=25°C, 2V step 1.2 * µs Slew Rate, AV = 100 TC = 25°C, CC = 2.2pF * V/µs Slew Rate, AV = 10 TC = 25°C, CC = 22pF * V/µs 600 ±VS–.5 900 750 650 1. +VS and –VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to –VS. POWER SUPPLY PA119 PA119A Test Conditions Min Typ Max Min Typ Max Voltage TC=25°C to 85°C ±15 ±35 ±40 * * * Current, quiescent TC = 25°C 100 120 * * Parameter 6 Units V mA PA119U Rev J PA119CE • PA119CEA THERMAL Parameter Resistance, AC, junction to case1 Resistance, DC, junction to case Resistance, junction to air Temperature Range, case Test Conditions PA119 Min TC=25°C to 85°C, F > 60 Hz TC=25°C to 85°C, F < 60 Hz TC=25°C to 85°C Meets full range specs PA119A Typ Max 1.46 1.84 Min Max 1.64 * * °C/W 2.0 * * °C/W 30 -25 Units Typ °C/W * +85 * * °C 1. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz. Note: * The specification of PA119A is identical to the specification for PA119 in applicable column to the left. PA119U Rev J 7 PA119CE • PA119CEA TYPICAL PERFORMANCE GRAPHS Figure 5: Current Limit 80 3.5 70 3.0 60 Current Limit, ILIM (A) /ŶƚĞƌŶĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ͕W;t) Figure 4: Power Derating 50 40 30 20 сϬ ͘Ϯϳ ɏ 2.5 2.0 1.5 RCL сϭ͘Ϯ ɏ 1.0 RCL = ь 10 0 25 50 75 100 125 0 -50 150 Case Temperature, TC (°C) 25 50 75 100 125 Figure 7: Small Signal Response 1.6 100 80 Open Loop Gain, AOL (dB) 1.4 1.2 1.0 0.8 0.6 30 0 -25 Case Temperature, TC (°C) Figure 6: Quiescent Current Normalized Quiescent Current, IQ (X) CL 0.5 0 40 50 60 70 Total Supply Voltage, VS (V) 8 R 80 60 2. 2p F 40 22 pF 33 0p 20 F 0 -20 100 1k 10k 100k 1M 10M 100M Frequency, F (Hz) PA119U Rev J PA119CE • PA119CEA Figure 8: Output Voltage Swing Figure 9: Power Response 80 58 Output Voltage, VO (VP-P) 15 11 |+V|+|–VS| = 80V 8 100k 200k 600k 1M 2M 0.5 0 1 2 3 4 5 Output Current, IO (A) 30 ZLсϭϱɏ 400 200 100 80 VIN = 2V AV = 10 tr = 10ns RLсϭϱё 20 Output Voltage, VO (V) 600 10 0 -10 -20 40 4 6 10 20 40 60 100 200 400 ŽŵƉĞŶƐĂƟŽŶĂƉĂĐŝƚŽƌ͕C;pF) PA119U Rev J 8M 20M Figure 11: Pulse Response 1000 800 2 4M Frequency, F (Hz) Figure 10: Slew Rate vs. Comp. ^ůĞǁZĂƚĞ;sͬʅƐͿ F 22p pF 21 pF 2.2 30 C C= –V RLсϭϱɏ 330 1.0 41 C C= +V CC= Voltage Drop From Supply (V) 1.5 -30 -50 0 50 100 150 200 250 300 Time, t (ns) 9 PA119CE • PA119CEA Figure 12: Input Noise Figure 13: Common Mode Rejection 120 ŽŵŵŽŶDŽĚĞZĞũĞĐƟŽŶ͕DZ;ĚͿ Input Noise Voltage, VN;Ŷsͬя,nj) 30 20 15 10 7 5 3 10 100 80 60 40 20 100 1k 10k 100k 1M 1k 10k Figure 14: Power Supply Rejection 10M 100M Figure 15: Common Mode Voltage 70 Common Mode Voltage, VCM (VP-P) 100 WŽǁĞƌ^ƵƉƉůLJZĞũĞĐƟŽŶ͕W^Z;Ě) 1M Frequency, F (Hz) Frequency, F (Hz) 80 60 40 20 65 60 55 50 45 40 0 1k 10k 100k 1M Frequency, F (Hz) 10 100k 10M 100M 10 100 1k 10k 100k 1M 10M Frequency, F (Hz) PA119U Rev J PA119CE • PA119CEA SAFE OPERATING AREA (SOA) The MOSFET output stage of this power operational amplifier has two distinct limitations: 1. The current handling capability of the MOSFET geometry and the wire bonds. 2. The junction temperature of the output MOSFETs. Figure 16: SOA 5 ƚс 4 ϬϬ ŵ ϯ 3 ϬϬ ŵ Ɛ Ɛ Ğ Ăƚ ^ƚ ĚLJ 2 1 ϭ ƚс ĞĂ ^ƚ KƵƚƉƵƚƵƌƌĞŶƚ&ƌŽŵнVSŽƌͲVS (A) 10 TC=25°C 10 20 30 40 50 80 100 ^ƵƉƉůLJƚŽKƵƚƉƵƚŝīĞƌĞŶƟĂů͕VS- VO (V) The SOA curves combine the effect of these limits and allow for internal thermal delays. For a given application, the direction and magnitude of the output current should be calculated or measured and checked against the SOA curves. This is simple for resistive loads but more complex for reactive and EMF generating loads. The following guidelines may save extensive analytical efforts: 1. Capacitive and inductive loads up to the following maximums are safe: ±VS Capacitive Load Inductive Load 40 V 30 V 20 V 15 V 0.1µF 500µF 2500µF ∞ 11 mH 24 mH 75 mH 100 mH 2. Safe short circuit combinations of voltage and current are limited to a power level of 100W. 3. The output stage is protected against transient flyback. However, for protection against sustained, high energy flyback, external fast-recovery diodes should be used. PA119U Rev J 11 PA119CE • PA119CEA GENERAL Please read Application Note 1 “General Operating Considerations” which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.apexanalog.com for Apex Microtechnology’s complete Application Notes library, Technical Seminar Workbook, and Evaluation Kits. TYPICAL APPLICATION This fast power driver utilizes the 900V/µs slew rate of the PA119 and provides a unique interface with a current output DAC. By using the DAC’s internal 1 kΩ feedback resistor, temperature drift errors are minimized, since the temperature drift coefficients of the internal current source and the internal feedback resistor of the DAC are closely matched. Gain of VOUT to IIN is –6.5/ mA. The DAC’s internal 1k resistor together with the external 500 Ω and 110 Ω form a “tee network” in the feedback path around the PA119. This effective resistance equals 6.5 kΩ. Therefore the entire circuit can be modeled as 6.5 kΩ feedback resistor from output to inverting input and a 5mA current source into the inverting input of the PA119. Now we see the familiar current to voltage conversion for a DAC where VOUT = –IIN x RFEEDBACK Figure 17: Typical Application ϭϭϬё +40V RCL+ ϱϬϬё 1K DAC ±5mA ±32.5V PA119 RCL- hƉƚŽϰ 5.6pF -40V WϭϭϵĂƐĂ&ĂƐƚWŽǁĞƌƌŝǀĞƌ CURRENT LIMIT Q2 (and Q25) limit output current by turning on and removing gate drive when voltage on pin 2 (pin 7) exceeds 0.65V differential from the positive (negative) supply rail. With internal resistors equal to 1.2 Ω, current limits are approximately 0.5A with no external current limit resistors. With the addition of external resistors current limit will be: To determine values of external current limit resistors: 0.65V I LIM  A  = ------------------- + 0.54A R CL    0.65V R CL    = ------------------------------------I CL  A  – 0.54A 12 PA119U Rev J PA119CE • PA119CEA PHASE COMPENSATION At low gain settings, an external compensation capacitor is required to insure stability. In addition to the resistive feedback network, roll off or integrating capacitors must also be considered when determining gain settings. The capacitance values listed in the external connection diagram, along with good high frequency layout practice, will insure stability. Interpolate values for intermediate gain settings. SUPPLY CURRENT The PA119 features a class A/B driver stage to charge and discharge gate capacitance of Q7 and Q19. As these currents approach 0.5A, the savings of quiescent current over that of a class A driver stage is considerable. However, supply current drawn by the PA119, even with no load, varies with slew rate of the output signal as shown below. Figure 18: Supply Current Supply Current, IS (mA) 400 VOUT = 60VP-P SINE RL = 500 Ω 300 200 100 0 30K 100K 300K 1M 3M Frequency, F (Hz) 10M OUTPUT LEADS Keep the output leads as short as possible. In the video frequency range, even a few inches of wire have significant inductances, raising the interconnection impedance and limiting the output current slew rate. Furthermore, the skin effect increases the resistance of heavy wires at high frequencies. Multistrand Litz Wire is recommended to carry large video currents with low losses. THERMAL SHUTDOWN The thermal protection circuit shuts off the amplifier when the substrate temperature exceeds approximately 150°C. This allows the heatsink selection to be based on normal operating conditions while protecting the amplifier against excessive junction temperature during temporary fault conditions. Thermal protection is a fairly slow-acting circuit and therefore does not protect the amplifier against transient SOA violations (areas outside of the steady state boundary). It is designed to protect against shortterm fault conditions that result in high power dissipation within the amplifier. If the conditions that cause thermal shutdown are not removed, the amplifier will oscillate in and out of shutdown. This will result in high peak power stresses, destroy signal integrity, and reduce the reliability of the device. PA119U Rev J 13 PA119CE • PA119CEA STABILITY Due to its large bandwidth, the PA119 is more likely to oscillate than lower bandwidth power operational amplifiers. To prevent oscillations a reasonable phase margin must be maintained by: 1. Selection of the proper phase compensation capacitor. Use the values given in the table under external connections and interpolate if necessary. The phase margin can be increased by using a larger capacitor at the expense of slew rate. Total physical length (pins of the PA119, capacitor leads plus printed circuit traces) should be limited to a maximum of 3.5 inches. 2. Keep the external sumpoint stray capacitance to ground at a minimum and the sumpoint load resistance (input and feedback resistors in parallel) below 500 Ω. Larger sumpoint load resistances can be used with increased phase compensation and/or by bypassing the feedback resistor. 3. Connect the case to any AC ground potential. 14 PA119U Rev J PA119CE • PA119CEA PACKAGE OPTIONS PACKAGE STYLE CE NEED TECHNICAL HELP? CONTACT APEX SUPPORT! For all Apex Microtechnology product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@apexanalog.com. International customers can also request support by contacting their local Apex Microtechnology Sales Representative. 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