ASM2012C

ASM2012C DATA SHEET 6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C. 台北市大安路一段75巷7號6F-3 TEL:886-2-27818277 FAX:886-2-27815779 http://www.aplusinc.com.tw ASM2012C ASM2012C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Description The ASM2012C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature u u u u u u u u u u u u Single power supply can operate from 2.4V through 5V Internal Program ROM: 4K x 10-bit 1 sets of 16-bit DPR can access up to 64K x 10 bits data memory space Data Registers: • 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) • Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: • PRA: 4-bit I/O Port A (2Bh) • PRB: 4-bit Output Port B (2Dh) • PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive (RM) Timer: 1 • Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 1 Rev 1.0 ASM2012C FIGURE 1.1 : Block Diagram of ASM2012C Data Bus[3:0] PCLATCH(8) PCH(8) PCL(4) PC[11:0] (ADDR[15:12]) =0000b ADDR[15:0] Stack(12) (2-Level) 0 ROM_ADDR[15:0] 1 DPR3,2,1 DPR[15:0] Program (Data) ROM ROM Latch Instruction Latch Instruction Bus [9:0] Instruction Decoder DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Instruction Bus [9:0] Accumlator (4) SRAM ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh Timer0(9) PRA(4) PRB(4) PRC(4) P1,P2,P3,P4 enter test mode One-Channel ( Voice synthesizer ) weak or strong pull-low for PRA, PRB, PRC Clock Generator Test select Power on Reset RESET pin PRA0 VDD/GND OSC P RASL(4) Reset Chip Reset Chip COUT C OUT 2 Rev 1.0 Instruction Bus [9:0] Control Signal ASM2012C FIGURE 1.2 : External ROM Map of ASM2012C PC[11:0] 12bit x 2 STACK 16-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing Program and data ROM 00080h-003FFh 00400h 00000h-00FFFh 00FFFh(4K) 00000h-0FFFFh Data ROM 0FFFFh(64Kx10-bits) 3 Rev 1.0 ASM2012C 1.2 Pin-Out ASM2012C Pin-Out PRC1 PRC0/RESET I I STI Std./O.D. STI Std./O.D. STI Std./O.D. STI Std./O.D. Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability PRA3-1 I/O PRA0/RESET I/O OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 I I O I I O I O I Std./O.D. STI Std./O.D. 1.3 Application circuit 4 Rev 1.0 ASM2012C 1.4 Bonding Diagram 19 RC3 18 RC2 17 RC1 16 RC0 15 GND2 14 VDD2 13 TEST 12 AOSC ( 64K x 10-bit ) Block ROM ASM2012C RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 ASM2012C Pad Location PAD # 1 2 3 4 5 6 7 8 9 10 PAD Name RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 X -682.16 -559.84 -437.52 -315.2 -191.28 71.12 189.52 307.92 430.24 552.56 Chip Size: PAD # -772.68 11 -772.68 12 -772.68 13 Y X=1540+80 (um), Y=1780+80 (um) PAD Name X Y RB3 667.68 -772.68 AOSC 633.56 804 TEST 432.48 804 VDD2 GND2 RC0 RC1 RC2 RC3 -772.68 -772.68 -772.68 -772.68 -772.68 -772.68 -772.68 14 15 16 17 18 19 273.16 134.68 -51.76 -248.4 -454.24 -650.88 804 804 804 804 804 804 5 Rev 1.0 ASM2012C 1.5 DC Characteristics for ASM2012C SYMBOL VDD Isb Iop PARAMETER OPERATING VOLTAGE SUPPLY CURREN T STANDBY OPERATING VDD MIN. TYP. MAX. UNIT 2.4 3 5 3 5 3 5 5 3 5 3 5 -10 -20 3 5 1 1 2 7 3 9 -5.2 -3 -8 7 20 10 20 V uA mA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) 4MHz, RM (IO ports) Fosc(3v)Fosc(2.4v) Fosc (3v) VDD=3V, Rosc=220k, 4MHz Iih INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT FREQUENCY STABILITY Fosc VARIATION uA Ioh Iol dF/F dF/F mA % % FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 330 2.68 220 4.11 Rosc & Freq. 200 4.7 150 5.94 8 Freq. MHz 6 4 2 0 0 100 200 Rosc k ohm 300 400 5.94 4.7 4.11 2.68 6 Rev 1.0