ASIX
AX88140A Fast Ethernet MAC Controller
ASIX AX88140A
100BASE-TX/FX PCI Bus Fast Ethernet MAC Controller Data Sheet(11/03/’97)
DOCUMENT NO. : AX140D2.DOC This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
AX88140A CONTENTS
PRELIMINARY
1.0 INTRODUCTION ................................................................................................................................................ 6 1.1 GENERAL DESCRIPTION: ...................................................................................................................................... 6 1.2 FEATURES ............................................................................................................................................................ 7 1.3 BLOCK DIAGRAM: ............................................................................................................................................... 8 1.4 AX88140AQ PIN CONNECTION DIAGRAM FOR 160-PIN ...................................................................................... 9 1.5 AX88140AP PIN CONNECTION DIAGRAM FOR 144-PIN .................................................................................... 10 2.0 SIGNAL DESCRIPTION .................................................................................................................................. 11 2.1 SIGNAL DESCRIPTIONS FOR 160-PIN AND 144-PIN.............................................................................................. 11 2.2 PCI INTERFACE GROUP ...................................................................................................................................... 12 2.3 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP .................................................................... 14 2.4 MII/SYM/SRL INTERFACE SIGNALS GROUP ...................................................................................................... 14 2.5 EXTENDED , NC, POWER PINS GROUP ................................................................................................................ 16 3.0 CONFIGURATION OPERATION .................................................................................................................. 17 3.1 CONFIGURATION SPACE MAPPING ..................................................................................................................... 17 3.2 CONFIGURATION SPACE ..................................................................................................................................... 18 3.2.1 Configuration ID Register (CSID)............................................................................................................ 18 3.2.2 Command and Status Configuration Register (CSCS)............................................................................... 18 3.2.3 Configuration Revision Register (CSRV).................................................................................................. 18 3.2.4 Configuration Latency Timer Register (CSLT)......................................................................................... 18 3.2.5 Configuration Base I/O Address Register (CBIO).................................................................................... 19 3.2.6 Configuration Base Memory Address Register (CBMA) .......................................................................... 19 3.2.7 Expansion ROM Base Address Register (CBER)...................................................................................... 19 3.2.8 Configuration Interrupt Register (CSIT) .................................................................................................. 19 4.0 REGISTERS OPERATION .............................................................................................................................. 20 4.1 REGISTERS MAPPING ......................................................................................................................................... 20 4.2 HOST REGS ....................................................................................................................................................... 21 4.2.1 Bus Mode Register (REG0)........................................................................................................................ 21 4.2.2 Transmit Poll Demand (REG1)................................................................................................................. 21 4.2.3 Receive Poll Demand (REG2)................................................................................................................... 22 4.2.4 Receive List Base Address (REG3) ........................................................................................................... 22 4.2.5 Transmit List Base Address (REG4) ......................................................................................................... 22 4.2.6 Status Register (REG5) ............................................................................................................................. 23 4.2.7 Operation Mode Register (REG6) ............................................................................................................ 24 4.2.8 Interrupt Enable Register (REG7) ............................................................................................................ 26 4.2.9 Missed Frame and Overflow Counter (REG8) ........................................................................................ 26 4.2.10 Serial ROM and MII Management Register (REG9).............................................................................. 27 4.2.11 General-Purpose Timer (REG11)........................................................................................................... 27 4.2.12 General-Purpose Port Register (REG12) ............................................................................................... 28 4.2.13 Filtering Index (REG13) ......................................................................................................................... 28 4.2.14 Filtering data (REG14)........................................................................................................................... 28 5.0 HOST COMMUNICATION.............................................................................................................................. 30 5.1 DESCRIPTOR LISTS AND DATA BUFFERS ............................................................................................................ 30 5.2 RECEIVE DESCRIPTORS ...................................................................................................................................... 31 5.2.1 Receive Descriptor 0 (RDES0) .................................................................................................................. 31 5.2.2 Receive Descriptor 1 (RDES1) .................................................................................................................. 32 5.2.3 Receive Descriptor 2 (RDES2) .................................................................................................................. 32 5.2.4 Receive Descriptor 3 (RDES3) .................................................................................................................. 32 5.3 TRANSMIT DESCRIPTORS ................................................................................................................................... 33 5.3.1 Transmit Descriptor 0 (TDES0)................................................................................................................. 33 5.3.2 Transmit Descriptor 1 (TDES1)................................................................................................................. 34 5.3.3 Transmit Descriptor 2 (TDES2)................................................................................................................. 34 5.3.4 Transmit Descriptor 3 (TDES3)................................................................................................................. 34 2 ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
6.0 ELECTRICAL SPECIFICATION AND TIMINGS ...................................................................................... 35 6.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 35 6.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 35 6.3 DC CHARACTERISTICS ...................................................................................................................................... 35 6.4 A.C. TIMING CHARACTERISTICS ........................................................................................................................ 36 6.4.1 PCI CLOCK .............................................................................................................................................. 36 6.4.2 PCI Timings ............................................................................................................................................... 36 6.4.3 Reset Timing .............................................................................................................................................. 36 6.4.4 MII/SYM Timing ........................................................................................................................................ 37 6.4.5 10Mbps serial timing ................................................................................................................................. 38 6.4.6 Boot ROM Read Cycles ............................................................................................................................. 39 7.0 PACKAGE INFORMATION............................................................................................................................ 40 APPENDIX A H/W NOTE .................................................................................................................................... 41 A.1 BOOT ROM READ CYCLE .................................................................................................................................. 41 A.2 POWER SUPPLY ................................................................................................................................................. 42 A.3 BOUNDARY SCAN TEST PINS ............................................................................................................................ 42 APPENDIX B FUNCTION APPLICATION ...................................................................................................... 43 B.1 APPLICATION FOR PCI INTERFACE .................................................................................................................... 43 B.2 APPLICATION FOR BOOT ROM INTERFACE ....................................................................................................... 44 B.3 APPLICATION FOR SERIAL ROM INTERFACE..................................................................................................... 44 B.4 APPLICATION FOR PHY INTERFACE .................................................................................................................. 45 B.4.1 AX88140A, QSI6611, & MTD213 Application ......................................................................................... 45 B.4.2 Application for MII Mode : LEVEL ONE LXT970.................................................................................... 45 B.4.3 Application for MII Mode : MYSON MTD972 + MTD971....................................................................... 46 B.4.4 Application for MII Mode : DAVICOM DM9101 ..................................................................................... 46
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ASIX ELECTRONICS CORPORATION
AX88140A FIGURES
PRELIMINARY
FIG - 1 AX88140A BLOCK DIAGRAM ........................................................................................................................... 8 FIG - 2 AX88140AQ PIN CONNECTION DIAGRAM FOR 160-PIN ..................................................................................... 9 FIG - 3 AX88140AP PIN CONNECTION DIAGRAM FOR 144-PIN .................................................................................... 10 FIG - 4 DESCRIPTOR STRUCTURE EXAMPLE ................................................................................................................. 30 FIG - 5 RECEIVE DESCRIPTOR FORMAT........................................................................................................................ 31 FIG - 6 TRANSMIT DESCRIPTOR FORMAT ..................................................................................................................... 33 FIG - 7 APPLICATION FOR PCS / SERIAL MODE ........................................................................................................... 45 FIG - 8 APPLICATION FOR MII MODE WITH LXT970................................................................................................... 45 FIG - 9 APPLICATION FOR MII MODE WITH MDT972 + MTD971............................................................................... 46 FIG - 10 APPLICATION FOR MII MODE WITH DM9101 ................................................................................................ 46
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ASIX ELECTRONICS CORPORATION
AX88140A TABLES
PRELIMINARY
TAB - 1 PCI INTERFACE GROUP ................................................................................................................................... 13 TAB - 2 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP ................................................................. 14 TAB - 3 MII/SYM/SRL INTERFACE SIGNALS GROUP ................................................................................................... 15 TAB - 4 EXTENDED , NC, POWER PINS GROUP ............................................................................................................. 16 TAB - 5 CONFIGURATION SPACE MAPPING .................................................................................................................. 17 TAB - 6 CSID CONFIGURATION ID REGISTER DESCRIPTION ....................................................................................... 18 TAB - 7 CSCS COMMAND AND STATUS CONFIGURATION REGISTER ........................................................................... 18 TAB - 8 CSRV CONFIGURATION REVISION REGISTER DESCRIPTION ........................................................................... 18 TAB - 9 CSLT CONFIGURATION ID REGISTER DESCRIPTION ...................................................................................... 18 TAB - 10 CBIO CONFIGURATION BASE I/O ADDRESS REGISTER DESCRIPTION .......................................................... 19 TAB - 11 CBMA CONFIGURATION BASE MEMORY ADDRESS REGISTER DESCRIPTION ............................................... 19 TAB - 12 CBER EXPANSION ROM BASE ADDRESS REGISTER DESCRIPTION .............................................................. 19 TAB - 13 CSIT CONFIGURATION INTERRUPT REGISTER DESCRIPTION ........................................................................ 19 TAB - 14 COMMAND AND STATUS REGISTER MAPPING ............................................................................................... 20 TAB - 15 REG0 BUS MODE REGISTER DESCRIPTION................................................................................................... 21 TAB - 16 REG1 TRANSMIT POLL DEMAND REGISTER DESCRIPTION ........................................................................... 21 TAB - 17 REG2 RECEIVE POLL DEMAND REGISTER DESCRIPTION .............................................................................. 22 TAB - 18 REG3 RECEIVE LIST BASE ADDRESS REGISTER DESCRIPTION ..................................................................... 22 TAB - 19 REG4 TRANSMIT LIST BASE ADDRESS REGISTER DESCRIPTION .................................................................. 22 TAB - 20 REG5 STATUS REGISTER DESCRIPTION........................................................................................................ 24 TAB - 21 REG6 OPERATION MODE REGISTER DESCRIPTION ....................................................................................... 25 TAB - 22 PORT AND DATA RATE SELECTION ............................................................................................................... 25 TAB - 23 REG7 INTERRUPT ENABLE REGISTER DESCRIPTION..................................................................................... 26 TAB - 24 REG8 MISSED FRAME AND OVERFLOW COUNTER DESCRIPTION ................................................................. 26 TAB - 25 REG9 SERIAL ROM, AND MII MANAGEMENT REGISTER DESCRIPTION ..................................................... 27 TAB - 26 REG11 GENERAL-PURPOSE TIMER REGISTER DESCRIPTION ........................................................................ 28 TAB - 27 REG12 GENERAL-PURPOSE PORT REGISTER DESCRIPTION.......................................................................... 28 TAB - 28 REG13 FILTERING INDEX REGISTER DESCRIPTION ...................................................................................... 28 TAB - 29 REG14 FILTERING DATA REGISTER DESCRIPTION ....................................................................................... 28 TAB - 30 DESCRIPTION OF FILTERING BUFFER ............................................................................................................ 28 TAB - 31 LAYOUT OF FILTERING BUFFER .................................................................................................................... 29 TAB - 32 RECEIVE DESCRIPTOR 0 ................................................................................................................................ 32 TAB - 33 RECEIVE DESCRIPTOR 1 ................................................................................................................................ 32 TAB - 34 RECEIVE DESCRIPTOR 2 ................................................................................................................................ 32 TAB - 35 RECEIVE DESCRIPTOR 3 ................................................................................................................................ 32 TAB - 36 TRANSMIT DESCRIPTOR 0 ............................................................................................................................. 34 TAB - 37 TRANSMIT DESCRIPTOR 1 ............................................................................................................................. 34 TAB - 38 TRANSMIT DESCRIPTOR 2 ............................................................................................................................. 34 TAB - 39 TRANSMIT DESCRIPTOR 3 ............................................................................................................................. 34
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.0 Introduction
1.1 General Description:
l l l l l The AX88140A Fast Ethernet Controller is a high performance and highly integrated PCI Bus Ethernet Controller chip. The AX88140A is cost effective, high performance solution for PCI add-in adapters, PC motherboards, or bridge/hub applications. It implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 LAN standard. The AX88140A contains a high speed 32 bit PCI Bus master interface to host CPU. Two large independent transmit and receive FIFO allow the AX88140A to buffer the Ethernet packet efficiently. The 10/100Mbps ports can be programmed to support 10Mbps, 100Mbps media-independent interface (MII), or 100BASE-TX physical coding sub-layer (PCS)mode, For 10Mbps operation AX88140A provides a standard serial Interface to the external 10Mbps ENDEC chip.
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ASIX ELECTRONICS CORPORATION
AX88140A 1.2 Features
l l l l l l l l l l l l l l l l l l l l
PRELIMINARY
Single chip PCI bus Fast Ethernet Controller. Direct interface to PCI bus. Support both 10Mbps and 100Mbps data rate. Full or Half duplex operation supported for both10Mbps and 100Mbps operation. Provides a MII port for both 10/100Mbps operation. On chip PCS support for 100BASE-TX symbol mode operation. On chip external 10Mbps ENDEC Interface. Support 21MHz to 33MHz no wait state PCI Bus Interface. Two large Independent FIFO for transmit and receive. no additional On board buffer memory required. Interface to serial ROM for Ethernet ID address and jumper-less board design. 256KB boot ROM support. On chip general purpose, programmable register and I/O pins. Unlimited PCI burst. external and internal loop-back capability. Support early interrupts on transmit. Powerful on chip buffer management DMA. And PCI Bus master operation reduce CPU utilization. Big and little endian byte ordering supported. IEEE 802.3u 100BASE-T, TX, and T4 Compatible. 160 pin or 144 pin PQFP package. 5V CMOS process.
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ASIX ELECTRONICS CORPORATION
AX88140A 1.3 Block Diagram:
PRELIMINARY
SERIAL ROOM
BOOT ROM Interface
Serial ROM I/F
BOOT ROM I/F MII Interface MAC Controller PCS Interface SYM MII
Receive FIFO
PCI BUS
PCI BUS Interface
Buffer Management DMA Engine
Transmit FIFO
10 BT Interface
SRL
General Purpose REG
General purpose I/O pins
Fig - 1 AX88140A Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.4 AX88140AQ Pin Connection Diagram for 160-pin
The AX88140A is housed in the 160-pin plastic quad flat pack. Fig - 2 shows the AX88140A pin connection diagram.
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
nc nc nc nc nc nc srl_txen srl_tclk srl_txd srl_rclk srl_rxen srl_rxd srl_clsn mii/srl symtxd mtxd/symtxd mtxd/symtxd vdd vss mtxd/symtxd mtxd/symtxd mtxen/symtxen nc mtclk/symtclk rcv_match vdd vss symrxd mrxd/symrxd mrxd/symrxd mrxd/symrxd mrxd/symrxd mrclk/symrclk mcrs mcol mrxdv mrxerr sd nc nc
nc nc int# rst# vdd vss pci_clk vdd gnt# req# vss ad ad vss ad ad vss ad ad vdd ad ad c_be# idsel vss ad ad ad ad vdd ad ad vdd vss vss ad ad vss nc nc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ASIX 88140AQ
nc nc vss vdd mdc mdio nc br_a br_a brce# br_ad br_ad vdd vss br_ad br_ad br_ad br_ad br_ad br_ad vss genp genp genp genp vdd vss genp genp genp genp sr_cs sr_ck sr_di sr_do vdd vss vdd* nc nc
nc nc vss cbe# frame# irdy# trdy# devsel# stop# vdd perr# serr# par cbe# vss ad ad ad vss ad ad vdd ad ad vss ad cbe# ad ad vss ad ad vdd ad ad vss ad ad nc nc
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Fig - 2 AX88140AQ Pin connection diagram for 160-pin
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.5 AX88140AP Pin Connection Diagram for 144-pin
The AX88140A is housed in the 144-pin plastic quad flat pack. Fig - 3 shows the AX88140A pin connection diagram.
int# rst# vdd vss pci_clk vdd gnt# req# vss ad ad vss ad ad vss ad ad vdd ad ad cbe# idsel vss ad ad ad ad vdd ad ad vdd vss vss ad ad vss
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
nc nc nc nc srl_txen srl_tclk srl_txd srl_rclk srl_rxen srl_rxd srl_clsn mii/srl symtxd mtxd/symtxd mtxd/symtxd vdd vss mtxd/symtxd mtxd/symtxd mtxen/symtxen nc mtclk/symtclk rcv_match vdd vss symrxd mrxd/symrxd mrxd/symrxd mrxd/symrxd mrxd/symrxd mrclk/symrclk mii_crs mcol mrxdv mrxerr sd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ASIX 88140AP
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
vss vdd mdc mdio nc br_a br_a brce# br_ad br_ad vdd vss br_ad br_ad br_ad br_ad br_ad br_ad vss genp genp genp genp genp vdd vss genp genp genp genp sr_cs sr_ck sr_di sr_do vdd vss vdd*
vss cbe# frame# irdy# trdy# devsel# stop# vdd perr# serr# par cbe# vss ad ad ad vss ad ad vdd ad ad vss ad cbe# ad ad vss ad ad vdd ad ad vss ad ad
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Fig - 3 AX88140AP Pin connection diagram for 144-pin
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
2.0 Signal Description
2.1 Signal Descriptions for 160-pin and 144-pin
The following terms describe the AX88140A pin-out: Address phase Address and appropriate bus commands are driven during this cycle. l Data phase Data and the appropriate byte enable codes are driven during this cycle. l# All pin names with the # suffix are asserted low. l The following abbreviations are used in Tab - 1 PCI interface group Tab - 2 Boot ROM , Serial ROM , Generalpurpose signals group ,Tab - 3 MII/SYM/SRL interface signals group ,Tab - 4 Extended , NC, Power pins group.. I O I/O O/D Input Output Input /Output Open Drain
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ASIX ELECTRONICS CORPORATION
AX88140A 2.2 PCI interface group
SIGNAL TYPE PIN PIN NUMBER NUMBER FOR 160 PIN FOR 144 PIN
12, 13, 15, 16, 18, 19, 21, 22, 26, 27, 28, 29, 31, 32, 36, 37, 56, 57, 58, 60, 61, 63, 64, 66, 68, 69, 71, 72, 74, 75, 77, 78 23, 44, 54, 67 10, 11, 13, 14, 16, 17, 19, 20, 24, 25, 26, 27, 29, 30, 34, 35, 50, 51, 52, 54, 55, 57, 58, 60, 62, 63, 65, 66, 68, 69, 71, 72 21, 38, 48, 61
PRELIMINARY
DESCRIPTION
AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD CBE# CBE# CBE# CBE#
I/O
Address and data bits are multiplexed on the same pins. During the address phase, the AD contain a physical address (32 bits). During, data phases, AD contain 32 bits of data. The AX88140A supports both read and write bursts (in master operation only). Little and big endian byte ordering can be used.
I/O
DEVSEL#
I/O
48
42
FRAME#
I/O
45
39
GNT# IDSEL INT#
I I O/D
9 24 3
7 22 1
IRDY#
I/O
46
40
BUS COMMAND and BYTE ENABLE Are multiplexed on the same PCI pins. During the address phase of the transaction, CBE# Provide the BUS COMMAND. During the data phase, CBE# Provide the BYTE ENABLE. The BYTE ENABLE determines which byte lines carry valid data., CBE# Applies to byte 0, and CBE# Applies to byte 3. Device select Is asserted by the target of the current bus access. When the AX88140A is the master of the current bus access, the target assert DEVSEL# confirming the access. It is driven by AX88140A When AX88140A is selected as a slave. The FRAME# Signal is driven by the AX88140A To indicate the beginning and duration of an access. FRAME# Asserts to indicate the beginning of a bus transaction. While FRAME# is asserted, data transfers continue. When FRAME# deasserts the next data phase is the final data phase transaction. BUS GRANT Indicates to the AX88140A That access to the bus is granted. Initialization devise select asserts To indicate that the host is issuing a configuration cycle to the AX88140A. Interrupt request asserts When one of the appropriate bits of reg5 sets and causes an interrupt, provided that the corresponding mask bit in reg7 is not asserted. interrupt request deasserts by writing a 1 into the appropriate crs5 bit. This pin must be pulled up by an external resistor. Initiator ready Indicates the bus master ability to complete the current data phase of the transaction. A data phase is completed on any rising edge of the clock When both IRDY# and target ready TRDY# are asserted. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. When the AX88140A is the bus master, IRDY# is asserted during write operations to indicate that valid data is present on the AD. During read operations, the AX88140A asserts
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ASIX ELECTRONICS CORPORATION
AX88140A
PAR I/O 53 47
PRELIMINARY
IRDY# to indicate that it is ready to accept data. Parity is an even parity bit for the AD AD and CBE#. During address and data phases, parity is calculated on all the AD AND CBE#lines whether or not any of these lines carry meaningful information. The clock provides the timing for the AX88140A related PCI bus transactions. All the bus signals are sampled on the rising edge of PCI_CLK. The clock frequency range is between 21MHZ and 33MHZ. Parity error asserts when a data parity error is detected. When the AX88140A is the bus master it monitor PERR# to see if the target report a data parity error., when the AX88140A is the bus target and a parity error is detected, the AX88140A asserts PERR#. This pin must be pulled up by an external resistor. Bus request is asserted by the AX88140A to indicate to the bus arbiter that it wants to use the bus. Resets the AX88140A to its initial state. This signal must be asserted for at least 10 active PCI clock cycles. When is the reset state, all PCI output pins are put into tri-state and all PCI o/d signals are floated. System Error is used by AX88140A to report address parity Error. This pin must be pulled up by an external resistor. Stop indicator indicates that the current target is requesting the bus master to stop the current transaction. The AX88140A responds to the assertion of STOP# when it is the bus master, and stop the current transaction. Target ready indicates the target ability to complete the current data phase of the transaction. A data phase is completed on any clock when both TRDY# and IRDY# are asserted. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. When the AX88140A is the bus master, target ready is asserted by the bus slave on the read operation, indicating that valid data is present on the ad lines. During a write cycle, it indicates that the target is prepared to accept data.
PCI_CLK
I
7
5
PERR#
I/O
51
45
REQ# RST#
O I
10 4
8 2
SERR# STOP#
I/O I/O
52 49
46 43
TRDY#
I/O
47
41
Tab - 1 PCI interface group
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
2.3 Boot ROM , Serial ROM , General-purpose signals group
SIGNAL TYPE PIN PIN NUMBER NUMBER FOR 160 PIN FOR 144 PIN
112 113 110, 109, 106, 105, 104, 103, 102, 101 111 88 89 87 86 99, 98, 97, 96, 93, 92, 91, 90 102 103 100, 99, 96, 95, 94, 93, 92, 91 101 78 79 77 76 89, 88, 87, 86, 83, 82, 81, 80
DESCRIPTION
BR_A BR_A BR_AD BR_AD BR_AD BR_AD BR_AD BR_AD BR_AD BR_AD BR_CE# SR_CK SR_CS SR_DI SR_DO GENP GENP GENP GENP GENP GENP GENP GENP
0 0 I/O
Boot ROM address line bit 0. Boot ROM address line bit 1. This pin also latches the boot ROM address and control lines by the two external latches. Boot ROM address and data multiplexed lines bits 7 through 0. In the first of two consecutive address cycles, these lines contain the boot ROM address bits 9 through 2; followed by boot ROM address bits 17 through 10 in the second cycle. During the data cycle, bits 7 through 0 contain data.
O O O O I I/O
Boot ROM chip enable. Serial ROM clock signal. Serial ROM chip-select signal. Serial ROM data-in signal. Serial ROM data-out signal. General-purpose pins can be used by software as either status pins or control pins. These pins can be configured by software to perform either input or output functions.
Tab - 2 Boot ROM , Serial ROM , General-purpose signals group
2.4 MII/SYM/SRL interface signals group
SIGNAL TYPE PIN PIN NUMBER NUMBER FOR 160 PIN FOR 144 PIN
I I I 126 127 125 112 113 111
DESCRIPTION
MCOL MCRS MRXDV
MRXERR
I
124
110
MDC
O
116
106
MDIO
I/O
115
105
MII/SRL
O
147
133
Collision detected is asserted when detected by an external physical layer protocol(PHY) device. Carrier sense is asserted by the PHY when the media is active. Data valid is asserted by an external PHY when receive data is present on the MRXD/SYRXD lines and is deasserted at the end of the packet. This signal should be synchronized with the MRCLK/SYMRCLK signal. Receive error asserts when a data decoding error is detected by an external PHY device. This signal is synchronized to MRCLK/SYMRCLK and can be asserted for a minimum of one receive clock. When asserted during a packet reception, it sets the cyclic redundancy check(CRC) error bit in the receive descriptor (RDESO). MII management data clock is sourced by the AX88140A to the PHY devices as a timing reference for the transfer of information on the MII_MDIO signal. MII management data input/output transfers control information and status between the PHY and the AX88140A. Indicates the selected port: SRL or MII/SYM. When asserted, the MII/SYM port is active. When deasserted, the SRL port is active.
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ASIX ELECTRONICS CORPORATION
AX88140A
MRCLK/SYMRCLK MRXD/SYMRXD MRXD/SYMRXD MRXD/SYMRXD MRXD/SYMRXD MTCLK/SYMTCLK I I 128 132, 131, 130, 129 137 114 118, 117, 116, 115 123
PRELIMINARY
Supports either the 25-MHZ or 2.5-MHZ receive clock. This clock is recovered by the PHY. Four parallel receive data lines When MII mode is selected. This data is driven by an external PHY that attached the media and should be synchronized with the MRCLK/SYMRCLK signal. Supports the 25-MHZ or 2.5-MHZ transmit clock supplied by the external physical layer medium dependent (PMD) device. This clock should always be active. Four parallel transmit data lines. This data is synchronized to the assertion of the MTCLK/SYMTCLK signal and is latched by the external PHY on the rising edge of the MTCLK/SYMTCLK signal. Transmit enable signals that the transmit is active to an external PHY device. In PCS mode (REG6), This signal reflects the transmit activity of the MAC sub-layer. Receive match indication is asserted when a received packet has passed address recognition. Receive match indication is asserted when a received packet has passed address recognition. Signal detect indication supplied by an external physical layer medium dependent (PMD) device. Collision detect signals a collision occurrence on the Ethernet cable to the AX88140A. It may be asserted and deasserted asynchronously by the external ENDEC to the receive clock. Receive clock carries the recovered receive clock supplied by an external ENDEC. during idle periods, SRL_RCLK may be inactive. Receive data carries the input receive data from the external ENDEC. The incoming data should be synchronous with the SRL_RCLK signal. Receive enable signals activity on the Ethernet cable to the AX88140A. It is asserted when receive data is present on the Ethernet cable and is deasserted at the end of a frame. It may be asserted and deasserted asynchronously to the receive clock (SRL_RCLK) by the external ENDEC. Transmit clock carries the transmit clock supplied by an external ENDEC. This clock must always be active (even during reset). Transmit data carries the serial output data from the AX88140A. This data is synchronized to the SRL_TCLK signal. Transmit enable signals an external ENDEC That the AX88140A transmit is in progress. Receive data, together with the four receive lines MII/SYM_RXD, Provide five parallel lines of data in symbol from for use in PCS mode (100BASE-T, REG6
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