AX88796CLI

AX88796C Low-Power SPI or Non-PCI Ethernet Controller Features Document No.: AX88796C/V1.17/12/09/14 back-pressure flow control Supports auto-polling function Supports 10/100Mbps N-way Auto-negotiation operation Advanced Power Management features Supports dynamic power management to reduce power dissipation during idle or light traffic period Supports very low power Wake-On-LAN (WOL) mode when the system enters sleep mode and waits for network event to awake it up. The wakeup events supported are network link state change, receipt of a Magic Packet or a pre-programmed Microsoft Wakeup Frame or through GPIO pin Supports Protocol Offload (ARP & NS) for Windows 7 Networking Power Management Supports complete I/O pins isolation during WOL mode or Remote Wakeup Ready mode to reduce leakage current on non-PCI and SPI slave host interface Supports optional EEPROM interface to store MAC address Supports up to four GPIOs and two of them support Wake-On-LAN Supports programmable LED pins for various network activity indications with variable voltage I/O and programmable driving strength Integrates voltage regulator, 25MHz crystal oscillator and power on reset circuit on chip Supports optional clock output (25, 50 or 100MHz) for system use, if 25MHz crystal is present Supports optional clock input (25MHz) from system clock to save the 25MHz crystal cost 64-pin LQFP RoHS compliant package Operates over 0 to +70C or -40 to +85C temperature range High-performance non-PCI local bus Supports 8/16-bit SRAM-like host interface (US Patent Approval), easily interfaced to most common embedded MCUs; or 8/16-bit local CPU interface including MCS-51 series, Renesas series CPUs Supports Slave-DMA to minimize CPU overhead and burst mode read & write access for frame reception & transmission on SRAM-like interface for high performance applications Supports variable voltage I/O (1.8/2.5/3.3V) and programmable driving strength (8/16mA) Interrupt pin with programmable timer High-performance SPI slave interface Supports SPI slave interface for CPU with SPI master. The SPI slave interface supports SPI timing mode 0 and 3, up to 40MHz of SPI CLK, variable voltage I/O and programmable driving strength Supports optional Ready signal as flow control for SPI packet RX/TX Single-chip Fast Ethernet MAC/PHY controller Embeds 14KB SRAM for packet buffers Supports IPv4/IPv6 packet Checksum Offload Engine to reduce CPU loading, including IPv4 IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICM Pv6 checksum generation & check Supports VLAN match filter Integrates IEEE 802.3/802.3u standards compatible 10BASE-T/100BASE-TX (twisted pair copper mode) Fast Ethernet MAC/PHY transceiver in one single-chip Supports twisted pair crossover detection and correction (HP Auto-MDIX) Supports full duplex operation with IEEE 802.3x flow control and half duplex operation with ASIX ELECTRONICS CORPORATION 1 4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300 TEL: 886-3-579-9500 FAX: 886-3-579-9558 Release Date: 12/09/2014 http://www.asix.com.tw AX88796C Low-Power SPI or Non-PCI Ethernet Controller Target Applications Netbook Industrial Computer Cable, Satellite and IP STB IPTV, Digital Media Adapter Network DVD, DVR-R, HDD IP/Video Phone, VoIP ATA Internet Radio POS Terminal, Kiosk Multi Functional Printer RFID Reader Time Attendance RS232/422/485 to Ethernet Building / Home Automation HVAC Control Networked Home Appliance Security System Biometric Access Control Fingerprint Reader Network Camera Remote Surveillance Professional DVR Fire and Safety Industrial Control Remote Data Collection Equipment Remote Monitor Remote Control and Management Environment Monitoring or Network Sensor Automatic Meter Reading Networked UPS Lighting Control System Block Diagram 2 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Copyright © 2010-2014 ASIX Electronics Corporation. All rights reserved. DISCLAIMER No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make changes to the product specifications and descriptions in this document at any time, without notice. ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without limitation warranties of merchantability, fitness for a particular purpose, and non-infringement. Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a design of ASIX products. TRADEMARKS ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of their respective owners. 3 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Table of Contents 1.0 Introduction ........................................................................................................................... 9 1.1 1.2 1.3 General Description ............................................................................................................ 9 Block Diagram .................................................................................................................... 9 Pin Connection Diagram ................................................................................................... 10 1.3.1 1.3.2 1.3.3 1.4 Bus Interface Configuration Table and Application ......................................................... 13 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 2.0 8/16-Bit SRAM-like or Renesas SHx Series CPU Bus Mode .................................................................. 10 8/16-Bit Address-Data Multiplex or MCS-51 Bus Mode ......................................................................... 11 SPI Bus Mode ........................................................................................................................................... 12 8-Bit SRAM-like Bus Interface ................................................................................................................ 13 16-Bit SRAM-like Bus Interface .............................................................................................................. 14 MCS-51 Bus Interface .............................................................................................................................. 14 8-Bit Address-Data Multiplex Bus Interface ............................................................................................ 15 16-Bit Address-Data Multiplex Bus Interface .......................................................................................... 15 Renesas SHx series CPU Bus Interface .................................................................................................... 16 SPI Mode Bus Interface ............................................................................................................................ 16 Signal Description ............................................................................................................... 17 2.1 2.2 2.3 2.4 2.5 2.6 3.0 Local CPU Bus Interface Signals Group .......................................................................... 17 10/100Mbps Twisted-Pair Interface Signals Group .......................................................... 19 Build-in PHY LED Indicator Signals Group .................................................................... 19 EEPROM Signals Group .................................................................................................. 20 SPI Interface Signals Group ............................................................................................. 21 Miscellaneous Signals Group ........................................................................................... 21 Memory Mapping Table ..................................................................................................... 23 3.1 3.2 EEPROM Memory Format Table ..................................................................................... 23 Internal Memory Mapping Table ...................................................................................... 26 3.2.1 3.2.2 4.0 Register Read/Write Access ..................................................................................................................... 27 RX/TX Packet Buffer Access ................................................................................................................... 27 Basic Operation ................................................................................................................... 28 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4 4.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.8 4.8.1 4.8.2 4.9 Receiver Filtering ............................................................................................................. 28 Unicast Address Match Filter ................................................................................................................... 28 Multicast Address Match Filter ................................................................................................................ 29 Broadcast Address Match Filter ............................................................................................................... 31 VLAN Match Filter .................................................................................................................................. 31 Buffer Management Operation ......................................................................................... 32 Packet Reception ............................................................................................................... 32 Packet Transmission ......................................................................................................... 33 Filling Packet to Transmit Buffer: Host write data to TX memory .................................. 35 Removing Packets from the Ring: Host read data from RX memory .............................. 39 Wake-up Detection............................................................................................................ 43 Wake-up frame ......................................................................................................................................... 43 Magic Packet frame .................................................................................................................................. 45 Link Change Wakeup ............................................................................................................................... 46 GPIO Wakeup ........................................................................................................................................... 46 Flow Control ..................................................................................................................... 47 Full-Duplex Flow Control ........................................................................................................................ 47 Half-Duplex Flow Control........................................................................................................................ 48 Auto-Polling Function ...................................................................................................... 48 4 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.10 4.11 4.12 Mixed Endian Byte Ordering ............................................................................................ 49 EEPROM Interface ........................................................................................................... 50 Power Management Function ........................................................................................... 51 4.12.1 4.12.2 4.12.3 4.12.4 4.13 4.14 5.0 Hardware-detect Cable-Off Power Saving Mode (PSCR [4]=0, default) ............................................ 52 Software Control Cable-Off Power Saving Mode (PSCR [4]=1) ........................................................ 52 Sleep Mode .......................................................................................................................................... 53 Wake-On-LAN Power Saving Mode ................................................................................................... 53 Checksum Offload Function ............................................................................................. 54 GPIO Function .................................................................................................................. 58 SPI Interface ........................................................................................................................ 59 5.1 5.2 Introduction ....................................................................................................................... 59 Features ............................................................................................................................. 59 5.2.1 5.3 5.4 Mode Access............................................................................................................................................. 60 SPI Module Operation ...................................................................................................... 61 Instruction Set Summary .................................................................................................. 62 5.4.1 5.5 SPI Mode Instruction Table ...................................................................................................................... 62 Commands Waveform....................................................................................................... 63 5.5.1 SPI Mode .................................................................................................................................................. 63 5.5.1.1 Read command................................................................................................................................ 63 5.5.1.2 Write command ............................................................................................................................... 65 5.6 6.0 SPI Status Access .............................................................................................................. 68 Registers Description .......................................................................................................... 69 6.1 Internal Register Mapping Table....................................................................................... 69 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.1.18 6.1.19 6.1.20 6.1.21 6.1.22 6.1.23 6.1.24 6.1.25 6.1.26 6.1.27 6.1.28 6.1.29 6.1.30 6.1.31 6.1.32 6.1.33 Page 0 Offset 0x00: Page Select Register (PSR) ...................................................................................... 71 Page 0 Offset 0x02 : Byte Order Register (BOR) .................................................................................. 72 Page 0 Offset 0x04: Function Enable Register (FER) .............................................................................. 72 Page 0 Offset 0x06: Interrupt Status Register (ISR) ................................................................................. 73 Page 0 Offset 0x08: Interrupt Mask Register (IMR) ................................................................................ 74 Page 0 Offset 0x0A: Wakeup Frame Configuration Register (WFCR) .................................................... 75 Page 0 Offset 0x0C: Power Saving Configuration Register (PSCR) ........................................................ 77 Page 0 Offset 0x0E: MAC Configuration Register (MACCR) ................................................................ 78 Page 0 Offset 0x10: TX Free Buffer Count Register (TFBFCR) ............................................................. 79 Page 0 Offset 0x12: TX Sequence Number Register (TSNR) ............................................................. 79 Page 0 Offset 0x14: RX/TX Data Port Register (RTDPR) .................................................................. 79 Page 0 Offset 0x16: RX Bridge Control Register 1 (RXBCR1) .......................................................... 79 Page 0 Offset 0x18: RX Bridge Control Register 2 (RXBCR2) .......................................................... 80 Page 0 Offset 0x1A: RX Total Valid Word Count Register (RTWCR) ................................................ 80 Page 0 Offset 0x1C: RX Current Packet Header Register (RCPHR) .................................................. 80 Page 0 ~ 7 Offset 0x1E: Remote Wakeup Register (RWR) ................................................................. 81 Page 1 Offset 0x02: RX Packet Process Enable Register (RPPER) .................................................... 81 Page 1 Offset 0x08: Memory Read/Write Control Register (MRCR) ................................................. 81 Page 1 Offset 0x0A: Memory Data Register (MDR) ........................................................................... 81 Page 1 Offset 0x0C: RX Memory Pointer Register (RMPR) .............................................................. 81 Page 1 Offset 0x0E: TX Memory Pointer Register (TMPR) ............................................................... 82 Page 1 Offset 0x10: RX Bridge Stuffing Packet Control Register (RXBSPCR) ................................. 82 Page 1 Offset 0x12: RX MAC Control Register (RXMCR) ................................................................ 82 Page 2 Offset 0x02: IO Control Register (ICR) ................................................................................... 83 Page 2 Offset 0x04: PHY Control Register (PCR) .............................................................................. 84 Page 2 Offset 0x06: PHY Status Register (PHYSR) ........................................................................... 85 Page 2 Offset 0x08: MDIO Read/Write Data Register (MDIODR) .................................................... 86 Page 2 Offset 0x0A: MDIO Read/Write Control Register (MDIOCR) ............................................... 86 Page 2 Offset 0x0C: I_Full/I_Speed LED Control Register 0 (LCR0) ................................................ 87 Page 2 Offset 0x0E: I_LK/Act LED Control Register 1 (LCR1) ........................................................ 88 Page 2 Offset 0x10: IPG Control Register (IPGCR) ........................................................................... 88 Page 2 Offset 0x12: Chip Revision ID Register (CRIR) ..................................................................... 88 Page 2 Offset 0x14: Flow Control High/Low Watermark Control Register (FLHWCR) .................... 89 5 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.34 6.1.35 6.1.36 6.1.37 6.1.38 6.1.39 6.1.40 6.1.41 6.1.42 6.1.43 6.1.44 6.1.45 6.1.46 6.1.47 6.1.48 6.1.49 6.1.50 6.1.51 6.1.52 6.1.53 6.1.54 6.1.55 6.1.56 6.1.57 6.1.58 6.1.59 6.1.60 6.1.61 6.1.62 6.1.63 6.1.64 6.1.65 6.1.66 6.1.67 6.1.68 6.1.69 6.1.70 6.1.71 6.1.72 6.1.73 6.1.74 6.1.75 6.1.76 6.1.77 6.1.78 6.1.79 6.1.80 6.1.81 6.1.82 6.1.83 6.1.84 6.1.85 6.1.86 6.1.87 6.1.88 6.1.89 6.1.90 6.1.91 6.1.92 6.1.93 Page 2 Offset 0x16: RX Control Register (RXCR) ............................................................................. 89 Page 2 Offset 0x18: Jam Limit Count Register (JLCR)....................................................................... 90 Page 2 Offset 0x1C: Max Packet Length Register (MPLR) ................................................................ 90 Page 3 Offset 0x02: MAC Address Setup Register 0 (MACASR0) .................................................... 91 Page 3 Offset 0x04: MAC Address Setup Register 1 (MACASR1) .................................................... 91 Page 3 Offset 0x06: MAC Address Setup Register 2 (MACASR2) .................................................... 91 Page 3 Offset 0x08: Multicast Filter Array Register (MFAR01) ......................................................... 92 Page 3 Offset 0x0A: Multicast Filter Array Register (MFAR23) ........................................................ 92 Page 3 Offset 0x0C: Multicast Filter Array Register (MFAR45)......................................................... 92 Page 3 Offset 0x0E: Multicast Filter Array Register (MFAR67) ......................................................... 92 Page 3 Offset 0x10: VLAN ID0 Filter Register (VID0FR) ................................................................. 92 Page 3 Offset 0x12: VLAN ID1 Filter Register (VID1FR) ................................................................. 93 Page 3 Offset 0x14: EEPROM Checksum Register (EECSR) ............................................................ 93 Page 3 Offset 0x16: EEPROM Data Register (EEDR) ........................................................................ 93 Page 3 Offset 0x18: EEPROM Control Register (EECR) ................................................................... 93 Page 3 Offset 0x1A: Test Packet Configuration Register (TPCR) ....................................................... 94 Page 3 Offset 0x1C: Test Packet Length Register (TPLR) .................................................................. 94 Page 4 Offset 0x02: GPIO Enable Register (GPIOER) ....................................................................... 94 Page 4 Offset 0x04: GPIO IRQ Control Register (GPIOCR) .............................................................. 95 Page 4 Offset 0x06: GPIO Wakeup Control Register (GPIOWCR) .................................................... 95 Page 4 Offset 0x0A: SPI Configuration Register (SPICR) .................................................................. 96 Page 4 Offset 0x0C: SPI Interrupt Status and Mask Register (SPIISMR) ........................................... 97 Page 4 Offset 0x12: COE RX Control Register 0(COERCR0) ........................................................... 98 Page 4 Offset 0x14: COE RX Control Register 1(COERCR1) ........................................................... 99 Page 4 Offset 0x16: COE TX Control Register 0(COETCR0) .......................................................... 100 Page 4 Offset 0x18: COE TX Control Register 1(COETCR1) .......................................................... 101 Page 5 Offset 0x02: Wakeup Frame Timer Register (WFTR) ........................................................... 101 Page 5 Offset 0x04: Wakeup Frame Cascade Command Register (WFCCR) ................................... 102 Page 5 Offset 0x06: Wakeup Frame Command 0 ~ 3 Register (WFCR03) ....................................... 103 Page 5 Offset 0x08: Wakeup Frame Command 4 ~ 7 Register (WFCR47) ....................................... 104 Page 5 Offset 0x0A: Wakeup Frame 0 Byte Mask [15:0] Register (WF0BMR0) ............................. 104 Page 5 Offset 0x0C: Wakeup Frame 0 Byte Mask [31:16] Register (WF0BMR1) ........................... 104 Page 5 Offset 0x0E: Wakeup Frame 0 CRC Register (WF0CR) ....................................................... 104 Page 5 Offset 0x10: Wakeup Frame 0 Offset Byte Register (WF0OBR) .......................................... 105 Page 5 Offset 0x12: Wakeup Frame 1 Byte Mask [15:0] Register (WF1BMR0) .............................. 105 Page 5 Offset 0x14: Wakeup Frame 1 Byte Mask [31:16] Register (WF1BMR1) ............................ 105 Page 5 Offset 0x16: Wakeup Frame 1 CRC Register (WF1CR) ........................................................ 105 Page 5 Offset 0x18: Wakeup Frame 1 Offset Byte Register (WF1OBR) .......................................... 106 Page 5 Offset 0x1A: Wakeup Frame 2 Byte Mask [15:0] Register (WF2BMR0) ............................. 106 Page 5 Offset 0x1C: Wakeup Frame 2 Byte Mask [31:16] Register (WF2BMR1) ........................... 106 Page 6 Offset 0x02: Wakeup Frame 2 CRC Register (WF2CR) ........................................................ 106 Page 6 Offset 0x04: Wakeup Frame 2 Offset Byte Register (WF2OBR) .......................................... 107 Page 6 Offset 0x06: Wakeup Frame 3 Byte Mask [15:0] Register (WF3BMR0) .............................. 107 Page 6 Offset 0x08: Wakeup Frame 3 Byte Mask [31:16] Register (WF3BMR1) ............................ 107 Page 6 Offset 0x0A: Wakeup Frame 3 CRC Register (WF3CR) ....................................................... 107 Page 6 Offset 0x0C: Wakeup Frame 3 Offset Byte Register (WF3OBR) .......................................... 108 Page 6 Offset 0x0E: Wakeup Frame 4 Byte Mask [15:0] Register (WF4BMR0) .............................. 108 Page 6 Offset 0x10: Wakeup Frame 4 Byte Mask [31:16] Register (WF4BMR1) ............................ 108 Page 6 Offset 0x12: Wakeup Frame 4 CRC Register (WF4CR) ........................................................ 108 Page 6 Offset 0x14: Wakeup Frame 4 Offset Byte Register (WF4OBR) .......................................... 109 Page 6 Offset 0x16: Wakeup Frame 5 Byte Mask [15:0] Register (WF5BMR0) .............................. 109 Page 6 Offset 0x18: Wakeup Frame 5 Byte Mask [31:16] Register (WF5BMR1) ............................ 109 Page 6 Offset 0x1A: Wakeup Frame 5 CRC Register (WF5CR) ....................................................... 109 Page 6 Offset 0x1C: Wakeup Frame 5 Offset Byte Register (WF5OBR) .......................................... 110 Page 7 Offset 0x02: Wakeup Frame 6 Byte Mask [15:0] Register (WF6BMR0) .............................. 110 Page 7 Offset 0x04: Wakeup Frame 6 Byte Mask [31:16] Register (WF6BMR1) ............................ 110 Page 7 Offset 0x06: Wakeup Frame 6 CRC Register (WF6CR) ........................................................ 110 Page 7 Offset 0x08: Wakeup Frame 6 Offset Byte Register (WF6OBR) .......................................... 111 Page 7 Offset 0x0A: Wakeup Frame 7 Byte Mask [15:0] Register (WF7BMR0) ............................. 111 Page 7 Offset 0x0C: Wakeup Frame 7 Byte Mask [31:16] Register (WF7BMR1) ........................... 111 6 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.94 6.1.95 6.1.96 6.1.97 6.1.98 6.1.99 6.1.100 6.1.101 6.2 PHY Register Detailed Description .................................................................................115 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 7.0 Page 7 Offset 0x0E: Wakeup Frame 7 CRC Register (WF7CR) ....................................................... 111 Page 7 Offset 0x10: Wakeup Frame 7 Offset Byte Register (WF7OBR) .......................................... 112 Page 7 Offset 0x12: Wakeup Frame Reply 0 ~ 1 Register (WFR01) ................................................. 112 Page 7 Offset 0x14: Wakeup Frame Reply 2 ~ 3 Register (WFR23) ................................................. 113 Page 7 Offset 0x16: Wakeup Frame Reply 4 ~ 5 Register (WFR45) ................................................. 113 Page 7 Offset 0x18: Wakeup Frame Reply 6 ~ 7 Register (WFR67) ................................................. 114 Page 7 Offset 0x1A: Wakeup Frame Partial Checksum 0 Register (WFPC0) ................................... 114 Page 7 Offset 0x1C: Wakeup Frame Partial Checksum 1 Register (WFPC1) ................................... 114 MR0: Basic Mode Control Register ....................................................................................................... 116 MR1: Basic Mode Status Register .......................................................................................................... 117 MR2: PHY Identifier Register 1 ............................................................................................................. 118 MR3: PHY Identifier Register 2 ............................................................................................................. 118 MR4: Auto Negotiation Advertisement Register .................................................................................... 118 MR5: Auto Negotiation Link Partner Ability Register ........................................................................... 119 MR6: Auto Negotiation Expansion Register .......................................................................................... 119 Electrical Specifications ................................................................................................... 120 7.1 DC Characteristics .......................................................................................................... 120 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.2 7.3 7.4 7.5 Absolute Maximum Ratings ................................................................................................................... 120 General Operating Condition.................................................................................................................. 120 DC Characteristics of 3.3V I/O (VCCIO = 3.3V) .................................................................................. 121 DC Characteristics of 2.5V I/O (VCCIO = 2.5V) .................................................................................. 122 DC Characteristics of 1.8 V I/O (VCCIO = 1.8V) ................................................................................. 123 DC Characteristics of Voltage Regulator ................................................................................................ 124 Thermal Characteristics .................................................................................................. 124 Power Consumption ........................................................................................................ 125 Power-up Sequence ......................................................................................................... 126 AC Timing Characteristics.............................................................................................. 127 7.5.1 Clock Timing .......................................................................................................................................... 127 7.5.2 Reset Timing........................................................................................................................................... 128 7.5.3 Serial EEPROM Timing ......................................................................................................................... 129 7.5.4 10/100M Ethernet PHY Interface Timing............................................................................................... 130 7.5.5 8/16-Bit SRAM-like Bus Timing ........................................................................................................... 131 7.5.5.1 Single Read Bus Timing ............................................................................................................... 131 7.5.5.2 Single Write Bus Timing ............................................................................................................... 132 7.5.5.3 Burst Read Bus Timing ................................................................................................................. 133 7.5.5.4 Burst Write Bus Timing ................................................................................................................ 136 7.5.6 8/16-Bit Address/Data Multiplex Bus Timing ........................................................................................ 139 7.5.6.1 8/16-Bit Single Read Bus Timing ................................................................................................. 139 7.5.6.2 8/16-Bit Single Write Bus Timing................................................................................................. 140 7.5.6.3 16-Bit Burst Read Bus Timing ...................................................................................................... 141 7.5.6.4 16-Bit Burst Write Bus Timing ..................................................................................................... 142 7.5.7 8051 Bus Timing .................................................................................................................................... 143 7.5.7.1 Single Read Bus Timing ............................................................................................................... 143 7.5.7.2 Single Write Bus Timing ............................................................................................................... 144 7.5.8 Renesas series CPU Bus Timing ............................................................................................................ 145 7.5.8.1 Single Read Bus Timing ............................................................................................................... 145 7.5.8.2 Single Write Bus Timing ............................................................................................................... 146 7.5.8.3 Burst Read Bus Timing ................................................................................................................. 149 7.5.8.4 Burst Write Bus Timing ................................................................................................................ 152 7.5.9 SPI Bus Timing ...................................................................................................................................... 155 7.5.9.1 Mode 0 Timing .............................................................................................................................. 155 7.5.9.2 Mode 3 Timing .............................................................................................................................. 156 8.0 8.1 9.0 Package Information ........................................................................................................ 157 64-pin LQFP package ..................................................................................................... 157 Ordering Information ....................................................................................................... 158 7 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 10.0 Revision History ................................................................................................................ 159 Appendix A: Disable AX88796C voltage regulator ................................................................... 161 List of Figures FIG 1 FIG 2 FIG 3 FIG 4 FIG 5 FIG 6 FIG 7 FIG 8 FIG 9 FIG 10 FIG 11 FIG 12 FIG 13 FIG 14 FIG 15 FIG 16 FIG 17 FIG 18 FIG 19 FIG 20 FIG 21 FIG 22 FIG 23 FIG 24 FIG 25 FIG 26 AX88796C BLOCK DIAGRAM ......................................................................................................................... 9 8/16-BIT SRAM-LIKE/RENESAS MODE PIN OUT DIAGRAM .......................................................................... 10 8/16-BIT ADDRESS-DATA MULTIPLEX/MCS-51 MODE PIN OUT DIAGRAM ................................................. 11 SPI MODE PIN OUT DIAGRAM ...................................................................................................................... 12 8-BIT SRAM-LIKE BUS APPLICATION DIAGRAM ......................................................................................... 13 16-BIT SRAM-LIKE BUS APPLICATION DIAGRAM ....................................................................................... 14 MCS-51 BUS APPLICATION DIAGRAM ......................................................................................................... 14 8-BIT ADDRESS-DATA MULTIPLEX BUS APPLICATION DIAGRAM ................................................................ 15 16-BIT ADDRESS-DATA MULTIPLEX BUS APPLICATION DIAGRAM .............................................................. 15 RENESAS SHX SERIES CPU BUS APPLICATION DIAGRAM ............................................................................ 16 SINGLE SPI BUS APPLICATION DIAGRAM .................................................................................................. 16 INTERNAL SRAM MAP .................................................................................................................................. 26 MULTICAST FILTER EXAMPLE ....................................................................................................................... 29 MULTICAST FILTER ARRAY HASHING ALGORITHM ...................................................................................... 30 GENERAL TRANSMIT PACKET FORMAT ......................................................................................................... 33 HOST FILL PACKET TO TX MEMORY THROUGH SCATTER MEMORY APPROACH ............................................. 36 TX HEADER FORMAT ................................................................................................................................. 37 THE AX88796C RX PACKET FORMAT........................................................................................................... 39 RX HEADER FORMAT.................................................................................................................................... 40 AUTO-REPLY ARP FORMAT.......................................................................................................................... 44 PAUSE PACKET FORMAT ............................................................................................................................... 47 TX / RX FLOW CONTROL .............................................................................................................................. 48 FOUR FIXED PATTERNS FOR BYTE LANE TEST ............................................................................................... 49 EEPROM CONNECTIONS............................................................................................................................... 50 IPV6 PACKET FORMAT .................................................................................................................................. 57 SPI TIMING DIAGRAM ................................................................................................................................... 60 List of Tables TAB - 1 TAB - 2 TAB - 3 TAB - 4 TAB - 5 TAB - 6 TAB - 7 TAB - 8 TAB - 9 TAB - 10 TAB - 11 TAB - 12 TAB - 13 TAB - 14 TAB - 15 TAB - 16 TAB - 17 THE AX88796C BUS INTERFACE CONFIGURATION TABLE ........................................................................... 13 LOCAL CPU BUS INTERFACE SIGNALS GROUP ............................................................................................... 18 10/100MBPS TWISTED-PAIR INTERFACES SIGNALS GROUP ........................................................................... 19 BUILT-IN PHY LED INDICATOR SIGNALS GROUP .......................................................................................... 19 EEPROM BUS INTERFACE SIGNALS GROUP ................................................................................................... 20 SINGLE SPI INTERFACE SIGNALS GROUP ....................................................................................................... 21 MISCELLANEOUS SIGNALS GROUP ................................................................................................................. 22 EEPROM DATA FORMAT .............................................................................................................................. 24 VID1/VID2 SETTING TO FILTER RECEIVED PACKET ...................................................................................... 31 GPIO WAKEUP CONFIGURATION TABLE ...................................................................................................... 46 POWER MANAGEMENT STATUS..................................................................................................................... 51 GPIO CONFIGURATION TABLE ...................................................................................................................... 58 SPI MODE INSTRUCTION TABLE ................................................................................................................... 62 SPI STATUS TABLE ....................................................................................................................................... 68 THE EMBEDDED PHY REGISTERS ............................................................................................................... 115 DEVICE POWER CONSUMPTION TABLE ........................................................................................................ 125 SYSTEM POWER CONSUMPTION TABLE ....................................................................................................... 125 8 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 1.0 Introduction 1.1 General Description The AX88796C is a SPI or non-PCI Ethernet controller with low power, low-pin-count and variable voltage I/O for the Embedded and Industrial Ethernet applications. The AX88796C supports 8/16-bit SRAM-like or Address-Data Multiplex host interface with variable voltage I/O, providing a glue-less connection to common or high-end MCUs. The AX88796C also provides an alternative SPI slave interface for MCUs with SPI master for simplifying host interface connection. The AX88796C integrates on-chip Fast Ethernet MAC and PHY, which is IEEE 802.3/802.3u 10BASE-T/100BASE-TX compatible, and 14KB embedded SRAM for packet buffering to accommodate high bandwidth applications. The AX88796C offers a wide array of features including support for advanced power management, high performance data transfer on host interface, IPv4/IPv6 checksum offload engine, HP Auto-MDIX, and IEEE 802.3x and back-pressure flow control. The AX88796C supports two operating temperature ranges, namely, commercial grade from 0 to 70 C and industrial grade from –40 to 85 C. The small form factor of 64-pin LQFP package helps reduce the overall PCB space. The programming of AX88796C is simple, so the users can easily port the software drivers to many embedded systems very quickly. 1.2 Block Diagram SPI or Local Bus Interface SA0-4 SD0-15 CSn WRn RDn IRQ Bus Interface MUX Local Bus Interface SPI Interface (Optional) EEDIO EECS EECK EEPROM Interface POR Wake-On LAN Checksum Offload Engine GPIO Interface 14KByte SRAM 10/100M Ethernet MAC Packet Buffer Management Voltage Regulator Power Management Unit 10/100M Ethernet PHY Crystal Oscillator Fig 1 AX88796C BLOCK DIAGRAM 9 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. TPO+ TPOTPI+ TPI(HP Auto-MDIX) AX88796C Low-Power SPI or Non-PCI Ethernet Controller 1.3 Pin Connection Diagram The AX88796C is housed in the 64-pin plastic light quad flat pack. Note: N/C means No Connect. SD5 SD6 SD7 SD8 SD9 8/16-Bit SRAM-like or Renesas SHx Series CPU Bus Mode SA2 SA3 SA4 SA5/FIFO_SEL VCCIO VCCK SD0 SD1 SD2 SD3 SD4 1.3.1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SA1 49 SA0 50 *GPIO1/AEN 51 CSn 52 RDn 53 WRn 54 GPIO0 55 TCLK 56 TEST_CK_EN 57 GND VCCK VCC18A XTALIN XTALOUT GND18A RSET_BG 32 SD10 31 SD11 30 SD12 29 SD13 28 SD14/GPIO2* 27 SD15/GPIO3* 26 GND 25 VCCIO 24 VCCK AX88796C 64-LQFP 58 59 60 61 62 63 64 o 1 23 IRQ 22 PME 21 EECS/GPIO3* 20 EECK/GPIO2* 19 EEDIO/GPIO1* 18 GND 17 RSTn 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I_FULL/COL I_SPEED I_LK/ACT TEST1 TEST2 GND3R3 VCC3R3 V18F GND18A TPOTPO+ VCC18A TPITPI+ GND3A3 VCC3A3 Fig 2 8/16-BIT SRAM-LIKE/RENESAS MODE PIN OUT DIAGRAM * NOTE: The GPIO1, GPIO2 and GPIO3 can only be enabled when EEPROM is not exist or data bus is not in used or regular pin function is disconnected. Please reference GPIOWCR[10:8] register information to carefully turn on and mux out the GPIO pin when normal pin is not connected. 10 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller SD5/SA5 SD6 SD7 SD8/PSEN(51) SD9 8/16-Bit Address-Data Multiplex or MCS-51 Bus Mode N/C N/C N/C N/C VCCIO VCCK SD0/SA0 SD1SA1 SD2/SA2 SD3/SA3 SD4/SA4 1.3.2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N/C 49 N/C 50 AEN 51 CSn 52 RDn 53 WRn 54 GPIO0 55 TCLK 56 TEST_CK_EN 57 GND VCCK VCC18A XTALIN XTALOUT GND18A RSET_BG 32 SD10 31 SD11 30 SD12 29 SD13 28 SD14/GPIO2* 27 SD15/GPIO3* 26 GND 25 VCCIO 24 VCCK AX88796C 64-LQFP 58 59 60 61 62 63 64 o 1 23 IRQ 22 PME 21 EECS/GPIO3* 20 EECK/GPIO2* 19 EEDIO/GPIO1* 18 GND 17 RSTn 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I_FULL/COL I_SPEED I_LK/ACT TEST1 TEST2 GND3R3 VCC3R3 V18F GND18A TPOTPO+ VCC18A TPITPI+ GND3A3 VCC3A3 Fig 3 8/16-BIT ADDRESS-DATA MULTIPLEX/MCS-51 MODE PIN OUT DIAGRAM * NOTE: The GPIO1, GPIO2 and GPIO3 can only be enabled when EEPROM is not exist or data bus is not in used or regular pin function is disconnected. Please reference GPIOWCR[10:8] register information to carefully turn on and mux out the GPIO pin when normal pin is not connected. 11 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller SPI Bus Mode N/C N/C N/C SA5/FIFO_SEL VCCIO VCCK MOSI MISO N/C N/C N/C N/C GPIO2* GPIO3* N/C N/C 1.3.3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N/C 49 N/C 50 *GPIO1 51 SSn 52 N/C 53 N/C 54 GPIO0 55 SPI CLK 56 TEST_CK_EN 57 GND VCCK VCC18A XTALIN XTALOUT GND18A RSET_BG AX88796C(SPI) 64-LQFP 58 59 60 61 62 63 64 o 1 2 32 N/C 31 N/C 30 N/C 29 N/C 28 GPIO2* 27 GPIO3* 26 GND 25 VCCIO 24 VCCK 23 IRQ 22 PME 21 EECS/GPIO3* 20 EECK/GPIO2* 19 EEDIO/GPIO1* 18 GND 17 RSTn 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I_FULL/COL I_SPEED I_LK/ACT TEST1 TEST2 GND3R3 VCC3R3 V18F GND18A TPOTPO+ VCC18A TPITPI+ GND3A3 VCC3A3 Fig 4 SPI MODE PIN OUT DIAGRAM * NOTE: The GPIO1, GPIO2 and GPIO3 can only be enabled when EEPROM is not exist or data bus is not in used or regular pin function is disconnected. Please reference GPIOWCR[10:8] register information to carefully turn on and mux out the GPIO pin when normal pin is not connected. 12 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 1.4 Bus Interface Configuration Table and Application The AX88796C supports total seven different types of bus interfaces include 8/16 Bit SRAM-like bus interface, 8/16-Bit Address-Data Multiplex interface, Renesas CPU series bus interface, MCS-51 and SPI bus interface. The AX88796C can be configured to the specific bus type automatically by pull-up and pull-down the EECS/EECK/I_FULL pins. Assume the external crystal is used. Please pull-down the TEST2, TEST1, and TEST_CK_EN three pins to ground. I_FULL PD PD PD PD PU PU PU PU EECS PD PD PU PU PD PD PU PU EECK PD PU PD PU PD PU PD PU Bus Type 8-bit SRAM-like bus 8-bit Address/Data multiplexed bus Reserved MCS-51 (805x) 16-bit SRAM-like bus 16-bit Address/Data multiplexed bus SPI Mode 16-bit local bus with byte write enable (Renesas SHx CPU bus style) TAB - 1 THE AX88796C BUS INTERFACE CONFIGURATION TABLE 1.4.1 8-Bit SRAM-like Bus Interface An example, the AX88796C’s bus setting to 8-bit SRAM-like bus mode. Three external pull-down resistors are connected to pin I_FULL, pin EECS and pin EECK. Please reference TAB-1 for the AX88796C bus type setting and pull down the unused SD[15:8] pins via 47K resistors. The pin SA5 suggest connect to the address higher than 2K address space and make sure SA0 is toggling when burst mode access data in and out of buffer memory. Note: A12 is just a reference minimal address pin to tie to SA5. AX88796C A0 A1 A2 A3 A4 A12 CSn RDn WRn INT Data[7:0] SA0 I_FULL SA1 EECS SA2 EECK SA3 AEN SA4 SA5/FIFO_SEL CSn RDn WRn IRQ SD[7:0] 8-Bit MCU Fig 5 8-BIT SRAM-LIKE BUS APPLICATION DIAGRAM 13 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. Pull-Down Pull-Down Pull-Down Pull-Down AX88796C Low-Power SPI or Non-PCI Ethernet Controller 1.4.2 16-Bit SRAM-like Bus Interface An example, the AX88796C’s bus setting to 16-bit SRAM-like bus mode. Please reference TAB-1 for the AX88796C bus type setting. The pin SA5 suggest connect to the address higher than 2K address space and make sure SA0 is toggling when burst mode access data in and out of buffer memory. Note: A12 is just a reference minimal address pin to tie to SA5. AX88796C SA0 I_FULL SA1 EECS SA2 EECK SA3 AEN SA4 SA5/FIFO_SEL CSn RDn WRn IRQ SD[15:0] A0 A1 A2 A3 A4 A12 CSn RDn WRn INT Data[15:0] Pull-Up Pull-Down Pull-Down Pull-Down 16-Bit MCU Fig 6 16-BIT SRAM-LIKE BUS APPLICATION DIAGRAM 1.4.3 MCS-51 Bus Interface An example, the AX88796C’s bus setting as MCS-51 mode. Two external pull-up resistors are connected to pin EECS and pin EECK. One pull down resistor is connected to the I_FULL pin. Please reference TAB-1 for the AX88796C bus type setting. AX88796C PSEN AEN DATA[7:0] RDn WRn INT SD[8] AEN SD[15:9] SD[7:0] RDn WRn IRQ MCS-51 NC The internal pull-down/up resisters controlled by Page 2 Offset 0x02, IO Control Register (ICR) I_FULL EECS EECK Pull-Down Pull-Up Pull-Up Fig 7 MCS-51 BUS APPLICATION DIAGRAM 14 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 1.4.4 8-Bit Address-Data Multiplex Bus Interface The AX88796C’s bus interface can set to 8-bit Address-Data multiplex bus mode. Please reference TAB-1 for the AX88796C bus type setting and pull down the unused SD[15:8] pins via 47K resistors. The AX88796C 8-bit Address-Data multiplex bus mode only supports single read and single write data access mode. AX88796C CSn RDn WRn INT Data[7:0] AEN CSn RDn WRn IRQ SD[7:0] AEN I_FULL EECS EECK Pull-Down Pull-Down Pull-Up 8-Bit MCU Fig 8 8-BIT ADDRESS-DATA MULTIPLEX BUS APPLICATION DIAGRAM 1.4.5 16-Bit Address-Data Multiplex Bus Interface The AX88796C’s bus interface can set to 16-bit Address-Data multiplex bus mode. Please reference TAB-1 for the AX88796C bus type setting. AX88796C CSn RDn WRn INT Data[15:0] AEN CSn RDn WRn IRQ SD[15:0] AEN I_FULL EECS EECK 16-Bit MCU Fig 9 16-BIT ADDRESS-DATA MULTIPLEX BUS APPLICATION DIAGRAM 15 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. Pull-Up Pull-Down Pull-Up AX88796C Low-Power SPI or Non-PCI Ethernet Controller 1.4.6 Renesas SHx series CPU Bus Interface The AX88796C supports Renesas SHx series CPU bus interface. Please reference TAB-1 for bus type setting. AX88796C A0 A1 A2 A3 A4 A12 CSn RDn WRn INT Data[15:0] AEN SA0 I_FULL SA1 EECS SA2 EECK SA3 SA4 SA5/FIFO_SEL CSn RDn WRn IRQ SD[15:0] AEN Pull-Up Pull-Up Pull-Up Renesas SHx CP 1.4.7 Fig 10 RENESAS SHX SERIES CPU BUS APPLICATION DIAGRAM SPI CLK SSn MOSI MISO SPI IRQ Mode Bus Interface CSn The AX88796C supports single SPI mode and please reference 5.4.1 for instruction set table U setting. that supports this Generic Host CPU With SPI Interface SPI CLK SSn MOSI MISO IRQ Fig 11 AX88796C I_FULL EECS EECK Pull-Up Pull-Up Pull-Down SINGLE SPI BUS APPLICATION DIAGRAM 16 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 2.0 Signal Description The following abbreviations are used in AX88796C pinout: All pin names with the “n” suffix are low-active signals. The following abbreviations are used in following Tables. MI MO MB T 4mA 8mA I O Multivoltage Input (3.3/2.5/1.8V) Multivoltage Output (3.3/2.5/1.8V) Bi-directional multivoltage I/O Tri-state 4mA driving strength 8mA driving strength 1.8V input 1.8V output PU PD AB P A S AO Pull Up (75Kohm) Pull Down (75Kohm) Analog IO differential pair Power Pin Analog Schmitt trigger Analog Output 2.1 Local CPU Bus Interface Signals Group Signal SA[4:0] SD[15:0] IRQ Type MI Pin No. Description 46, 47, 48, System Address: Signals SA[4:0] are address bus input 49, 50 lines. The internal PSR register bit [3] Address Shifter Control bit select the internal address decoding sequence. PIN 46 ~ 50 CHIP Internal Address Bus Decode AddressShifter 0 (Default, 1 (Enable) Control Bit Disable) Page0 Offset 0x00 [3] SA0 SA0 SA1 SA1 SA1 SA2 SA2 SA2 SA3 SA3 SA3 SA4 SA4 SA4 N/A MB/8mA 27, 28, 29, System Data Bus: Signals SD[15:0] constitute the 30, 31, 32, bi-directional data bus. 33, 34, 35, NOTE: 1.When the Bus Type is set to MCS-51 mode then SD8 36, 37, 38, pin will become PSEN. 39, 40, 41, 2.SD14 and SD6 can be configured to GPIO2 through 42 GPIOWCR [10:9] register setting when not used. 3.SD15 and SD7 can be configured to GPIO3 through GPIOWCR [10:9] register setting when not used.. MO/T/8mA 23 Programmable Interrupt request. Programmable polarity, source and buffer types. The IRQ polarity can be configured by EEPROM auto-loader or FER register 17 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller SA[5] or MI/PD 45 FIFO_SEL System Address or FIFO Select: When driven high, all accesses to the AX88796C are to the RX or TX data buffer FIFO (Data Port). The AX88796C supports two kinds of Data Port for receiving/transmitting packets from/to the AX88796C. One is the PIO (Program I/O) Data Port; the other one is the SRAM-like Data Port. The SRAM-like Data Port address range depends on which address line of host processor is being connected to the address line SA5/FIFO_SEL of the AX88796C. Please reserve minimal 2K address space for burst access. Software on host CPU can issue a Single Data Read/Write command to both PIO Data Port and SRAM-like Data Port. However, to use Burst Data Read/Write commands, one has to use SRAM-like Data Port, which requires SA5/FIFO_SEL (pin 45) of the AX88796C connecting to an upper address line of the host CPU. Our reference schematic has SA5/FIFO_SEL pin connected to upper address line for supporting Burst Data Read/Write commands. CSn MI/PU 52 RDn WRn MI/PU MI/PU 53 54 GPIO0 MB/8mA AEN/GPIO1 MI 55 51 PME 22 MO/T/8mA Chip Select: Active low. If the AX88796C bus type (TAB-1) is set to SPI Mode then this pin is Slave Select input for SPI bus. Read: Active low strobe to indicate a read cycle. Write: Active low strobe to indicate a write cycle. This signal also used to wakeup the AX88796C when it is in reduced power state. General purpose IO pin #0 Address enable for 8/16-Bit Address-Data Multiplex, MCS-51 bus modes and low byte write select for Renesas bus mode. Please pull-down this pin when configured to 8/16-Bit SRAM-like bus modes. If the AX88796C bus type (TAB-1) is set to SPI Mode then this pin can be configured to GPIO1 provide extra GPIO selection. NOTE: AEN can be configured to GPIO1 through GPIOWCR [8] register setting when not used. Wakeup Indicator: When programmed to do so, is asserted when the AX88696C detects a wakeup event and is requesting the system to wake up from the sleep state. The polarity and buffer type of this signal is programmable through the WFCR register setting. TAB - 2 LOCAL CPU BUS INTERFACE SIGNALS GROUP 18 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 2.2 10/100Mbps Twisted-Pair Interface Signals Group Signal TPI+ TPITPO+ TPORSET_BG Type AB AB AB AB AO Pin No. 3 4 6 7 64 Description Twisted Pair Receive Input, Positive Twisted Pair Receive Input, Negative Twisted Pair Transmit Output, Positive Twisted Pair Transmit Output, Negative Off-chip resister. Must be connected 12.1K ohm ± 1% to ground. TAB - 3 10/100MBPS TWISTED-PAIR INTERFACES SIGNALS GROUP 2.3 Build-in PHY LED Indicator Signals Group Signal I_FULL/COL Type MB/PU/ 8mA Pin No. Description 16 Full-Duplex/Collision Status. If this signal is low, it indicates full-duplex link established, and if it is high, then the link is in half-duplex mode. When in half-duplex and collision occurrence, the output will be driven low for 80ms and driven high at minimum 80ms. The users can also programmed register LCR0 [7:0] and change this LED output function. The LCR1 [15] configure this LED polarity to active high or active low (default). The pull-up or pull-down on pin I_FULL is also used to configure the AX88796C bus type. Please also reference AX88796C bus type table (TAB-1) for detail information. I_SPEED I_LK/ACT MO/8mA MO/8mA 15 14 Speed Status: If this signal is low, it indicates 100Mbps, and if it is high, then the speed is 10Mbps. The LCR0 [15:8] register provides a register setting to configure this LED output function. The users can change the default setting by program this register. Link Status/Active: If this signal is low, it indicates link, and if it is high, then the link is fail. When in link status and line activity occurrence, this signal is pulsed high (LED off) for 80ms whenever transmit or receive activity is detected. This signal is then driven low again for a minimum of 80ms, after which time it will repeat the process if TX or RX activity is detected. The register LCR1 [7:0] provides a programmable setting to configure this LED output function. The users can change the default setting by program this register. TAB - 4 BUILT-IN PHY LED INDICATOR SIGNALS GROUP 19 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 2.4 EEPROM Signals Group Signal EECS Type MB/4mA/PD EECK MB/4mA/PD EEDIO MB/4mA/PU Pin No. Description 21 EEPROM Chip Select: EEPROM chip select signal. NOTE: EECS can be configured to GPIO3 through GPIOWCR [10:9] register setting when not used. 20 EEPROM Clock: Signal connected to EEPROM clock pin. EECS, EECK can load BUS type setting during power on reset cycle.(PD: Pull Down PU: Pull Up) NOTE: EECK can be configured to GPIO2 through GPIOWCR [10:9] register setting when not used. I_FULL EECS EECK Bus Type PD PD PD 8-bit SRAM-like bus (AEN unused and must be pull-low.) PD PD PU 8-bit Address/Data multiplexed bus (AEN=1 address cycle, AEN=0 data cycle). Pin SD7 ~ SD0 is used. SD5 ~ SD0 represent address bus when AEN =1. Pin SD7 ~SD0 represent data bus when AEN=0. Pin CSN should be low when the AX88796C is selected. PD PU PD Reserved PD PU PU MCS-51 (805x)(PSEN/AEN active high) PU PD PD 16-bit SRAM-like bus (AEN unused and must be pull-low.) PU PD PU 16-bit Address/Data multiplexed bus (AEN=1: address cycle, AEN=0 : data cycle) Pin SD15 ~ SD0 is used. SD5 ~ SD0 represent address bus when AEN =1. SD15 ~SD0 represent data bus when AEN=0. CSN should be low when the AX88796C is selected. PU PU PD SPI Mode (AEN unused and can be pull-low if GPIO mode is unused.) PU PU PU 16-bit local bus with byte write enable (Renesas SHx style, AEN = low byte SD7 ~ SD0 enable, WRn = high byte SD15 ~ SD8 enable) 19 EEPROM Data In/Out: Signal connected to EEPROM data input and data output pin. NOTE: EEDIO can be configured to GPIO1 through GPIOWCR [8] setting when not used. TAB - 5 EEPROM BUS INTERFACE SIGNALS GROUP 20 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 2.5 SPI Interface Signals Group Signal MOSI MISO SSn SPI_CLK Type MI/8mA MO/T/8mA MI/PU MI Pin No. 42 41 52 56 Description SPI data input SPI data output SPI slave select signal (active low) SPI clock input TAB - 6 SINGLE SPI INTERFACE SIGNALS GROUP 2.6 Miscellaneous Signals Group Signal XTALIN Type I XTALOUT O RSTn MI/S/PU TCLK MB/PD Pin No. Description 61 Crystal/Oscillator Input: A 25MHz crystal, +/- 50 PPM can be connected across XTALIN and XTALOUT. CMOS Local Clock: A 25MHz clock, +/- 50 PPM, 40%-60% duty cycle. Note that the pin does not support 3.3V or 5V voltage supply. 62 Crystal/Oscillator Output: A 25MHz crystal, +/- 50 PPM can be connected across XTALIN and XTALOUT. If a single-ended external clock (LCLK) is connected to XTALIN, the crystal output pin should be left floating. 17 Chip Reset. Reset is active low. Place the AX88796C under the reset mode. During the rising edge, the AX88796C loads the power on setting data. 56 TCLK is bi-direction I/O type pin and support 25MHz system clock input when XTALIN (Pin 61) and XTALOUT (Pin 62) are unused or 25/50/100MHz extra clock output when configure to clock output port. NOTE: 1. TCLK and SPI CLK share the same pin. When AX88796C is configured to SPI mode the TCLK will be used as SPI CLK. 2. TCLK output clock is not free-running clock. If the AX88796C is in Power Saving Mode 2 (PS2)/Sleep Mode and TCLK clock output is enabled then NO clock will be send out due to power saving function gated the internal clock source. 3. Please make sure FER[4:3] setting to the right clock output frequency. 4. TCLK clock output source is from internal PHY. When power saving in Power Saving Mode 2 (PS2) mode, this clock output source will be gated. 21 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller TEST2 TEST1 TEST_ CK_ EN PD PD PD TCLK Comment Clock output Register setting to decide 25, 50 or 100MHz clock output. The register FER[4:3] is the clock output select register. [4] [3] TCLK Output 0 0 Disable. (Default input direction and internal pull-down, compatible with AX88796B) 0 1 25MHz clock output 1 0 50MHz clock output 1 1 100MHz clock output PD PD PU 25MHz XTALOUT/XTALIN not used clock input PD PU X N/A N/A PU X X N/A IC test mode TEST_CK_EN MI/PD/S 57 TCLK mode select. Please reference TCLK table setting TEST2 MI/PD/S 12 TCLK mode select. Please reference TCLK table setting TEST1 MI/PD/S 13 TCLK mode select. Please reference TCLK table setting VCC3A3 P 1 Power Supply for Analog Circuit: +3.3V DC. GND3A3 P 2 Power Supply for Analog Circuit: +0V DC or Ground Power. VCC18A P 5, 60 Analog power for oscillator, PLL, and Ethernet PHY differential I/O pins, 1.8V GND18A P 8, 63 Analog ground for oscillator, PLL, and Ethernet PHY differential I/O pins. V18F P 9 On-chip 3.3V to 1.8V Regulator output +1.8V DC with 150mA driving current. VCC3R3 P 10 On-chip 3.3V to 1.8V Regulator power supply: +3.3V DC. GND3R3 P 11 On-chip 3.3V to 1.8V Regulator ground. GND P 18, 26, 58 Ground. VCCIO P 25, 44 Multi-voltage Power Supply for IO Pad: +3.3V/2.5V/1.8V DC. VCCK P 24, 43, 59 Power Supply for core logic: +1.8V DC. TAB - 7 MISCELLANEOUS SIGNALS GROUP 22 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 3.0 Memory Mapping Table 3.1 EEPROM Memory Format Table The AX88796C supports 16-bit mode 93C56/93C66 EEPROM. The EEPROM content will be auto-loaded to respective AX88796C registers setting described in below EEPROM mapping format during AX88796C hardware reset. During hardware reset, the EEPROM loader will check the high-byte of the EEPROM first word data and the Check Sum field value at low-byte of EEPROM address 0x27. Please make sure the high-byte of first word is equal to 0x5A before programming the EEPROM data. If the hardware calculated the checksum value of EECSR register plus the Check Sum filed of EEPROM address 0x27 is not equal to 0xFF then the EEPROM loader will proclaim that wrong EEPROM data and stop auto-loading EEPROM. Please check PSCR [15] EEPROM_OK and EECSR register checksum value for EEPROM auto-loading status. If PSCR [15] EEPROM_OK is one and EECSR register is 0xFF then external EEPROM device is not connected. If PSCR [15] EEPROM_OK is zero, then the device report checksum value did not match with expected checksum value and no EEPROM data can load into the AX88796C internal registers. The EEPROM data can be indirectly accessed through the EECR and EEDR registers. The EECSR register saves the pre-calculated checksum complement value for EEPROM auto-loading finish check. The EECSR provides hardware calculated total checksum value from 0x00 up to the valid address location. If 0xFF minus EECSR checksum value is equal to the EEPROM address 0x27’s checksum value then the checksum test is passed. The users can change the EEPROM length value (address 00h, low-byte) to 0Fh if the wakeup frame function is not supported that can reduce the EEPROM auto-loading time. The following is a sample EEPROM data with the desired MAC address 00-12-34-56-78-9A.  Please reference register description section and set the correspondent value for your specific application. Addr 0x00 Page #, Offset# Length (low-byte) Register Description Length: Indicates the total of word counts for auto loading 0x01 D[15:0]* 0x5A, Length 0x789A Page 3 Offset0x02 0x02 0x3456 Page 3 Offset 0x04 0x03 0x0012 Page 3 Offset 0x06 0x04 0x05 0x06 0x0003 0xFFFF 0x0820 Page 0 Offset 0x04 Page 0 Offset 0x08 Page 0 Offset 0x0C MAC Address Setup Register0 (MACASR0) MAC address [39:32], [47:40] MAC Address Setup Register1 (MACASR1) MAC address [23:16], [31:24] MAC Address Setup Register2 (MACASR2) MAC Address [7:0], [15:8] Function Enable Register (FER) Interrupt Mask Register (IMR) Power Saving Configuration Register (PSCR) NOTE: Bit 11 (PHY_Reset) can’t be written from EEPROM load process and should be force to default value!! 23 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x0018 0x0000 0x1002 0x0C00 0xFF00 0x0000 0xF000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Page 0 Offset 0x0E Page 2 Offset 0x02 Page 2 Offset 0x04 Page 4 Offset 0x0A Page 4 Offset 0x0C Page 4 Offset 0x02 Page 4 Offset 0x04 Page 4 Offset 0x06 Page 5 Offset 0x02 Page 5 Offset 0x04 Page 5 Offset 0x06 Page 5 Offset 0x08 Page 5 Offset 0x0A Page 5 Offset 0x0C Page 5 Offset 0x0E Page 5 Offset 0x10 Page 5 Offset 0x12 Page 5 Offset 0x14 Page 5 Offset 0x16 Page 5 Offset 0x18 Page 5 Offset 0x1A Page 5 Offset 0x1C Page 6 Offset 0x02 Page 6 Offset 0x04 Page 6 Offset 0x06 Page 6 Offset 0x08 Page 6 Offset 0x0A Page 7 Offset 0x12 Page 7 Offset 0x14 Page 7 Offset 0x1A Page 7 Offset 0x1C Page 0 Offset 0x0A MAC Configuration Register (MACCR) IO Control Register (ICR) PHY Control Register (PCR) SPI Configuration Register (SPICR) SPI Interrupt Status and Mask Register (SPIISMR) GPIO Enable Register (GPIOER) GPIO IRQ Control Register (GPIOCR) GPIO Wakeup Control Register (GPIOWCR) Wakeup Frame Timer Register (WFTR) Wakeup Frame Cascade Command Register (WFCCR) Wakeup Frame Command 0~3 Register (WFCR03) Wakeup Frame Command 4~7 Register (WFCR47) Wakeup Frame 0 Byte Mask [15:0] Register (WF0BMR0) Wakeup Frame 0 Byte Mask [31:16] Register (WF0BMR1) Wakeup Frame 0 CRC Register (WF0CR) Wakeup Frame 0 Offset Byte Register (WF0OBR) Wakeup Frame 1 Byte Mask [15:0] Register (WF1BMR0) Wakeup Frame 1 Byte Mask [31:16] Register(WF1BMR1) Wakeup Frame 1 CRC Register (WF1CR) Wakeup Frame 1 Offset Byte Register (WF1OBR) Wakeup Frame 2 Byte Mask [15:0] Register (WF2BMR0) Wakeup Frame 2 Byte Mask [31:16] Register (WF2BMR1) Wakeup Frame 2 CRC Register (WF2CR) Wakeup Frame 2 Offset Byte 0 Register (WF2OBR) Wakeup Frame 3 Byte Mask [15:0] Register (WF3BMR0) Wakeup Frame 3 Byte Mask [31:16] Register (WF3BMR1) Wakeup Frame 3 CRC Register (WF3CR) Wakeup Frame Reply 0 ~ 1 Register (WFR01) Wakeup Frame Reply 2 ~ 3 Register (WFR23) Wakeup Frame Partial Checksum 0 Register (WFPC0) Wakeup Frame Partial Checksum 1 Register (WFPC1) Wakeup Frame Configuration Register (WFCR) NOTE: Please make sure checksum value is correct before write this value. To protect sleep mode being write incorrectly causing chip in sleep state. 0x27 0x00, Check Sum (low-byte) The Check Sum value of EEPROM address 00h ~ h fields. This field will always be auto-loaded into the EECSR register no matter the field value. TAB - 8 EEPROM DATA FORMAT 24 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller The AX88796C EEPROM 8 bits Checksum Algorithm: Addr[00] (High Byte) + Addr[00] (Low Byte) carry[0] sum[0] sum[0] + carry[0] + Addr [01] (High Byte) + Addr [01] (Low Byte) carry[1] sum[1] ● ● ● sum[Length-1] + carry[Length-1] + Addr [Length] (High Byte) + Addr [Length] (Low Byte) carry[Length] sum[Length] Addr [27h](Low)= 0xFF – ( sum[Length] + carry[Length] ) EECSR value 25 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 3.2 Internal Memory Mapping Table The AX88796C internal register address [7:0] is mapping to {SA5=0, PS2, PS1, PS0, SA4, SA3, SA2, SA1, SA0}. The SA5 set to zero to enable internal register access. If SA5 set to one then the internal TX/RX buffer memory access will be enabled. There are total 8 pages within the register space and each page has total 32 byte data. The SA4, SA3 SA2, SA1 and SA0 will be the offset inside each page. The three page select bits PS2, PS1 and PS0 configured from the PSR [2:0] decide which page to select. 0x00 Internal Register Page 0 ~ Page 7 0xFF SA5=1, Write process SA0 toggling 4Kbyte Transmit Memory Buffer SA5=1, Read process 10Kbyte Receive Memory Buffer SA0 toggling Fig 12 INTERNAL SRAM MAP 26 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 3.2.1 Register Read/Write Access The AX88796C provides direct access to internal register through read/write operation when SA5 is set to zero. The PSR [2:0] define the page select information (Page 0 ~ Page 7). Pin SA4 ~ SA0 provide the offset information. The AX88796C supports register burst read or burst write access when the chip select signal is continuous stay low. 3.2.2 RX/TX Packet Buffer Access The AX88796C provides 4Kbyte TX Buffer RAM and 10Kbyte RX Buffer RAM for packet reception and transmission. When SA5=1, the burst operation to access TX/RX buffer will be enabled as long as chip select stay low. The AX88796C also supports PIO access to TX/RX buffer RAM through page 0 offset 14h register setting. Please always reserve at least 2KB memory buffer when access through SA5 burst access. 27 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.0 Basic Operation 4.1 Receiver Filtering The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast destination addresses are filtered using a hashing algorithm. (See following description.) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise the Protocol Control Logic rejects it. Each destination address is also checked for all 1’s, which is the reserved for broadcast address. 4.1.1 Unicast Address Match Filter The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in MACASR2/MACASR1/MACASR0 to the bit sequence of the received packet. MACASR2[15:8] MACASR2[7:0] MACASR1[15:8] MACASR1[7:0] MACASR0[15:8] MACASR0[7:0] D7 DA7 DA15 DA23 DA31 DA39 DA47 D6 DA6 DA14 DA22 DA30 DA38 DA46 D5 DA5 DA13 DA21 DA29 DA37 DA45 D4 DA4 DA12 DA20 DA28 DA36 DA44 D3 DA3 DA11 DA19 DA27 DA35 DA43 D2 DA2 DA10 DA18 DA26 DA34 DA42 D1 DA1 DA9 DA17 DA25 DA33 DA41 D0 DA0 DA8 DA16 DA24 DA32 DA40 Note: The bit sequence of the received MAC address is DA0, DA1, … DA46, DA47 …. 28 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.1.2 Multicast Address Match Filter The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. All multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones. MFAR0 MFAR1 MFAR2 MFAR3 MFAR4 MFAR5 MFAR6 MFAR7 D7 FB7 FB15 FB23 FB31 FB39 FB47 FB55 FB63 D6 FB6 FB14 FB22 FB30 FB38 FB46 FB54 FB62 D5 FB5 FB13 FB21 FB29 FB37 FB45 FB53 FB61 D4 FB4 FB12 FB20 FB28 FB36 FB44 FB52 FB60 D3 FB3 FB11 FB19 FB27 FB35 FB43 FB51 FB59 D2 FB2 FB10 FB18 FB26 FB34 FB42 FB50 FB58 D1 FB1 FB9 FB17 FB25 FB33 FB41 FB49 FB57 D0 FB0 FB8 FB16 FB24 FB32 FB40 FB48 FB56 {MFAR67 [15:0], MFAR54 [15:0], MFAR23 [15:0], MFAR01 [15:0]} = the multicast address bit map for multicast frame filtering block. For example, see below Fig-13. DA 81 81 81 81 81 81 CRC32 {crc31, 30, 29, 28, 27, 26} Address [5:0] = 1Ah MFAR [63:0] = 400_0000h Fig 13 MULTICAST FILTER EXAMPLE As shown in below figure, the Multicast Filter Array Register (MFAR) provides filtering of multicast addresses hashed through the CRC logic. All Destination Address field are fed through the 32 bits CRC generation logic. As the last bit of the Destination Address field enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1-to-64 decoder and index a unique filter bit (FB0-63) in the Multicast Filter Array. If the filter bit selected is set, the multicast packet is accepted. The system designer should use a program to determine which filter bits to set in the multicast registers. All multicast filter bits that correspond to Multicast Filter Array Registers accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones. 29 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Note that the Ethernet MAC regardless of MFAR setting always filters all the receiving Pause Frames. 48 bits DA field (DA [40] = 1 indicating a multicast DA) 32-bit CRC Generator CRC [31:26] 1 to 64-bit decoder Index to MFA Multicast Filter Array Fig 14 Selected bit: 0: Reject the multicast packet 1: Accept the multicast packet MULTICAST FILTER ARRAY HASHING ALGORITHM Example: If the accepted multicast packet’s destination address Y is found to hash to the value 32 (0x20), then FB32 in MFAR34 should be initialized to “1”. This will allow the Ethernet MAC to accept any multicast packet with the destination address Y. Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64 logical address filters if these addresses are chosen to map into unique locations in the multicast filter. Note: The LSB bit of received packet’s first byte being “1” signifies a Multicast Address. Following is the truth table about multicast packet filtering condition. (Please also refer to RXCR register description) PRO AMALL AM Pass Hashing Multicast Packet Filtered by Ethernet bit bit bit Algorithm? MAC? 0 0 0 0 Yes 0 0 0 1 Yes 0 0 1 0 Yes 0 0 1 1 No 0 1 0/1 0/1 No 1 0/1 0/1 0/1 No Note: Passing Hashing Algorithm means that the selected bit in MFAR of CRC-32 result is set to “1”. 30 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.1.3 Broadcast Address Match Filter The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s, which is the values are “FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the Protocol Control Logic rejects the packet. 4.1.4 VLAN Match Filter The AX88796C compares the thirteenth and fourteenth bytes of receive frames. If not match with VLAN_ID1 (VID1FR), VLAN_ID_0 (VID0FR) then reject current frame. The VLAN filter will always accept VLAN_ID is zero of receive frames due to it is IEEE-802.1Q (for priority purpose) frames. The maximum length of the good packet is thus change from 1518 bytes to 1522 bytes. 802.1Q VLAN tagging 7 Bytes Layer 2 Preamble 1 Byte SFD 6 Bytes Destination Address 6 Bytes Source Address 2B 2B 2B 8100 TCI L/T Frame (64-1518 Bytes) VLAN (64-1522 Bytes) 3 bits Priority 46-1500 Bytes Data 1 bit CFI 4 Bytes Pad FCS 12 bits VLAN ID The VLAN ID field (12 bits) within the received IEEE-802.1Q tagged packet will be used to compare with VID1 and VID2 setting. If it matches either VID1 or VID2, or its value is equal to all zeros, the received IEEE-802.1Q tagged packets will be forwarded to the Host interface. Meanwhile, the VSO bit (VID0FR [15]) determines whether the VLAN Tag bytes (4 bytes) are stripped off or not during forwarding to the Host interface. Also, if the incoming packets contain no VLAN Tag bytes, they will be forwarded to the Host interface by default. If there is no match between the received IEEE-802.1Q tagged packets and VID1 and VID2, the packets will be discarded. Please reference TAB-9 below. Received packet VID1, VID2 Zero Not zero Untagged Tagged VID=Zero VID= Not zero Forwarded Forwarded Discarded Forwarded Forwarded Match: Forwarded No Match: Discarded TAB - 9 VID1/VID2 SETTING TO FILTER RECEIVED PACKET 31 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.2 Buffer Management Operation There are four buffer memory access types used in the AX88796C buffer access flow. 1. Packet Reception: write data to RX memory buffer from MAC 2. Packet Transmission: read data from TX memory buffer to MAC 3. Filling Packets to Transmit Buffer: Host interface write data to TX memory 4. Removing Packets from the Receive Buffer Ring: Host interface read data from RX memory The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write operation and type 4 does Remote DMA read operation. 4.3 Packet Reception The Local DMA receives channel use a Buffer Ring Structure comprised of a series of contiguous fixed length 128 byte buffers for storage of received packets. Ethernet packets consist of minimum packet size (64 bytes) to maximum packet size (1522 bytes), the 128 byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. In addition these buffers provide memory resources for storage of back-to-back packets in loaded networks. Buffer Management Logic in the AX88796C controls the assignment of buffers for storing packets. The Buffer Management Logic provides three basic functions: linking receives buffers for long packets, recovery of buffers when a packet is rejected, and recalculation of buffer pages that have been read by the host. Beginning Of Reception When the first packet begins arrive the AX88796C and begins storing the packet at the location pointed to by the RMPR. An offset of 8 bytes is reserved in this first buffer to allow room for storing receives status corresponding to this packet. Linking Receive Buffer Pages If the length of the packet exhausts the first 128 bytes buffer, the DMA performs a forward link to the next buffer to store the remainder of the packet. For a maximal length packet the buffer logic will link 12 buffers to store the entire packet. Buffers cannot be skipped when linking; a packet will always be stored in contiguous buffers. Successful Reception If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet. The DMA then stores the Receive Status, a Pointer to where the next packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are discarded and reception of the next packet begins on the next empty 128 byte buffer boundary. The AX88796C is then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer had been previously calculated and temporarily stored in an internal scratchpad register.) 32 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Buffer Recovery For Rejected Packets If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR), recovering all buffers that had been used to store the rejected packet. This operation will not be performed if the AX88796C is programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC is always stored in buffer memory after the last byte of received data for the packet. 4.4 Packet Transmission The Local DMA Read is also used during transmission of a packet. When the AX88796C receives a command to transmit the packet, the buffer memory data will be moved into the FIFO as required during transmission. The AX88796C Controller will generate and append the preamble, synch and CRC fields. The AX88796C supports options of transmit queue function to enhance transmit performance. Transmit Packet Assembly The AX88796C requires a contiguous assembled packet with the format shown below. The transmit byte count includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC. When transmitting data smaller than 64 bytes, The AX88796C can auto padding to a minimum length of 64 bytes Ethernet frame. The packets are placed in the buffer RAM by the system. System programs the AX88796C Core's Remote DMA to move the data from the system buffer RAM to internal transmit buffer RAM. The data transfer must be 16-bits (1 word) when in 16-bit mode, and 8-bits when the AX88796C Controller is set in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register. Destination Address Source Address Length / Type Data (Pad if < 46 Bytes) Fig 15 6 Bytes 6 Bytes 2 Bytes 46 Bytes Minimal GENERAL TRANSMIT PACKET FORMAT Conditions Required To Begin Transmission In order to transmit a packet, the following three conditions must be met: 1. The Inter-packet Gap Timer has timed out 2. At least one byte has entered the FIFO. 3. If a collision had been detected then before transmission the packet back-off time must have timed out. 33 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Collision Recovery During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit DMA pointers for retransmission of the packet. The COL bit will be set and the NCR (Number of Collisions Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be aborted. Transmit Packet Assembly Format The following diagrams describe the format for how packets must be assembled prior to transmission for different byte ordering schemes. The various formats are selected in the Data Configuration Register. D15 D8 D7 D0 Destination Address 1 Destination Address 0 Destination Address 3 Destination Address 2 Destination Address 5 Destination Address 4 Source Address 1 Source Address 0 Source Address 3 Source Address 2 Source Address 5 Source Address 4 Type / Length 1 Type / Length 0 Data 1 Data 0 … … This format is used with 16-bit bus interface D7 D0 Destination Address 0 (DA0) Destination Address 1 (DA1) Destination Address 2 (DA2) Destination Address 3 (DA3) Destination Address 4 (DA4) Destination Address 5 (DA5) Source Address 0 (SA0) Source Address 1 (SA1) Source Address 2 (SA2) Source Address 3 (SA3) Source Address 4 (SA4) Source Address 5 (SA5) Type / Length 0 Type / Length 1 Data 0 Data 1 … This format is used with 8-bit bus interface Note: All examples above will result in a transmission of a packet in order of DA0 (Destination Address 0), DA1, DA2, DA3 and so on in byte. Bits within each byte will be transmitted least significant bit first. 34 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.5 Filling Packet to Transmit Buffer: Host write data to TX memory The Remote DMA channel is used to both assemble packets for transmission, and move the received packets from the Receive Buffer Ring. It may also be used as a general-purpose slave DMA channel for moving blocks of data or commands between host memory and local buffer memory. There are two modes of operation, Remote Write and Remote Read Packet. Remote Write A Remote Write transfer is used to move a block of data from the host into local buffer memory. The Remote DMA will read data from the I/O port and sequentially write it to local buffer memory beginning at the Remote Start Address. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is terminated when the Remote Byte Count Register reaches a count of zero. For detail programming procedure please reference the AX88796C Software Programming Guide documentation for further detail information. Scatter memory approach (Packet data distributed in difference memory locations) The scatter memory approach assumes the packet information is located in different memory pages. The AX88796C driver will copy these slices of the data into the TX memory in segment header format without re-grouping the packet. For example, the first yellow packet has the Layer 2 payload located in memory location 1, Layer 3 data in yellow location 2, Layer 4 data stored in yellow location 3 and the rest data in yellow location 4. The AX88796C is able to support direct moving each segment data with different segment ID to the AX88796C TX memory buffer and reassemble in to one packet before pass to TX MAC. CPU Memory 1 3 FS:1 LS:0 FS:0 LS:0 FS:0 LS:0 FS:0 LS:1 FS:1 LS:0 FS:0 LS:0 FS:0 LS:1 3 796C H S 1 S 2 S 3 S 4 E H S 1 S 2 S 3 E 2 2 Segment Header SOP Header EOP Header 4 1 35 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Sequence number should continuous between each dma burst Previous DMA Packet Next DMA Packet SOP Sequence Number = 0 EOP Sequence Number = 0 SOP Sequence Number = 1 SOP Header SOP Sequence Number = 3 Segment Header Data EOP Sequence Number = 3 EOP Header SOP Header SOP Sequence Number = 4 Segment Header Data EOP Sequence Number = 1 SOP Sequence Number = 2 Fig 16 Segment Header Data EOP Header SOP Header Segment Header Data EOP Sequence Number = 4 EOP Header SOP Header SOP Sequence Number = 5 Segment Header Data EOP Sequence Number = 2 SOP Header EOP Header SOP Header Segment Header Data EOP Sequence Number = 5 EOP Header EOP Header HOST FILL PACKET TO TX MEMORY THROUGH SCATTER MEMORY APPROACH 36 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller TX Header Format: The AX88796C TX header format is list in Fig 17 for reference. 1. The SOP Header contains the packet length information, sequence ID, checksum, de-queue control information. 2. The Segment Header include segment length, segment number ID, alignment information, first/last index information. 3. The EOP header has packet length and segment number for hardware end of the packet check. TX SOP Header 15 14 DICF CPHI 13 12 11 10 9 8 7 6 Manual INT dequeue 5 4 3 2 1 0 3 2 1 0 3 2 1 0 Packet Length [10:0] Sequence Number [4:0] Packet Length Bar [10:0] TX Segment Header 15 14 FS LS 13 12 11 10 9 8 7 6 5 4 Segment Number[2:0] Segment Length [10:0] Start Offset [2:0] Segment Length Bar [10:0] End Offset [1:0] TX EOP Header 15 14 13 12 11 10 9 8 7 6 5 4 Sequence Number [4:0] Packet Length [10:0] Sequence Number Bar [4:0] Packet Length Bar [10:0] Fig 17 TX HEADER FORMAT TX SOP Header Format: Bit 31:27 26:16 15 14 13 12 Name Function Description Sequence Number[4:0] Packet pre-assigned ID for tracking Packet Length Bar [10:0] TX packet length invert. For header check. DICF Disable TX checksum insertion function. 1: Disable checksum insertion. 0: Enable checksum insertion function. CPHI Pseudo header checksum value included. 1: Pseudo header checksum value included in Layer four checksum field. 0: No meaning in L4 checksum field. INT Generate interrupt when transmit complete Manual dequeue 1: Current packet will be paused until packet stay timer over TX timer limit if TX timer is enabled. 37 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 11 10:0 N/A Packet Length[10:0] 0: Current packet will be transmitted immediately. N/A Total packet size information TX Segment Header Format: Bit 31:30 29:27 26:16 15 14 13:11 10:0 Name End Offset[1:0] Function Description The data transfer unit by DMA. The software must use set field to tell AX88796C the data transfer unit of DMA operation. The AX88796C doesn't check this field in PIO mode. 0: The DMA controller transfer data in unit of 32-bit. 1: The DMA controller transfer data in unit of 64-bit. 2: The DMA controller transfer data in unit of 128-bit. 3: The DMA controller transfer data in unit of 256-bit. Start Offset[2:0] Data starting index location. The starting byte of the packet. SegmentLength Bar[10:0] Invert of segment length for internal checking purpose FS First Segment of the packet if set to one LS Last Segment of the packet if set to one Segment Number[2:0] Segment ID for grouping purpose and internal checking. Segment Length [10:0] Packet segment length information. TX EOP Header Format: Bit 31:27 26:16 15:11 10:0 Name Function Description SequenceNumberBar[4:0] The inverse of the sequence number for header check Packet Length Bar [10:0] Inverse of Packet length for header check Sequence Number [4:0] The packet segment number Packet Length [10:0] Packet total length information 38 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.6 Removing Packets from the Ring: Host read data from RX memory Remote Read A Remote Read transfer is used to move a block of data from local buffer memory to the host. The Remote DMA will sequentially read data from the local buffer memory, beginning at the Remote Start Address, and write data to the I/O port. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is terminated when the Remote Byte Count Register reaches zero. Please reference the AX88796C Software Programming Guide for further detail guideline for read process. RX Packet Format for Received Packets The following diagrams (Fig 18) describe the format for how received packets are placed into memory by the local DMA channel. The AX88796C RX packet format includes three of RX packet header information plus regular Ethernet packet format include DA MAC, SA MAC, packet type, and payload. D15 D8 D7 D0 RX Header1 [15:0] RX Header1 [31:16] RX Header2 [15:0] RX Header3 [15:0](optional, if FER[2] is set to one) RX Header3 [31:16](optional, if FER[2] is set to one) Destination Address 1 Destination Address 0 Destination Address 3 Destination Address 2 Destination Address 5 Destination Address 4 Source Address 1 Source Address 0 Source Address 3 Source Address 2 Source Address 5 Source Address 4 Type / Length 1 Type / Length 0 Data 1 Data 0 … … Fig 18 THE AX88796C RX PACKET FORMAT 39 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller RX Header Format: The AX88796C RX packet headers provide the receiving packet length, VLAN/L2/3/4 packet type, checksum information, and packet error-type information. The RX header information will smooth and easy for host to speed up their read process and enhance the overall RX performance. Fig 19 shows the AX88796C RX header format. RX Header 1 15 14 13 12 MC/ BC Runt Pkt MII Error CRC Error 31 30 29 28 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 3 2 1 0 Packet Length [10:0] 27 26 25 24 23 Sequence Number [4:0] 22 21 20 Packet Length Bar [10:0] RX Header 2 15 CE 14 13 L3_Pkt_Type 12 11 10 L4_PKT_Type 9 8 7 L3_ Err L4_ Err Reserved 6 5 4 Priority[2:0] Strip VLAN IND[2:0] RX Header 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 22 21 20 19 18 17 16 Csum [15:0] 31 30 29 28 27 26 25 24 23 Offset [7:0] Protocol [7:0] Fig 19 RX HEADER FORMAT RX Header 1 Format: Bit Name 31:27 Sequence Number[4:0] 26:16 Packet Length Bar[10:0] 15 MC/BC 14 13 Runt Packet MII Error 12 CRC Error 11 N/A 10:0 Packet Length[10:0] Function Description Packet Sequence number ID for tracking Inverse of Packet Length[10:0] for header check 1: Multicast or Broadcast Packet 0: Unicast Packet Receive runt packet. Packet size is less than 64 bytes 1: RX Error found on receive packet 0: No MII Error found 1: Receive packet CRC checksum error 0: Good CRC checksum N/A Receive Packet Size information 40 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller RX Header 2 Format: Bit 15 Name CE 14:13 L3_PKT_Type[1:0] 12:10 L4_PKT_Type[2:0] 9 L3_Err 8 L4_Err 7 6:4 N/A Priority[2:0] 3 Strip 2:0 VLAN ID[2:0] Function Description This bit combines 4 kinds of status, IPv4 version check error, IPv6 version check error, fragment packet and IPv6 parameter error. 1: One of listed status occurred in this packet. 0: No listed status in this packet. Layer 3 Packet type information 11: IPv6 in IPv4 tunnel 01: IPv6 10: IPv4 00: NON_IP packet Layer 4 Packet type information 001 : UDP 100 : TCP 010 : ICMP 011 : IGMP 101 : ICMPv6 100 : IP only 000 : IP only or COE do not parse Layer 4 header. Layer 3 checksum error. If this bit asserted, means this packet is a L3 error packet judged by COE. This packet did not pass the L3 checksum check Layer 4 checksum error. If this bit asserted, means this packet is a L4 error packet judged by COE. This packet did not pass the L4 checksum check.. N/A 3-bit field which refers to the IEEE 802.1p priority. It indicates the frame priority level from 0 (lowest) to 7 (highest), which can be used to prioritize different classes of traffic (voice, video, data, etc). (When VLAN_IND is equal to 3’b000, than this field is no effect.) VLAN Tag Strip 0: Received non-TAG frame or received TAG frame but hardware does not enable TAG strip function. 1: Received TAG-frame and TAG stripped by hardware VLAN Indication 000: This packet contains no VLAN tag. 100: This packet contains the VLAN id of 0 that is used for priority. 101: This packet contains the VLAN id of VID1 in the VLAN Control Register. 110: This packet contains the VLAN id of VID2 in the VLAN Control Register. 111: This packet contains the VLAN id which no match all zero, VID1 and VID2. 41 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller RX Header 3 Format: (Optional, enabled if register FER RH3M bit is set to one) Bit 31:24 23:16 15:0 Name Offset[7:0] Protocol[7:0] Csum[15:0] Function Description The offset of where Csum start calculate The protocol field of this packet Partial checksum of layer 4 payload 42 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.7 Wake-up Detection 4.7.1 Wake-up frame The AX88796C supports up to eight programmable filters that can go through many different kind of receive packet patterns, if the remote wakeup function is enabled. The remote wakeup function receives all the incoming frames and checks each frame against the enabled filter rule and recognizes the frame as a remote wake-up frame if it passes the MAC address filtering and CRC value match. In order to determine which bytes of the frames should be checked by the CRC-32 module. The AX88796C use a programmable byte mask and a programmable pattern offset for each of the eight supported filters. The AX88796C also provides the last byte match check and options cascade up to eight programmable filters. So these eight pattern detectors can operate simultaneously or sequentially. The byte mask is a 32-bit field that specifies whether or not each of the next 32 contiguous bytes within the frame, beginning in the pattern offset, should be checked. If bit j in the byte mask is set, the diction logic checks byte offset +j in the frame. The pattern offset define on Offset 7 ~ 0 for each wake-up filter 7 ~ 0 and the real offset value equal to Offset register multiplied by 2. (For example, the real offset value equal to 12 if set 6 on Offset register field) Last bytes 7 ~ 0 for each wake-up filter 7 ~ 0 also. The contents of Last Byte register must equal to the last of Byte Mask bit indicates of byte value. For example, if set Byte Mask [31:0] as 00C30003h then Byte Mask [23] is the last byte. Thus, the contents of Last byte register must equal to byte value of offset + 23. 43 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Microsoft Windows 7 ARP and NS Offload Support The AX88796C also supports the Microsoft Windows 7 ARP and NS offload function. The AX88796C will reply ARP and Neighbor Solicitation packets automatically before PME signal send out when the system is still in the Wake-Up mode setting with the ARP and NS protocol offload function is enabled and the good Wakeup frame is received. The AX88796C will latch the received wakeup frame’s SA and SIP and filled in the reply frame’s DA and DIP field plus re-calculate the good checksum value before sending out the reply packet. And the PME signal will be triggered after the ARP packet sending out from the PHY interface. The reference ARP frame format is list below. The following diagrams are the reference ARP packet format. IPv6 header Type Code chksum Reserved 135 0 32’b0 (dec) Target Address MAC address of source(Option) (IPv6 ICMPv6 Neighbor Solicitation packet) IPv6 header Type Code chksum Reserved 136 0 32’b0 (dec) Target Address MAC address of traget(Option) (IPv6 ICMPv6 Neighbor Advertisement packet) DA SA Etype Hardtype Prottype Hardsize Protsize Op Sender Sender Target Eth addr Target Padding = FFFFFFFFFFFF = 0806 = 0001 = 0800 = 06 = 04 = 0001 Eth addr IP addr = 000000000000 IP addr 18 bytes 28 bytes (ARP-Request packet) DA SA Etype Hardtype Prottype = 0806 = 0001 = 0800 Hardsize = 06 Fig 20 Protsize Op Sender Sender Target Target = 04 addrFORMAT IP addr Eth addr IP addr AUTO=-R0002 EPLYEth ARP 28 bytes (ARP-Reply packet) 44 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. Padding 55 bytes AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.7.2 Magic Packet frame The Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a network. The user can first turn on Magic Packet enable bit from the WFCR register bit [9] and set the MAC address before turn on the WFCR [5] enter the wakeup mode chip setting. Once the AX88796C has been put into the Magic Packet Wakeup mode, it scans all incoming Ethernet frames addressed to the node for a specific data sequence, which indicates to the controller that this is a Magic Packet frame. A Magic Packet frame must also meet the basic requirements for the Ethernet frame, such as SOURCE MAC ADDRESS, DESTINATION MAC ADDRESS (which may be the receiving station's IEEE address or a MULTICAST address which includes the BROADCAST address), and good CRC. The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a BROADCAST frame, as long as the 16 duplications of the IEEE address matches the address of the machine to be awakened. If the IEEE address for a particular node on the network is 0x112233445566, then the AX88796C scans for the data sequence (Assuming an Ethernet Frame): DA + SA + Misc. + FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 + Misc. + CRC. There are no other restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet, an IPX packet, etc. The frame may be bridged or routed across the network, without affecting its ability to wake up a node at the destination of the frame. If the AX88796C scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the controller detects the data sequence, however, then it alerts the PC's power management circuitry to wake up the system. A Wake-up frame is a special data packet containing the Ethernet address of the remote network card. Somewhere in this frame should exist a byte stream (magic sequence) composed by, at the least, 16 times the repetition of the Ethernet address and preceded by a synchronization stream of 6 bytes of 0xFF. 45 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.7.3 Link Change Wakeup The AX88796C supports the PHY link change wake up event by detecting the PHY link status signal. Any time when the internal PHY’s link status changes (one-to-zero or zero-to-one) and the Link-Status Change Wake-up option in the WFCR register bit [8] and bit [5] is enabled, then the AX88786C will detect a link-status change wakeup event and generate a valid PME signal to inform the host processor. When power saving function is turn on, please make sure WFTR register has at least 4 to 8 seconds delay setting to wait for the internal PHY enter the power saving mode when unplug the cable. 4.7.4 GPIO Wakeup The AX88796C supports up to two GPIO pin Wakeup function. Only the pin GPIO0 and pin GPIO1 pin is supported this function. Please make sure the pin GPIO0 and pin GPIO1 is enabled, and the GPIO wakeup register (GPIOWCR) is configured to expected wakeup even state (edge or level triggered). The wakeup function can be enabled if the wakeup enable bit and GPIO enable bit both set to one. And the wakeup status bit will show if the wakeup event is detected or not. The wakeup event can be configured from the GPIO Wakeup Select Register. If the Wakeup Select bit is set to 00 then the wakeup event will be triggered if detect a falling edge. If the Wakeup Select is configured to 01 then any rising edge will trigger wakeup event. GPIO Wakeup Enable Wakeup Status GPIO0 GPIOWR[0] GPIOWR[12] GPIO1 GPIOWR[1] GPIOWR[13] Wakeup Select GPIOWR[5:4] GPIOWR[7:6] TAB - 10 GPIO WAKEUP CONFIGURATION TABLE 46 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.8 Flow Control The AX88796C supports Full-duplex flow control using the pause control frame. It also supports half-duplex flow control using collision base of back-pressure method. 4.8.1 Full-Duplex Flow Control The format of a PAUSE frame is illustrated below. It conforms to the standard Ethernet frame format but includes a unique type field and other parameters as follows: The destination address of the frame may be set to either the unique DA of the station to be paused, or to the globally assigned multicast address 01-80-C2-00-00-01 (hex). The IEEE 802.3 standard for use in MAC control PAUSE frames has reserved this multicast address. The "Type" field of the PAUSE frame is set to 88-08 (hex) to indicate the frame is a MAC Control frame. The MAC Control op-code field is set to 00-01 (hex) to indicate the type of MAC Control frame being used is a PAUSE frame. The PAUSE frame is the only type of MAC Control frame currently defined. The MAC Control Parameters field contains a 16-bit value that specifies the duration of the PAUSE event in units of 512-bit times. Valid values are 00-00 to FF-FF (hex). If an additional PAUSE frame arrives before the current PAUSE time has expired, its parameter replaces the current PAUSE time, so a PAUSE frame with parameter zero allows traffic to resume immediately. A 42-byte reserved field (transmitted as all zeros) is required to pad the length of the PAUSE frame to the minimum Ethernet frame size. Preamble (7-bytes) Dest. MAC Start Frame Address Delimiter (6-bytes) (1-byte) = (01-80-C200-00-01) Source MAC Address (6-bytes) Length/Type (2-bytes) = 802.3 MAC Control (88-08) Fig 21 MAC Control Opcode (2-bytes) = PAUSE (00-01) MAC Control Parameters (2-bytes) = (00-00 to FF-FF) Reserved (42-bytes) = all zeros Frame Check Sequence (4-bytes) PAUSE PACKET FORMAT The AX88796C will inhibit transmit frames for a specified period of time if a PAUSE frame received and CRC is correct. If a PAUSE request is received while a transmit frame is in progress, then the pause will take effect after the transmitting is completed. A programmable of high water free-page-count in “Flow Control Register” used to measure the water level of receive buffer. The AX88796C use XOFF / XON flow-control method to avoid missing packet if receive buffer almost full. A XON transmitting when the total of free page count equal to or less then “high water free-page-count”. A XOFF transmitting when the total of free page count equal to or greater then (“high water free-page-count” + 6 pages). 47 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Fig 22 4.8.2 TX / RX FLOW CONTROL Half-Duplex Flow Control Whenever the receive buffer becomes full crosses a certain threshold level, The MAC starts sending a Jam signal, which will result in a collision. After sensing the collision, the remote station will back off its transmission. The AX88796C only generates this collision-based of back-pressure when it receives a new frame, in order to avoid any late collisions. A programmable of “Back-pressure Jam Limit count” (Offset 17h) is used for avoid HUB port partition due to many continues of collisions. The AX88796C will reset the “Back-pressure Jam Limit count” when either a transmitted or received frame without collision. A back-pressure leakage allow when senses continue of collisions count up to “Back-pressure Jam Limit count”, it will be no jamming one of receive frame even receive buffer is full. 4.9 Auto-Polling Function The AX88786C supports PHY management function through the internal serial MDIO/MDC interface. That is, the AX88786C can access related PHY registers via MDIO/MDC interface after power on reset. The AX88786C will periodically and continuously poll and update the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected PHY devices through MDIO/MDC serial interface. All the polling status will be automatically update in the register MACCR RE [0], FD[1], Speed[2] and RFC/TFC[4:3] location if the auto-polling function is enable in the PCR register bit [0]. The AX88796C also supports indirect read or write internal PHY register through the local bus interface. The MDIOCR and MDIODR registers provide the read or write setting to access the internal PHY register. Please reference these related register information for further detail. 48 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.10 Mixed Endian Byte Ordering The AX88796C supports “Big-“or “Little-endian” processor with 16-bit bus interfaces. The AX88796C provides mixed Endian byte ordering function for user configuration. The following table is to summarize of mixed Endian byte ordering configuration. Additionally, please refer to Byte Order Register (BOR), for additional information on status indication on big- or little-endian modes. The AX88796C provides two bytes of fixed patterns for user confirming the byte lane order configuration. The following table shows the fixed pattern on Byte1 and Byte0. These fixed patterns can be used to determine the byte lane ordering of current configuration. The users can write one to BOR to change the byte ordering. Fixed pattern on Byte Order register (read offset 02h Page 0) Data [15:0] Fig 23 Fixed Value 0x1234 FOUR FIXED PATTERNS FOR BYTE LANE TEST The AX88796C also supports TX/RX packet data swapping function. The FER register bit [8] is the packet data word swap function enable control bit. When enabled this word swap function then the upper word will swap with the lower word packet data. The FER register bit [9] is the packet data byte swap enable function. When enabled this byte swap function by setting one to this bit, then the AX88796C will enable byte swap function on both RX and TX packet data buffer and packet data bit [7:0] will swap to bit [15:8]. The packet data swapping function intends to convert the packet data when the host CPU is processing the packet in different Endian type purpose. 49 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.11 EEPROM Interface The AX88796C can optionally load its MAC address from an external serial EEPROM. If a properly configured EEPROM is detected by the AX88796C at power-up, hard reset or host set a reload EEPROM request, the constants of EEPROM data will be auto loading to internal memory automatically. A detailed explanation of the EEPROM data format in section 3.0 “EEPROM Memory Mapping”. After auto load EEPROM completed, the MAC address will be auto-loaded into the MACASR0~MACASR2 registers (Page3 Offset 02h ~ 06h) and then AX88796C will know its MAC address. In addition to have EEPROM auto load the MAC address, the Host driver can also manually configure the AX88796C MAC address by writing the MACASR0~MACASR2 registers. The AX88796C EEPROM use 3 PINs to connect to a most “93C56/66” type EEPROM configured for x16-bit operation. A connect diagram as below AX88796C 93C56/66 EECS EECK EECS EECK EEDI EEDIO EEDO Fig 24 EEPROM CONNECTIONS After EEPROM loader has finished reading the MAC after power-on, hard reset or host set a reload EEPROM request (CR page3 offset 0Ch), the Host is free to perform EECS, EECK and EEDIO as General Purpose I/O pin. 50 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.12 Power Management Function The AX88796C supports power saving modes to allow applications to minimize power consumption. There is one normal operation power state and there are two power saving states: Power Saving Mode 1 (PS1) and Power Saving Mode 2 (PS2). The “Power Management Register” (Page0 Offset 0Ch) controls those of power management modes. In WOL state, the AX88796C supports Wake on LAN function. In Sleep state, the AX88796C will turn off almost all function block power supply and gated clocks to minimize power consumption. In cable-off power saving 1 and 2 mode the AX88796C will turn off the different functional blocks within the internal PHY to reduce cable off power consumption. After wakeup event, the “Power Management Register” will be cleared and stay at normal operation power state. When the AX88796C is in Sleep mode, the host CPU can write “Host Wake Up Register” (Offset 1Eh) for non-SPI interface or set AX88796C SPI “ABh Exit Power Down (S3)” instruction for SPI interface to return the AX88796C to the normal operation state. The AX88976C Power consumption can be reduced to different level by disabling the different clocks under different power saving mode as outlined in table as below. The AX88796C BLOCK Internal 100MHz clock MAC Rx/Tx clock TX Driver Power Management Block PHY Osc. 25MHz clock Normal PS1 Operation On On On Off On Periodic on On On On On TAB - 11 PS2 WOL Sleep Mode Off Off Off On Off On Off Off On On Off Off Off Off Off POWER MANAGEMENT STATUS The AX88796C support the following power saving states: 1. PS1: Internal Ethernet PHY enter Power Saving state 1 2. PS2: Internal Ethernet PHY enter Power Saving State 2 3. WOL: Internal Ethernet PHY enters Wake-On-LAN power saving State, link to 10MHz to reduce power consumption if the remote PHY support 10M speed. 4. Sleep Mode: Host force the AX88796C enters the sleep state and wait for host wake-up command. The internal Ethernet PHY is in power down state. NOTE; When TCLK is configured to provide reference clock output, Please make sure power saving mode is either disabled or only set on Power Saving Mode 1 (PS1) mode cause the power saving function will gated the output reference clock when turn on. 51 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.12.1 Hardware-detect Cable-Off Power Saving Mode (PSCR [4]=0, default) The AX88796C power management module supports the hardware cable-off power saving function when PSCR [4] software power-saving function is disabled. When the AX88796C hardware detects the cable-off event on Ethernet PHY interface, then power management module will check PSCR [2:0] register setting and automatically change the internal PHY to the correspondent power saving state to reduce the power consumption. If the PSCR [2:0] is set to 001 and the cable-off is detected then the AX88796C will enter Power Saving Mode 1 (PS1) state. If PSCR [2:0] is set to 010 and cable-off is detected then the AX88796C will enter Power Saving Mode 2 (PS2) state. When the Ethernet cable is plug in then power management will change back to the normal ready state. The AX88796C will go back to Normal Operation state when internal PHY detect cable plug-in event from PS1 and PS2 state. 4.12.2 Software Control Cable-Off Power Saving Mode (PSCR [4]=1) The AX88796C supports software control power saving function for Power Saving Mode 2 (PS2). When PSCR [4] is set to one, the host software got the fully control of the internal power saving state transition; the host also needs to set MACCR [6] to enable Software Cable-Off Power Saving Interrupt. The AX88796C will report the cable-off interrupt to the external host through IRQ pin. The host can then program PSCR [2:0] register value to 010 to force the AX88796C enters PS2 state. When the cable plug-in event detected, the host interface can issue a resume command by writing “Host Wake Up Register” (Offset 1Eh) for non-SPI interface or setting AX88796C SPI “ABh Exit Power Down (S3)” instruction for SPI interface to return the AX88796C to the normal operation state. 52 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.12.3 Sleep Mode The host can write one to WFCR [4] sleep mode bit and the AX88796C will enter the sleep mode deep power saving state with Ethernet PHY power down and internal clock shut down. The host interface can issue a resume command by writing “Host Wake Up Register” (Offset 1Eh) for non-SPI interface or setting AX88796C SPI “ABh Exit Power Down (S3)” instruction for SPI interface to return the AX88796C to the normal operation state. Please check the device ready on PSR [7] for non-SPI interface and check the Device Ready bit of AX88796C SPI “05h Read Status” instruction for SPI interface to make sure the chip is in ready state because it will take a few ms for PHY and clock to recover back. It will take about 160ms for the AX88796C internal PHY back to device ready state after the host interface issue the resume command to exit the sleep mode. The software driver can either polling the AX88796C device ready status (PSR) for non-SPI interface, or polling the Device Ready bit of SPI “05h Read Status” register for SPI interface or wait about 160ms before the normal operation. 4.12.4 Wake-On-LAN Power Saving Mode The AX88796C supports the power saving function even the chip is in Wake-On-LAN mode state with WFCR [5] is set to one. The AX88796C can enter Wake-On-LAN power saving mode through the following two ways: 1. Hardware-enabled power saving control: When the AX88796C is in WOL state and the Ethernet cable is unplugged and PSCR [5] is pre-configured to one. 2. Software-enabled power saving control: When software detect link done on WOL mode then software can write one to PSCR [5] to turn on power saving mode When the AX88796C enter the WOL power-saving mode, the internal Ethernet PHY will check remote PHY’s speed ability and try link to 10MHz speed in order to reduce the power consumption when waiting the wake up event to be triggered. 53 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.13 Checksum Offload Function The AX88796C Checksum Offload function supports Layer 3 IPv4, Ipv6 protocol and Layer 4 TCP, UDP, ICMP, ICMPv6 and IGMP protocol include receive packet checksum value check and transmit packet checksum calculation and replacement offload CPU loading. The detail of the AX88796C Checksum Offload Function list below:  IP header parsing, including Ipv4 and Ipv6  Ipv4 header checksum check and generation (There is no checksum field in Ipv6 header)  Version error detecting on RX direction for IP packets with version not equal to 4 or 6  Detect RX IP packet header checksum error  TCP and UDP checksum check and generation  ICMP, ICMPv6 and IGMP message checksum check and generation The AX88796C supports the following Layer 2 Protocols checksum offload processing. 1. Ethernet II Encapsulation (RFC894) DA SA L/T Ver,HL TOS Total Ident. Flag/Frag = 4X length no offset TTL Protocol Header chksum Source IP addr Dest IP addr Option Data 20 bytes 46~1500 bytes (IPv4 packet) 2. IEEE 802.2/802.3 SNAP Encapsulation (RFC 1042) This Ipv4 packet format is the same as above except that the Ipv4 packet length has changed to 38~1492 bytes instead. DA SA Length < 0600 LLC Org. code Etype = AAAA03 = 000000 = 0800 IP datagram (38~1492 bytes) 22 bytes 54 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 3. Ethernet II Encapsulation (RFC894) with VLAN-tagged This Ipv4 packet format is the same as above without VLAN-tagged case. In other words, in addition to DA, SA, and Etype bytes in the MAC frame, there are the VLAN Tag byes: ETPID and TCI. DA SA ETPID TCI Etype = 8100 = 0800 18 bytes IP datagram (46~1500 bytes) (Ethernet II IP packet with VLAN Tag) 4. Ethernet II Encapsulation (RFC894) with stacked VLAN-tag (QinQ) This Ipv4 packet format is the same as above without VLAN-tagged case. There are two VALN tags, including ETPID and TCI field (stacked VLAN). DA SA ETPID TCI ETPID TCI Etype = 8100 = 8100 = 0800 IP datagram (46~1500 bytes) (Ethernet II IP packet with stacked VLAN Tag) 24 bytes 5. IEEE 802.2/802.3 SNAP Encapsulation (RFC 1042) with VLAN-tagged This Ipv4 packet format is the same as above without VLAN-tagged case and the packet length is 38~1492 bytes long. So in addition to DA, SA, Length, LLC, Org. code, and Etype bytes in MAC frame, the L2_Engine shall also remove the VLAN Tag byes: ETPID, TCI, and RIF bytes, before sending the packet towards L3_Engine. DA SA ETPID TCI Length (RIF) LLC Org. code Etype =8100 < 0600 = AAAA03 = 000000 = 0800 IP datagram (38~1492 bytes) 26 bytes 55 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6. PPPoE Encapsulation with VLAN-tagged PPPoE frames with (Etype = 8864 and Protocol = 0021) will have their IP/UDP/TCP/ICMP/IGMP checksums checked by L3/4 Engine. All other PPPoE frames with (Etype = 8863) or (Etype = 8864 and Protocol != 0021) will be treated as non-IP packets and passed to the software. PPPoE Header DA unicst SA Etype Ver/Tye Code = 8864 = 11 1 byte 1 byte PPPoE Payload Session Payload ID Length 2 bytes 2 bytes Protocol = 0021 2 byte IP header + UDP/TCP/ICMP/IGMP (IP/UDP/TCP/ICMP/IGMP checksum are in here) (38~1492 bytes) 22 bytes (IP packets in PPPoE Session stage) Layer 3 Processing The Layer 3 engine includes checksum check and generation, header parsing, functions in Ipv4 and header parsing function in Ipv6. The checksum engine will calculate the checksum of Ipv4 header and compare it with received checksum value. The checksum engine is used for pseudo header checksum calculation in Ipv6. The block also calculates the checksum for the transmitted IP header. The header parser will parse the Ipv4 header and capture some fields into registers for further processing by other blocks. In order to speed up the L4 checksum calculation and reduce the latency, L3 engine will control the L4 engine to pre-calculate the L4 pseudo header (protocol, SIP and DIP). The following received IP packets will be discarded by the L3 Engine.    Ethernet type is 0800 but IP version not equal to 4 Ethernet type is 86dd but IP version no equal to 6 Ipv4 header checksum error 56 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller Ipv6 frame The L3 engine supports Ipv6 frame, the Ipv6 parser can indicate the correct start point of L4 frame and pre-calculate the pseudo header check sum for L4 packet. DA SA Ether type IPv6 header = 86dd Extension header IPv6 datagram L4 datagram L4 header 0 or more bytes 40 bytes IPv6 packet format Version (4bit) Flow Label (20bit) Traffic Class (8bit) Next Header (8bit) Payload Length (16bit) Hop Limit (8bit) Source Address (128bit) Destination Address (128bit) IPv6 header format DA SA Ether type IPv6 header = 86dd Routing header IPv6 datagram TCP header TCP datagram Next Header = TCP Next Header = Routing Header IPv6 TCP packet with Routing Header DA SA Ether type IPv6 header Routing header = 86dd Next Header = Routing Header frag header IPv6 datagram TCP header TCP datagram Next Header = TCP Next Header = fragment Header IPv6 TCP packet with Routing Header and Fragment Header Fig 25 IPV6 PACKET FORMAT 57 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 4.14 GPIO Function The AX88796C has an optional feature to support up to four GPIO functions through multi-functional pin out when some of the functional pin is not enabled. Each GPIO pin is able to trigger interrupt event and only GPIO0 and GPIO1 support wakeup function and pass PME event to external host. GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO Enable GPIOER[0] GPIOER[1] GPIOER[2] GPIOER[3] Input GPIOER[4] GPIOER[5] GPIOER[6] GPIOER[7] Output GPIOER[8] GPIOER[9] GPIOER[10] GPIOER[11] Output Enable GPIOER[12] GPIOER[13] GPIOER[14] GPIOER[15] Interrupt Enable GPIOCR[0] GPIOCR[1] GPIOCR[2] GPIOCR[3] Interrupt Mask GPIOCR[12] GPIOCR[13] GPIOCR[14] GPIOCR[15] Interrupt Status GPIOCR[8] GPIOCR[9] GPIOCR[10] GPIOCR[11] Interrupt Select GPIOCR[4] GPIOCR[5] GPIOCR[6] GPIOCR[7] TAB - 12 GPIO CONFIGURATION TABLE When GPIO Enable is set to one, GPIO pin will be configured to output pin and pass output data from register to pin if the correspondent Output Enable is set to one. Otherwise, if output enable is set to zero then GPIO pin will consider as input pin and pass the pin data save to input register. The GPIO pins support the interrupt function if the interrupt enable bit and GPIO enable bit both set to one. The Interrupt Select register will define interrupt polarity active high if set to one or active low if set to zero. The interrupt mask register is able to mask the interrupt if the mask bit is set to one. The interrupt status value can read out from the Interrupt Status register and write one to clear the interrupt status bit. 58 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.0 SPI Interface 5.1 Introduction The AX88796C SPI slave module provides the interface between the host’s SPI master and the AX88796C’s local bus interface. It is compatible with the SPI serial bus interface. The host SPI can access the whole AX88796C’s internal registers space, TX FIFO and RX FIFO through SPI master commands. 5.2 Features        SPI compatible serial bus interface Supports mode 0 and mode 3 timing modes Supports maximum operation frequency up to 40MHz for all SPI access modes Supports special command to clear the SPI mode status bits. Supports the “Exit power down” command to wake up the AX88796C from the power saving or WOL suspend mode. Supports the SPI interrupt Supports register/status odd byte(s) access. 59 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.2.1 Mode Access The AX88796C supports mode 0 and mode 3 SPI timing modes. Mode 0: Timing diagram (the access length is based on command) SCLK MOSI MSB D6 D5 D4 D3 D2 D1 LSB MISO MSB D6 D5 D4 D3 D2 D1 LSB SS Bit sample time Note: SPI CLK (SCLK) pin needs external pull-down resistor and SSn pins need external pull-up resistor in Mode 0, SPI master mode. Mode 3: Timing diagram. (the access length is based on command) SCLK MOSI MSB D6 D5 D4 D3 D2 D1 LSB MISO MSB D6 D5 D4 D3 D2 D1 LSB SS Bit sample time Note: SPI CLK (SCLK) pin needs external pull-up resistor and SSn pins need external pull-up resistor in Mode 3, SPI master mode. Fig 26 SPI TIMING DIAGRAM 60 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.3 SPI Module Operation To access the TX FIFO and RXFIFO, the AX88796C SPI data transfer only supports the word access (16 bits). If there is a non-word data transfer for the TX FIFO and RX FIFO access, then the SPI slave module will issue an interrupt and raise a non-Word access flag to the SPI interrupt status register to indicate this error. For the internal register read or write access, the AX88796C can read or write all internal register’s odd bytes. There is a SPI status read command “05H” to read out the internal SPI status and the AX88796C interrupt status. The status output order are: the AX88796C status first (interrupt status) Low byte-> and the AX88796C status (interrupt status) High byte-> and the SPI status byte last. If the SPI slave module receives a un-define SPI command, the AX88796C SPI slave module will issue an interrupt and raise the un-define command access flag in the SPI interrupt status register to indicate this error. 61 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.4 Instruction Set Summary 5.4.1 SPI Mode Instruction Table Instruction Description 03h Read Data Read from register Compression = 0 Read from register Compression = 1 Writ Register compression=0 D8h Write Register 0Bh Fast Read Data RXQ Read Compression = 0 RXQ Read Compression = 1 02h TXQ Page Program write Compression =0 TXQ Compression =1 38h Enter QCS mode Enable QCS Mode FFh Reset mode bit to Reset Mode bit abort register random read 05h Read Status Read Status ABh Exit Power Down Exit Power Down(S3) B2h RXQ Read and TXQ Bi-direction Fast program read and program Compression =0 RXQ Read and TXQ program Compression =1 X: This parameter is not required. Op code Address Dummy Data Note Cycles Cycles Cycles 03h 8 16 8 03h 8 8 8 D8h 8 X 8 0Bh X 32 16-∞ 0Bh X 8 16-∞ 02h X 24 16-∞ 02h X X 16-∞ 38h X X X FFh X X X 05h X X 24 ABh X X X B2h X 32 16~∞ B2h X 8 16~∞ TAB - 13 SPI MODE INSTRUCTION TABLE NOTE: The RXQ means the RX FIFO or the RX memory access within the AX88796C core and the TXQ means the TX FIFO or the TX memory access. 62 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.5 Commands Waveform 5.5.1 SPI Mode NOTE : Signal SIO0 SIO1 SS_n Sclk Pin Name MOSI MISO SSn SPI_CLK 5.5.1.1 Read command 03h Register Read Command (SPICR SPI_r_compression = 0) 03h Register Read Command (SPICR SPI_r_compression = 1) 63 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 0Bh Fast RXQ Read Command (SPICR SPI_q_Compression = 0) 0Bh Fast RXQ Read Command (SPICR SPI_q_compression = 1) 64 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.5.1.2 Write command D8h Register Write Command 02h TXQ Write Command (SPICR SPI_q_compression =0) 02h TXQ Write Command (SPICR SPI_q_compression =1) 65 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 38h Enable QCS Mode 05h Read SPI Status Command ABh Exit Power Down Command (S3) 66 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller B2h Fast RXQ/TXQ Write Command (SPICR SPI_q_compression =0) B2h Fast RXQ/TXQ Write Command (SPICR SPI_q_compression =1) 67 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 5.6 SPI Status Access When the host SPI Master use the status read command “05h” to access the AX88796C interrupt status and SPI status. The status output order are: the AX88796C status come out first (interrupt status, Low byte)-> and the AX88796C status (interrupt status, High byte)-> and the SPI status byte last. For the interrupt status, please reference the register page 0 offset 0x06 for detail description. For the SPI status content, please check the following table. Bit Name [0] TXQ_IC/ RXQ_IC [1] [6:2] Reserved PMM_ST[4:0] Default R/W Value 0 R 0 R 00000 R [7] R Device Ready 0 Description TXQ initial complete/RXQ initial complete: Complete SPI TXQ or RXQ data path clear. If SPI slave get the TXQ/RXQ initial signal from TXQ/RXQ, SPI will clear TX/RX data paths. 1: SPI get TXQ/RXQ initial and clear TX/RX data path content already. 0: SPI didn’t get TXQ/RXQ initial signal or it is still doing TX data path clear. Reserved Power Management Module Status 00001: Chip Reset State 00010: Wait State 00011: Device Ready State (Normal Operation) 00100: PS1 State (Cable-off) 00101: PS2 State (Cable-off) 00111:Wake-On-LAN State 01000 PS1 and Wake-On-LAN State (Cable-off) 01001: PS2 and Wake-On-LAN State (Cable-off) 01010: Sleep Mode 01011: PHY in Reset State 10000: Software force in PS1 State 10001: Software force in PS2 State Device Ready Status. 1: Device ready(register access available) 0: Device not ready yet(register access unavailable) TAB - 14 SPI STATUS TABLE 68 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.0 Registers Description 6.1 Internal Register Mapping Table All the AX88796C internal registers are 16-bit wide. The Offset 0x02 to 0x1D mapped into page0 ~ page7, which are selected by PS (Page Select) in the Page Select Register (PSR, Offset 0x00). The Offset 0x1E and 0x1F through page 1 to page 7 are shared registers for chip level control purpose. Offset Page0 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E BOR 0x1234 FER 0x0043 ISR 0x0000 IMR 0xFFFF WFCR 0x0000 PSCR 0x1820 MACCR 0x0318 TFBFCR 0x001F TSNR 0x0040 RTDPR 0x0000 RXBCR1 0x0000 RXBCR2 0x4000 RTWCR 0x0000 RCPHR 0x0000 Page1 Page2 PSR 0x8040 (Register Default Value) RPPER ICR 0x0000 0x0000 PCR 0x1002 PHYSR 0x05FF MRCR MDIODR 0x2000 0x0000 MDR MDIOCR 0x0000 0x0000 RMPR LCR0 0x0101 0x0204 TMPR LCR1 0x0101 0x1508 RXBSPCR IPGCR 0xC000 0x120C RXMCR CRIR 0x0900 0x0000 FLHWCR 0x4224 RXCR 0x0001 JLCR 0x043F MPLR 0x0600 Remote Wakeup Register (RWR) 0x0000 69 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. Page3 MACASR0 0x0000 MACASR1 0x0000 MACASR2 0x0000 MFAR01 0x0000 MFAR23 0x0000 MFAR45 0x0000 MFAR67 0x0000 VID0FR 0x0000 VID1FR 0x0000 EECSR 0x0000 EEDR 0xFFFF EECR 0x2000 TPCR 0x1500 TPLR 0x0048 AX88796C Low-Power SPI or Non-PCI Ethernet Controller Offset 0x00 Page4 0x02 GPIOER 0x0000 GPIOCR 0xF000 GPIOWCR 0x0000 0x04 0x06 0x0C SPICR 0x0C00 SPIISMR 0xFF00 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E Page6 Page7 PSR 0x8040 0x08 0x0A Page5 COERCR0 0x0000 COERCR1 0x0000 COETCR0 0x0000 COETCR1 0x0000 WFTR WF2CR 0x0000 0x0000 WFCCR WF2OBR 0x0000 0x0000 WFCR03 WF3BMR0 0x0000 0x0000 WFCR47 WF3BMR1 0x0000 0x0000 WF0BMR0 WF3CR 0x0000 0x0000 WF0BMR1 WF3OBR 0x0000 0x0000 WF0CR WF4BMR0 0x0000 0x0000 WF0OBR WF4BMR1 0x0000 0x0000 WF1BMR0 WF4CR 0x0000 0x0000 WF1BMR1 WF4OBR 0x0000 0x0000 WF1CR WF5BMR0 0x0000 0x0000 WF1OBR WF5BMR1 0x0000 0x0000 WF2BMR0 WF5CR 0x0000 0x0000 WF2BMR1 WF5OBR 0x0000 0x0000 Remote Wakeup Register (RWR) 0x0000 70 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. WF6BMR0 0x0000 WF6BMR1 0x0000 WF6CR 0x0000 WF6OBR 0x0000 WF7BMR0 0x0000 WF7BMR1 0x0000 WF7CR 0x0000 WF7OBR 0x0000 WFR01 0x0000 WFR23 0x0000 WFR45 0x0000 WFR67 0x0000 WFPC0 0x0000 WFPC1 0x0000 AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.1 Page 0 Offset 0x00: Page Select Register (PSR) Bit Name [2:0] PS[2:0] [3] [6:4] AddressShifter Bus Setting [7] Device_Ready [14:8] [15] Reserved Soft reset Default R/W Function Value 000 RW Page Select The three bits select which register’s page is to be accessed. PS[2] PS[1] PS[0] Page Number 0 0 0 Page 0 (Default Page) 0 0 1 Page 1 0 1 0 Page 2 0 1 1 Page 3 1 0 0 Page 4 1 0 1 Page 5 1 1 0 Page 6 1 1 1 Page 7 0 RW Shift SA3~SA0 to SA4~SA1 for address decode process. 100 R Bus Setting Bus Function 000 8-bit SRAM-like bus (AEN should be pull-low.) 001 8-bit Address/Data multiplexed bus (AEN=1 address cycle, AEN=0 data cycle). Pin SD7 ~ SD0 is used. SD5 ~ SD0 represent address bus when AEN =1. SD7 ~SD0 represent data bus when AEN=0. CSN should be low when the AX88796C is selected. 010 Reserved 011 MCS-51 (805x) (PSEN/AEN active high) 100 16-bit SRAM-like bus (AEN should be pull- low.) 101 16-bit Address/Data multiplexed bus (AEN=1 address cycle, AEN=0 data cycle) Pin SD15 ~ SD0 is used. SD5 ~ SD0 represent address bus when AEN =1. SD0 ~SD15 represent data bus when AEN=0. CSN should be low when the AX88796C is selected. 110 SPI Mode (AEN unused and can be pull-low if GPIO mode is unused.) 111 16-bit local bus with byte write enable (Renesas SHx style, AEN = low byte SD7~SD0 enable, WRn = low byte SD15 ~ SD8 enable) 0 R Device ready status 1: Device ready 0: Device not ready yet 0x00 R Reserved 1 RW Whole chip software reset (Active Low) 1: Normal (Default) 0: Reset the whole chip 71 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.2 Page 0 Offset 0x02 : Byte Order Register (BOR) Bit Default R/W Function Value [15:0] ByteSwap_EN 0x0000 W Byte Swap function for all register If ByteSwap_EN=0x0000 (by default), SD bus = SD [15:0] If ByteSwap_EN≠0x0000 (by default), SD bus = {SD [7:0], SD [15:8]} [15:0] Test Byte 0x1234 R Test pattern to check Endian swap result Note: Driver should always read out the register value 0x1234 or 0x3412 to decide whether the bus is little endian or big endian. 6.1.3 Name Page 0 Offset 0x04: Function Enable Register (FER) Bit Name Default R/W Function Value 1 RW RX IP header aligned 32-bit. 1: Enable RX IP header aligned double word. (Default) [0] IPALM [1] DropCRC 1 [2] RH3M 0 [4:3] TCLK_SELECT 00 [5] One_RnW 0 [6] ALECLK_HL 1 [7] [8] Reserved WordSwap_EN 0 0 [9] ByteSwapF_EN 0 [10] IRQ_Active 0 [11] IRQ_TYPE 0 0: Disable RX IP header aligned double word [13:12] RESERVED [14] RX Bridge Enable 00 0 [15] 0 TX Bridge Enable RW RX Drop CRC Enable. 1: CRC byte is dropped on received MAC frame forwarding to host 0: CRC byte is not dropped. RW Checksum 2 byte + dummy 2 byte 1: RX Header 3 Csum append. 0: Disable RX Header 3 Header append (default). RW TCLK Output clock select 00: No clock output(Default) 01: 25MHz clock output 10: 50MHz clock output 11: 100MHz clock output RW RDn use enable 0:RDn use 1:RDn doesn’t use,WRn replease RDn RW ALE Clock Select 1: positive edge trigger 0: negative edge trigger R Reserved RW Word Swap function for TX and RX Bridge (Packet data only) 0: Disable (default) 1: Word swap enable RW Byte Swap function for TX and RX Bridge (Packet data only) 0:Disable (default) SD bus = SD [15:0] 1:Enable byte swap function SD bus = {SD [7:0], SD [15:8]} RW Interrupt active high/low selection 1: Interrupt active high 0: Interrupt active low (default) RW Interrupt I/O Buffer Type 0: Enable IRQ to function as an open-drain buffer for use in a wired-OR interrupt configuration. The interrupt output is always active low. 1: IRQ output is a Push-Pull driver RW Reserved RW RX Bridge Enable 1: Enable RX Bridge 0: Disable RX Bridge RW TX Bridge Enable 1: Enable TX Bridge 0: Disable TX Bridge 72 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.4 Page 0 Offset 0x06: Interrupt Status Register (ISR) Bit Name [0] RXPCT [1] [2] [3] [4] Reserved Reserved Reserved MDQ [5] TXT [6] TX_Pages [7] [8] Reserved TXERR [9] LinkChange [10] GPIO [11] SPI [15:12] Reserved Default R/W Function Value 0 R/WC RX packet receive status bit 1: RX interrupt active 0: RX interrupt inactive Write 1 to clear this interrupt event. 0 R/WC Reserved 0 R/WC Reserved 0 R/WC Reserved 0 R/WC TX manual dequeue interrupt 1: TX manual dequeue interrupt active 0: TX manual dequeue interrupt inactive Write 1 to clear this interrupt event. 0 R/WC TX packet transmit complete interrupt 1: TX packet transmit complete interrupt active 0: TX packet transmit complete interrupt inactive Write 1 to clear this interrupt event. 0 R/WC TX Free Page buffer more than driver require interrupt 1: TX_Pages interrupt active 0: TX_Pages inactive Write 1 to clear this interrupt event. 0 R/WC Reserved 0 R/WC TX packet error interrupt status bit 1: TX packet error interrupt active 0: TX packet error interrupt inactive Write 1 to clear this interrupt event. 0 R/WC PHY Link Change interrupt status bit 1: PHY Link Change interrupt active 0: PHY Link Change not detect Write 1 to clear this interrupt event. 0 R/WC GPIO interrupt status bit 1: GPIO interrupt active 0: GPIO interrupt inactive Write 1 to clear this interrupt event. 0 R/WC SPI interrupt status bit 1: SPI interrupt active 0: SPI interrupt inactive Write 1 to clear this interrupt event. 0 R/WC Reserved 73 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.5 Bit Page 0 Offset 0x08: Interrupt Mask Register (IMR) Name [0] RXPCT_mask [1] [2] [3] [4] Reserved Reserved Reserved MDQ_mask [5] TXT_mask [6] TX_Pages_mask [7] [8] Reserved TXERR_mask [9] LinkChange_mask [10] GPIO_mask [11] SPI_mask [15:12] Reserved Default R/W Function Value 1 RW RX packet receive interrupt mask bit 1: Mask RX packet interrupt on IRQ pin 0: Unmask RX packet interrupt on IRQ pin 1 RW Reserved 1 RW Reserved 1 RW Reserved 1 RW TX manual dequeue interrupt complete 1: Mask TX manual dequeue interrupt on IRQ pin 0: Unmask TX manual dequeue interrupt on IRQ pin 1 RW TX packet transmit complete interrupt mask 1: Mask TX packet transmit complete interrupt on IRQ pin 0: Unmask TX packet transmit complete interrupt on IRQ pin 1 RW TX Free Page buffer more than driver require interrupt mask 1: Mask TX Pages interrupt on IRQ pin. 0: Unmask TX Pages on IRQ pin. 1 RW Reserved 1 RW TX packet error interrupt mask bit 1: Mask TX packet error interrupt on IRQ pin 0: Unmask TX packet error interrupt on IRQ pin 1 RW PHY Link Change interrupt mask bit 1: Mask PHY Link Change interrupt on IRQ pin 0: Unmask PHY Link Change interrupt on IRQ pin 1 RW GPIO interrupt mask bit 1: Mask GPIO interrupt on IRQ pin 0: Unmask GPIO interrupt on IRQ pin 1 RW SPI interrupt mask bit 1: Mask SPI interrupt on IRQ pin 0: Unmask SPI interrupt on IRQ pin 111 RW Reserved 74 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.6 Bit Page 0 Offset 0x0A: Wakeup Frame Configuration Register (WFCR) Name [0] PME_IND Default R/W Function Value 0 RW PME indication 0: A static signal active when detect wake-up event. (Default) 1: A pulse when detect wake-up event. [1] PME_TYPE 0 RW PME I/O Type. When cleared, PME_POL is ignored, and the output is always active low. 0: PME to function as an open-grain buffer for use in a wired-or configuration. (Default) 1: PME output is a Push-Pull driver. [2] PME_POL 0 RW PME Polarity. 0: PME active low (Default) 1: PME active high (ignore when PME_TYPE is low) PME_POL PME_TYPE PME_IND PME 0 0 0 zzz [3] Reset_pme 0 [4] Sleep mode 0 [5] Wakeup mode 0 [7:6] PME_pulse 00 [8] En_linkchange 0 0 0 1 zzz 0 1 0 0 1 1 1 0 0 zzz 1 0 1 zzz 1 1 0 1 1 1 zzzzzzz zzzzzzz RW Reset PME pin to default value before re-start WOL detection 1: Reset PME 0: Normal WC 1: Sleep/Suspend Mode. The switch will turn off all the internal clocks. And the chip is in the minimum power consumption state. 0: Disable sleep mode The host CPU can write “Host Wake Up Register” (Offset 1Eh) for non-SPI interface or set AX88796C SPI “ABh Exit Power Down (S3)” instruction for SPI interface to return the AX88796C to the normal operation state. RW 1: Enable Wake-On-LAN detection function 0: Disable Wakeup mode RW PME_pulse. 00:2ms 01:8ms 10:32ms 11:64ms RW Enable link status change as one of the wake up condition. Wakeup condition: PHY link done status toggle from low to high or high to low. 1: Enable 0: Disable 75 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller [9] En_MagicPacket 0 [10] En_WakeUpframe 0 [11] PME_Enable 0 [12] Linkchange_status 0 [13] MagicPacket_status 0 [14] WakeUpframe_stat 0 us [15] PME_status 0 RW Enable Magic Packet detection as one of the wake up condition. Wakeup condition: Detect 0xFFFFFFFFFFFF follow by repeated 16 times DA_MAC pattern anywhere within the payload and good CRC value present. 1: Enable 0: Disable RW Enable Microsoft wakeup frame detector as one of the wakeup condition. Wakeup condition: Calculate CRC value across all the mask bits that match the expected CRC value and the packet has a good CRC value in the end. 1: Enable 0: Disable RW 1: Enable PME pin 0: Tri-state PME signal R Link change status 1: Link change event found 0: Idle R Magic frame detection status 1: Magic Frame found 0: Idle R Microsoft wakeup detection status 1: Microsoft wakeup frame found 0: Idle R PME status 1: PME output is high 0: PME output is low 76 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.7 Page 0 Offset 0x0C: Power Saving Configuration Register (PSCR) Bit Name [2:0] PowerSaving [3] [4] Reserved SWPowerSavingEn [5] WOLPowerSaving_en [6] SW_WOL [7] [8] [9] [10] [11] Reserved Reserved Reserved Reserved PHY_ Reset [12] PHY_Cabsilent [13] PHY_Cableoff [14] PHY_Link [15] EEPROM_OK Default R/W Function Value 000 RW PHY power saving state configurable register 000: Disable Power saving function 001: Cable Off Power Saving Level 1 010: Cable Off Power Saving Level 2 0 RW Reserved 0 RW Software power saving control enable 1: Software Control Power Saving Function 0: Select [12:8] as pre-configure power saving mode 1 RW WOL power saving enable 1: Enable power saving when WOL (Link to 10M) 0: Normal NOTE: Please set to 0 when ARP and NS offload function is enabled. 0 RW Software WOL Select enable 1: Software configure [13] WOLPowerSaving_en bit dynamically 0: Always use [13] as pre-defined WOLPowerSaving_en value(Default) 0 RW Reserved 0 RW Reserved 0 RW Reserved 0 RW Reserved 1 RW PHY reset signal. Active low and should be longer than 500ns. 1: Normal 0: Reset internal PHY The host CPU should write one to enable PHY back to normal state if this bit is set to 0. 1 R PHY Cable-off detect enable. Toggling when receive signal. 1: Cable-off detect 0: No Cable-off detect 0 R PHY Cable off 1: PHY Detect cable off 0: Normal 0 R PHY Link Status 1: PHY in Link state 0: PHY not Link yet 0 R EEPROM load complete 1: EEPROM load complete. Please also check EECSR register data. If EECSR data is 0xFF then external EEPROM does not exist 0: EEPROM not finish loading due to checksum failure 77 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.8 Page 0 Offset 0x0E: MAC Configuration Register (MACCR) Bit Name [0] RE [1] FD [2] Speed [3] RFC [4] TFC [5] TXAbortAllow [6] [7] Reserved PF [12:8] PMM_st [15:13] Reserved Default R/W Function Value 0 RW RX path Enable 1: Enable RX path of the ASIC. 0: Disabled (default). 0 RW Full-Duplex 1: Full Duplex mode (default). 0: Half Duplex mode. 0 RW Speed mode 1: 100 Mbps (default). 0: 10 Mbps. 1 RW RX Flow Control Enable 1: Enable RX Flow Control 0: Disable (Default) 1 RW TX Flow Control Enable 1: Enable TX Flow Control 0: Disable (Default) 0 RW Allow TX Abort 1: Enable 0: Disable 0 RW Reserved 0 RW Check only “length/type” field for Pause Frame. 1: Enable. Pause frames are identified only based on L/T filed. 0: Disabled. Pause frames are identified based on both DA and L/T fields (default). 00011 R Power Management Module Status 00001: Chip Reset State 00010: Wait State 00011: Device Ready State (Normal Operation) 00100: PS1 State (Cable-off) 00101: PS2 State (Cable-off) 00111:Wake-On-LAN State 01000 PS1 and Wake-On-LAN State (Cable-off) 01001: PS2 and Wake-On-LAN State (Cable-off) 01010: Sleep Mode 01011: PHY in Reset State 10000: Software force in PS1 State 10001: Software force in PS2 State 0x00 R Reserved 78 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.9 Bit Page 0 Offset 0x10: TX Free Buffer Count Register (TFBFCR) Name [6:0] [12:7] TX_FreeBuf TX_Pages[5:0] [13] TX_Pages_Set [14] TXDPT_start [15] TX_Transmit Default R/W Function Value 0x1F R Indicate how many free page buffers in TX packet memory. 0 RW Driver set this register to let 796C know how many tx page that driver require. 0 WC If driver set this bit and TX_Pages[5:0] , then the AX88796C will compare TX_FreeBuf and TX_Pages[5:0] , if TX_FreeBuf[5:0] value big then TX_Pages[5:0], the AX88796C will send TX_Pages interrupt to CPU. (Interrupt status in page0 offset 6 , bit 6) 0 WC Set 1 to start or restart TX dispatch timer. Reference page 1, offset 6, bit [15-8]. 0 WC If Interrupt assert and manual-enqueue status set, CPU should set this bit to 1 to continue transmit packet. 6.1.10 Page 0 Offset 0x12: TX Sequence Number Register (TSNR) Bit Name [4:0] TXB_SN[4:0] [5] TXB_ERR [6] TXB_Idle [7] [13:8] [14] [15] Reserved TXB_PktCnt[5:0] TXB_reinitial TXB_Start Default R/W Function Value 0 R Sequence number in TX Bridge. Cpu can read this signal to know the last succeed transmit packet’s sequence number. 0 R Indicate TX Bridge in error state. 1: TX Bridge in error state. 0: TX Bridge not in error state. 1 R Indicate TX Bridge in idle state. 1: TX Bridge in idle state. 0: TX Bridge not in idle state. 0 R Reserved 0 RW Indicate how many packets will send from CPU to TX Bridge. 0 WC Set this bit to 1 can let TX Bridge module state machine reinitialize. 0 WC Indicate TX Bridge start to receive packet from CPU. 6.1.11 Page 0 Offset 0x14: RX/TX Data Port Register (RTDPR) Bit Name [15:0] TXB_Data [15:0] RXB_Data Default R/W Function Value 0 W The host CPU can use this register to write TXB_Data[15:0] to TX Bridge. 0 R The host CPU can read RXB_Date[15:0] from RX Bridge. 6.1.12 Page 0 Offset 0x16: RX Bridge Control Register 1 (RXBCR1) Bit Name [13:0] RXB_BL [14] RXB_discard [15] RXB_start Default R/W Function Value 0 RW The host CPU should set this register to tell RX Bridge module how many DMA burst (in word count) will send. 0 WC The host CPU can set this bit to discard current packet in RX Bridge module. 0 WC The host CPU should set this bit to 1 before DMA burst read packet. 79 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.13 Page 0 Offset 0x18: RX Bridge Control Register 2 (RXBCR2) Bit Name [7:0] RXPC [12:8] [13] RXB_SN[4:0] RXB_Ready [14] RXB_Idle [15] RXB_Reinitial Default R/W Function Value 0 R The host CPU can read this register to know how many packets in RX memory. Before read this register, the CPU should set RX_Latch register to 1 in page 0 offset 0x1A bit 15. 0 R Indicate current packet’s sequence number in RX Bridge 0 R Indicate RX Bridge is ready for read. After CPU set RXB_start, the CPU should polling this register to make sure RX Bridge is ready for read or burst read. 0: RX Bridge is not ready for host CPU read or burst read operation 1: RX bridge is ready for host CPU read or burst read operation 1 R Indicate RX Bridge in idle state. 1: RX Bridge in idle state. 0: RX Bridge not in idle state. 0 WC Set this bit to 1 can let RX Bridge module state machine reinitialize. 6.1.14 Page 0 Offset 0x1A: RX Total Valid Word Count Register (RTWCR) Bit Name [13:0] RXWC [14] [15] Reserved RX_Latch Default R/W Function Value 0 The host CPU can read this register to know total packet word count in R RX memory, and then the CPU use this register to set the RXB_BL field of RXBCR1 register. Before read this register, the CPU should set RX_Latch register to 1 in page 0 offset 0x1A bit 15. 0 R Reserved 0 WC Before the CPU read RXWC[13:0] register in page 0 offset 0x1A or RXPC[7:0] register in page 0 offset 0x18 , the CPU should set this register to 1 first. 6.1.15 Page 0 Offset 0x1C: RX Current Packet Header Register (RCPHR) Bit [15:0] Name RXB_FFL Default R/W Function Value 0 R The host CPU can read this register to get current packet’s header1 in RX Bridge module. Bit 15 : indicate this packet is multicast or broadcast packet. 1: this packet is multicast or broadcast packet. 0: this packet is unicast packet Bit 14 : indicate this packet is runt packet. 1: this packet is runt packet. 0: this packet is normal size packet Bit 13 : indicate this packet got MII interface error. 1: this packet got MII interface error. 0: this packet no MII interface error Bit 12 : indicate this packet got CRC error. 1: this packet got CRC error. 0: this packet no CRC error Bit 11:Reserved Bit 10-0 : indicate this packet’s length. 80 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.16 Page 0 ~ 7 Offset 0x1E: Remote Wakeup Register (RWR) Bit [15:0] Name Sleep_mode_exit Default R/W Function Value 0x0000 WC Any write command to this address will cause the chip exit the sleep mode and back to normal mode operation. (This register is only valid for non-SPI interface.) Note: Any write to this register within any page for non-SPI interface will resume the AX88796C back to normal state; please set AX88796C SPI “ABh Exit Power Down (S3)” instruction for SPI interface to resume AX88796C back to normal state. 6.1.17 Page 1 Offset 0x02: RX Packet Process Enable Register (RPPER) Bit Name [0] RX Packet Enable [6:1] [7] [14:8] [15] Reserved Reserved Reserved Reserved Default R/W Function Value 0 RW 0 : RX packet process disable 1: RX packet process enable NOTE: Please write 1 to this bit to enable normal RX packet processing. 0x00 RW 0 R Reserved 0x00 RW Reserved 0 R Reserved 6.1.18 Page 1 Offset 0x08: Memory Read/Write Control Register (MRCR) Bit Name [11:0] [12] MM_Addr MM_RW [13] [14] [15] MM_ready MM_RX MM_TX Default R/W Function Value 0x000 RW TX/RX memory address. 0 WC Set 1 to read/write TX/RX memory. 1: read memory 0: write memory 1 R Indicate read or write memory finish. 0 WC Set 1 to access RX memory 0 WC Set 1 to access TX memory 6.1.19 Page 1 Offset 0x0A: Memory Data Register (MDR) Bit [15:0] Name MM_Data Default R/W Function Value 0x0000 RW Data to write TX/RX memory or read from TX/RX memory. 6.1.20 Page 1 Offset 0x0C: RX Memory Pointer Register (RMPR) Bit [7:0] [15:8] Name Default R/W Function Value MACRX_writepoint 0x01 R Indicate current write page pointer in RX LAN module MACRX_readpoint 0x01 R Indicate current read page pointer in TX host module. 81 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.21 Page 1 Offset 0x0E: TX Memory Pointer Register (TMPR) Bit [7:0] [15:8] Name Default R/W Function Value MACTX_writepoint 0x01 R Indicate current write page pointer in RX host module MACTX_readpoint 0x01 R Indicate current read page pointer in TX LAN module. 6.1.22 Page 1 Offset 0x10: RX Bridge Stuffing Packet Control Register (RXBSPCR) Bit Name [11:0] Reserved [14:12] RXB_SPW [15] RXB_SP Default R/W Function Value 0x000 R Reserved 100 RW RX bridge stuffing packet double word count. Minimum value is 1 and maximum value is 7. Default value is 4. 1 RW Enable the RX bridge stuffing packet function. 1: Enable (Default) 0: Disable 6.1.23 Page 1 Offset 0x12: RX MAC Control Register (RXMCR) Bit Name [7:0] [8] Reserved SBP [9] SM [10] [11] Reserved crcenLAN [12] stp [13] Reserved [15:14] Reserved Default R/W Function Value 0x00 R Reserved 1 RW Stop Backpressure. 1: When TFC bit = 1, setting this bit enables backpressure on TX direction “continuously” during RX buffer full condition in half duplex mode. 0: When TFC bit = 1, setting this bit enable backpressure on TX direction “intermittently” during RX buffer full condition in half duplex mode (default). 0 RW Super Mac support. 1: Enable Super Mac to shorten exponential back-off time during transmission retrying. 0: Disabled (default). 0 RW Reserved 1 RW TX Append CRC Enable. 1: CRC byte is generated and appended by the hardware for every transmitted MAC frame (default). 0: CRC byte is not appended. 0 RW Stop receiving packet process 0 RW Reserved 00 R Reserved 82 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.24 Page 2 Offset 0x02: IO Control Register (ICR) Bit [0] [1] [2] [3] [4] [5] [7:6] [7] [9:8] [10] Name PDSDLO PUSDLO PDSDHI PUSDHI PDSA PUSA IPME IIRQ ISD SDSR [12:11] ICLK [13] [14] [15] IGPIO IEEPROM ILED Default Value 0 0 0 0 0 0 0 0 00 R/W RW RW RW RW RW RW RW RW RW 0 RW 00 RW 00 0 0 RW RW RW Function Pull-Down Data Pad 7-0 Pull-Up Data Pad 7-0 Pull-Down Data Pad 15-8 Pull-Up Data Pad 15-8 Pull-Down SA0-5 Pull-Up SA0-5 PME Output Current 3.3V 2.5V 0 8mA 4.4mA 1 16mA 8.8mA IRQ Output Current 3.3V 2.5V 0 8mA 4.4mA 1 16mA 8.8mA Data Pad Output Current [1:0] 3.3V 2.5V 00 2mA 1.1mA 01 4mA 2.2mA 10 8mA 4.4mA 11 16mA 8.8mA SD0-15 IO pad output slew rate 0: Fast 1: Slow TCLK output current [1:0] 3.3V 2.5V 00 2mA 1.1mA 01 4mA 2.2mA 10 8mA 4.4mA 11 16mA 8.8mA GPIO output current 3.3V 2.5V 0 8mA 4.4mA 1 16mA 8.8mA EEPROM output current 3.3V 2.5V 0 8mA 4.4mA 1 16mA 8.8mA LED output current 3.3V 2.5V 0 8mA 4.4mA 1 16mA 8.8mA 1.8V 2.8mA 5.6mA 1.8V 2.8mA 5.6mA 1.8V 0.7mA 1.4mA 2.8mA 5.6mA 1.8V 0.7mA 1.4mA 2.8mA 5.6mA 1.8V 2.8mA 5.6mA 1.8V 2.8mA 5.6mA 1.8V 2.8mA 5.6mA 83 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.25 Page 2 Offset 0x04: PHY Control Register (PCR) Bit Name [0] Auto_Poll_En [1] Poll_fc [2] Poll_sel [3] [7:4] Reserved Opmode [12:8] Phyid[4:0] [15:13] Reserved Default R/W Function Value 0 RW PHY Auto-Polling Function. Enable If set to one then hardware will auto-polling internal PHY register setting and update Mac Control Register enable, speed, and duplex information. 1: Enable Auto-polling function 0: Disable (Default) 1 RW Enable Auto-polling Flow control function. Auto-polling PHY’s register and update flow control information. If PHY is in full duplex mode then 1: MAC Flow control depend on PHY and PHY’s link partner PHY pause capability 0: MAC disable Flow control If PHY is in half duplex mode then 1: MAC enable Flow control 0: MAC disable Flow control 0 RW Polling function select 1: Auto-polling logic will Check MR0 register (PHY addr. 0x0) status to make decision on MAC’s speed and duplex 0: Auto-polling logic will check MR4 register (PHY address 0x4) status to make decision on MAC’s speed and duplex. (Default) 0 R Reserved 0000 RW PHY Operation mode 0000: Auto-negotiation mode 0001: Auto-negotiation with 100 BASE-TX FDX/HDX ability 0010: Auto-negotiation with 10 BASE-T FDX/HDX ability 0011: Reserved 0100: Manual selection of 100 BASE-TX FDX 0101: Manual selection of 100 BASE-TX HDX 0110: Manual selection of 10 BASE-T FDX 0111: Manual selection of 10 BASE-T HDX 10000 RW Programmable PHY ID Registers. This address is used when multiple PHY are accessed through management interface. If the value is changed, new setting will effective after hardware/software is reset. The default value is 10000. 000 RW Reserved 84 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.26 Page 2 Offset 0x06: PHY Status Register (PHYSR) Bit Name [0] Speed Led [1] Duplex Led [2] Link Led [3] TX Led [4] RX Led [5] COL Led [6] [7] [8] [9] [10] Reserved Reserved Reserved Reserved XtalClkSelect [11] ASICClkSelect [15:12] Reserved Default R/W Function Value 1 R PHY Link Speed Status 0: 100MBps 1: 10MBps 1 R PHY Full Duplex Mode Status 0: Full Duplex Mode 1: Half Duplex Mode 1 R PHY Link Status 0: Link up 1: Link Down 1 R PHY TX activity 0: TX traffic passing 1: No Traffic 1 R PHY RX activity 0: RX traffic passing 1: No Traffic 1 R PHY Collision Status 0: Collision Detect 1: No Collision 1 R Reserved 1 R Reserved 1 R Reserved 0 R Reserved 1 R PHY XTLP/XTLN clock select 1: Use Crystal clock input XTLP/XTLN as PHY clock source 0: Disable 0 R PHY ASIC clock select 1: Select TCLK as PHY clock source 0: Disable 0x0 R Reserved 85 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.27 Page 2 Offset 0x08: MDIO Read/Write Data Register (MDIODR) Bit [15:0] Name Mdio_Data Default R/W Function Value 0x0000 RW MDIO data [15:0] When CPU set MDIO read command register to 1, The MDC/MDIO controller will show the read data from PHY register here. When CPU set MDIO write command register to 1, The MDC/MDIO controller will write this register data to the PHY register. 6.1.28 Page 2 Offset 0x0A: MDIO Read/Write Control Register (MDIOCR) Bit Name [4:0] Reg_addr [7:5] [12:8] Reserved Phy_addr [13] MDIORD_ok [14] MDIORead [15] MDIOWrite Default R/W Function Value 00000 RW PHY Register address. CPU should set this register to let the MDC/MDIO controller knows which PHY register to be accessed. 000 R Reserved 00000 RW PHY Physical ID. The CPU should set this register to let the MDC/MDIO controller know what PHY ID to be accessed. 0 R MDIO data valid After the CPU set the MDIO read command register to one, CPU should continue polling this bit to confirm that the MII management interface read cycle is done and Data [15:0] is also valid. After CPU set the MDIO write command register to one, CPU should continue polling this bit to confirm that the MII management interface write cycle is done. 1: MII management interface read/write cycle is done. 0: MII management interface read/write cycle is not done. 0 WC MDIO Read command to PHY 1: Read command 0: Idle The CPU should set this bit to one to let the MDC/MDIO controller perform MII management interface read cycle. CPU also needs to program the reg_addr and phy_addr value in MDIOCR first. 0 WC MDIO Write command to PHY 1: Write command 0: Idle The CPU should set this bit to one to let the MDC/MDIO controller perform MII management interface write cycle. CPU also needs to set the reg_addr, phy_addr and Data register in MDIOCR first. 86 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.29 Page 2 Offset 0x0C: I_Full/I_Speed LED Control Register 0 (LCR0) Bit Name [7:0] Sel_led0[7:0] [15:8] Sel_led1[7:0] Default R/W Function Value 0x04 RW Select LED pin I_FULL output function [7] Full Duplex/Collision [6] 10Base-T [5] Collision [4] TX/RX activity [3] Link/Act. [2] Full duplex [1] 100Base-TX [0] Enable LED pin (Please reference page 2 offset 0xE [15] setting to select I_FULL LED polarity) 1: enable LED 0: disable LED NOTE: The user can turn on multiple functions at the same time. For example, Sel_led0=0001_0001 then any RX or TX activity will turn on the LED light on LED0 pin. NOTE: I_FULL LED polarity can also set to active high or active low. So when Page 2 0xC [0] enable is off then output value will decide by I_FULL LED polarity setting in Page 2 offset 0x0E bit [15], I_FULL LED output 1 when I_FULL_select is active low and 0 when active high. 0x02 RW Select LED pin I_Speed output function [7] Full Duplex/Collision [6] 10Base-T [5] Collision [4] TX/RX activity [3] Link/Act. [2] Full duplex [1] 100Base-TX [0] Enable LED pin (active low) NOTE: The user can turn on multiple functions at the same time. 87 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.30 Page 2 Offset 0x0E: I_LK/Act LED Control Register 1 (LCR1) Bit Name [7:0] Sel_led2[7:0] [14:8] IPG [15] I_FULL_active Default R/W Function Value 0x08 RW Select LED pin I_LK/Act output function [7] Full Duplex/Collision [6] 10Base-T [5] Collision [4] TX/RX activity [3] Link /Act. [2] Full duplex [1] 100Base-TX [0] Enable LED pin (active low) NOTE: The user can turn on multiple functions at the same time. 0x15 RW Inter Packet Gap for back-to-back transfer on TX direction in MII mode (default = 15h). 0 RW I_FULL LED active select 0: active low if the I_FULL of bus type setting is pulled up 1: active high if the I_FULL of bus type setting is pulled down Please refer to TAB-1 for bus type setting. 6.1.31 Page 2 Offset 0x10: IPG Control Register (IPGCR) Bit [6:0] [7] [14:8] [15] Name IPG1 Reserved IPG2 Reserved Default Value 0x0C 0 0x12 0 R/W RW R RW R Function IPG part1 value (default = 0Ch). Reserved IPG part1 value + part2 value (default = 12h). Reserved 6.1.32 Page 2 Offset 0x12: Chip Revision ID Register (CRIR) Bit [3:0] [15:4] Name Chip_rev_ID Reserved Default R/W Value 0000 RW Chip Revision ID 0x000 RW Reserved Function 88 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.33 Page 2 Offset 0x14: Flow Control High/Low Watermark Control Register (FLHWCR) Bit Name [6:0] FCHW [7] [14:8] Reserved FCLW [15] Reserved Default R/W Function Value 0x24 RW Flow Control High-water mark [7:0]: RX free page count high water level, once internal RX free page counter lower than this threshold and Flow control is enabled, then TX MAC will send Pause ON Frame out to informal remote PHY stop transmit packets. 0 R Reserved 0x42 RW Flow Control Low-water mark [7:0]: When Flow control is enabled and pause is ON, RX free page counter if higher than this low water mark value then TX MAC will send pause OFF frame to inform remote PHY back to normal state and re-start transmit packets. 0 R Reserved 6.1.34 Page 2 Offset 0x16: RX Control Register (RXCR) Bit Name [0] PRO [1] AMALL [2] SEP [3] AB [4] AM [5] AP [6] ARP [7] [15:8] Reserved Reserved Default R/W Function Value 1 RW PACKET_TYPE_PROMISCUOUS. 1: All frames received by the ASIC are forwarded up toward the host. 0: Disabled 0 RW PACKET_TYPE_ALL_MULTICAST. 1: All multicast frames received by the ASIC are forwarded up toward the host, not just the frames whose scrambling result of DA matching with multicast address list provided in Multicast Filter Array Register. 0: Disabled. This only allows multicast frames whose scrambling result of DA field matching with multicast address list provided in Multicast Filter Array Register to be forwarded up toward the host (Default). 0 RW Accept Error Packet. 1: Accept save Error Packet. 0: Disabled, Reject Error Packet. (Default) 0 RW PACKET_TYPE_BROADCAST. 1: All broadcast frames received by the MAC are forwarded to the host interface. 0: Disabled. (Default) 0 RW PACKET_TYPE_MULTICAST. 1: All multicast frames who’s scrambling result of DA matching with multicast address list are forwarded to the host interface. (Please reference to section 4.1.2) 0: Disabled. (Default) 0 RW Accept Physical Address from Multicast Filter Array. 1: Allow unicast packets to be forwarded up toward host if the lookup of scrambling result of DA is found within multicast address list. 0: Disabled, that is, unicast packets filtering are done without regarding multicast address list (Default). 0 RW Accept Runt Packet. 1: Accept Runt Packet. 0: Disabled, Reject the runt packet (byte count less then 64 bytes) (Default). 0 RW Reserved 0x00 R Reserved 89 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.35 Page 2 Offset 0x18: Jam Limit Count Register (JLCR) Bit Name [5:0] Jam[5:0] [6] [7] Reserved cpteff [8] LDRND [15:9] Reserved Default R/W Function Value 0x3F RW Jam_Limit[5:0]: This is used for flow-control in half-duplex mode, which is based on force collision mechanisms to backpressure transmitting network node. During the force collision backpressure process, the Ethernet MAC will continue counting total collision count. When it has reached the Jam_Limit setting, the Ethernet MAC will stop backpressure to avoid Ethernet HUB from being partitioned (default = 3Fh) due to excessive collision on network link. 0 RW Reserved 0 RW Capture Effective Mode. 1: Enable capture effective mode. 0: Disabled. 0 RW LDRND: To load Random number into MAC’s exponential back-off timer, the user writes a “1” to enable the ASIC to load a small random number into MAC’s back-off timer to shorten the back-off duration in each retry after collision. This register is used for test purpose. Default value = 0. 0x02 R Reserved 6.1.36 Page 2 Offset 0x1C: Max Packet Length Register (MPLR) Bit [11:0] Name MPL [15:12] Reserved Default R/W Function Value 0x600 RW Maximum packet Length [11:0] Programmable maximum packet size allowed to be received range from 64 to 2047.Default value is 1522. 0x0 R Reserved 90 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.37 Page 3 Offset 0x02: MAC Address Setup Register 0 (MACASR0) Bit Name [7:0] MAC [47:40] [15:8] MAC [39:32] Default R/W Function Value 0x00 RW Default MAC address for host port. MAC address [47:40] 0x00 RW MAC address [39:32] 6.1.38 Page 3 Offset 0x04: MAC Address Setup Register 1 (MACASR1) Bit Name [7:0] MAC [31:24] [15:8] MAC [23:16] Default R/W Function Value 0x00 RW Default MAC address for host port. MAC address [31:24] 0x00 RW MAC address [23:16] 6.1.39 Page 3 Offset 0x06: MAC Address Setup Register 2 (MACASR2) Bit Name [7:0] MAC [15:8] [15:8] MAC [7:0] MACASR2[15:8] MACASR2[7:0] MACASR1[15:8] MACASR1[7:0] MACASR0[15:8] MACASR0[7:0] D7 DA7 DA15 DA23 DA31 DA39 DA47 Default R/W Function Value 0x00 RW Default MAC address for host port MAC address [15:8] 0x00 RW MAC address [7:0] D6 DA6 DA14 DA22 DA30 DA38 DA46 D5 DA5 DA13 DA21 DA29 DA37 DA45 D4 DA4 DA12 DA20 DA28 DA36 DA44 D3 DA3 DA11 DA19 DA27 DA35 DA43 D2 DA2 DA10 DA18 DA26 DA34 DA42 D1 DA1 DA9 DA17 DA25 DA33 DA41 D0 DA0 DA8 DA16 DA24 DA32 DA40 Note: The bit sequence of the received MAC address is DA0, DA1, … DA46, DA47 …. 91 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.40 Page 3 Offset 0x08: Multicast Filter Array Register (MFAR01) Bit [7:0] [15:8] Name MA0 [7:0] MA1 [7:0] Default R/W Value 0x00 RW Multicast Filter Array0 [7:0] 0x00 RW Multicast Filter Array1 [7:0] Function 6.1.41 Page 3 Offset 0x0A: Multicast Filter Array Register (MFAR23) Bit [7:0] [15:8] Name MA2 [7:0] MA3 [7:0] Default R/W Value 0x00 RW Multicast Filter Array2 [7:0] 0x00 RW Multicast Filter Array3 [7:0] Function 6.1.42 Page 3 Offset 0x0C: Multicast Filter Array Register (MFAR45) Bit [7:0] [15:8] Name MA4 [7:0] MA5 [7:0] Default R/W Value 0x00 RW Multicast Filter Array4 [7:0] 0x00 RW Multicast Filter Array5 [7:0] Function 6.1.43 Page 3 Offset 0x0E: Multicast Filter Array Register (MFAR67) Bit [7:0] [15:8] Name MA6 [7:0] MA7 [7:0] Default R/W Value 0x00 RW Multicast Filter Array6 [7:0] 0x00 RW Multicast Filter Array7 [7:0] Function 6.1.44 Page 3 Offset 0x10: VLAN ID0 Filter Register (VID0FR) Bit Name [11:0] VID0 [11:0] [13:12] Reserved [14] VFE Default Value 0x000 00 0 [15] 0 VSO R/W Function RW VLAN ID0 Filter Register R Reserved RW VLAN filter enable 1: Enable VLAN filter. The VLAN ID field (12 bits) received 802.1q tagged packets, which will be used to compare with VID1 and VID2 setting. If it matches either VID1 or VID2, or its value is equal to all zeros, the received 802.1q tagged packets will be forwarded to the Host. 0: Disable VLAN filter. The received packets with or without 802.1q Tag bytes will always be forwarded to the Host (default). RW VLAN Strip off. The VSO bit determines whether the VLAN Tag bytes (4 bytes) are stripped off or not during forwarding to the Host. 1: Strip off VLAN Tag (4 bytes) from the incoming packet. 0: Preserve VLAN Tag in the incoming packet (default). 92 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.45 Page 3 Offset 0x12: VLAN ID1 Filter Register (VID1FR) Bit Name [11:0] VID1 [11:0] [15:12] Reserved Default R/W Value 00 RW VLAN ID1 Filter Register 0x0 R Reserved Function 6.1.46 Page 3 Offset 0x14: EEPROM Checksum Register (EECSR) Bit [7:0] [15:8] Name Default R/W Function Value EEChecksum [7:0] 0x00 R EEPROM hardware calculated Checksum value over the valid address space. If this value plus the EEPROM 0x27 checksum data equal to 0xFF then the checksum value check is passed. Reserved 0x00 R Reserved 6.1.47 Page 3 Offset 0x16: EEPROM Data Register (EEDR) Bit [15:0] Name Default R/W Value EEPromdata [10:0] 0xffff RW EEPROM Data Register Function 6.1.48 Page 3 Offset 0x18: EEPROM Control Register (EECR) Bit Name [7:0] [11:8] EepromAddr [7:0] EE_command [12] [13] Reserve EE_READY [14] EE_reload [15] EE_Reset Default R/W Function Value 0x00 RW EEPROM Address Register 0x00 RW 0x0 EEPROM Idle 0x1 Read EEPROM 0x2 Write EEPROM 0x4 Disable EEPROM Write 0x8 Enable EEPROM Write 0 R Reserved 1 RW EEPROM Ready 1: EEPROM Ready, Indicate EEPROM ready to execute command 0: EEPROM not ready 0 RW EEPROM Auto Reload 1: EEPROM re-load function 0: Normal (Default) 0 RW EEPROM module reset 1:Reset EEPROM Control 0:Idel (Default) 93 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.49 Page 3 Offset 0x1A: Test Packet Configuration Register (TPCR) Bit [7:0] [13:8] [14] [15] Name TPPattern[7:0] TPInterval[5:0] TPRandom TPFix Default Value 0x00 0x15 0 0 R/W RW RW RW RW Function Data pattern or random seed Test Packet inter-frame gape Test Packet with Random pattern Test Packet with fix pattern The transmit test packets without padding CRC 4 bytes. 6.1.50 Page 3 Offset 0x1C: Test Packet Length Register (TPLR) Bit Name [11:0] TPLength [15:12] Reserved Default R/W Function Value 0x48 RW Set Test Packet Length [11:0] 0x0 R Reserved 6.1.51 Page 4 Offset 0x02: GPIO Enable Register (GPIOER) Bit Name [3:0] GPIO_En [7:4] GPIO_In [11:8] GPIO_Out [15:12] GPIO_OE Default R/W Function Value 0x0 RW GPIO3~GPIO0 Enable Register Enable GPIO function when set to one. 1: Enable 0: Disable 0x0 RW GPIO3~GPIO0 Input Data Register. Store the input data when GPIO output enable is not turned on. 0x0 RW GPIO3~GPIO0 Output Data Register. The output data register will load to the GPIO pin when output enable is set to one. 0x0 RW GPIO3~GPIO0 Output Enable Register. If set to one then GPIO pin is used as output pin. Otherwise, the GPIO is an input pin. 1: Output Enable 0: Disable 94 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.52 Page 4 Offset 0x04: GPIO IRQ Control Register (GPIOCR) Bit Name [3:0] GPIO_IntEn [7:4] GPIO_Int_HL [11:8] GPIO_Int_Status [15:12] GPIO_Int_Mask Default R/W Function Value 0x0 RW GPIO3~GPIO0 Interrupt Enable Register. Enable GPIO interrupt function when set to one. 1: GPIO Interrupt Enable 0: Disable 0x0 RW GPIO3~GPIO0 Interrupt Polarity Select Register Active high if set to one and Active low if set to zero. 1: Active high interrupt 0: Active low interrupt (Default) 0x0 WC GPIO3~GPIO0 Interrupt Status Register Write one to clear interrupt status bit. 0xf RW GPIO3~GPIO0 Interrupt Mask Register Mask Interrupt output when set to one. 1: Interrupt Mask Enable 0: Mask disable 6.1.53 Page 4 Offset 0x06: GPIO Wakeup Control Register (GPIOWCR) Bit Name Default R/W Function Value [1:0] GPIO_Wakeup_En[ 0x00 RW GPIO1~GPIO0 Wakeup Enable Register 1:0] When set to one will enable GPIO Wakeup Function 1: Enable GPIO Wakeup function 0: Disable [3:2] Reserved 00 R Reserved [7:4] GPIO_Wakeup_Sel 0000 RW GPIO1~GPIO0 Wakeup Select Register [3:0] GPIO_Wakeup_Sel[1:0]:GPIO0 Wakeup Select 00: Falling edge 01: Rising edge 10: Level low 11: Level high GPIO_Wakeup_Sel[3:2]:GPIO1 Wakeup Select 00: Falling edge 01: Rising edge 10: Level low 11: Level high [8] GPIO1 0 RW GPIO1 pin selection 1: GPIO1 on AEN pin if GPIOER [1] is set to 1 (GPIO1 enable) 0: GPIO1 on EEDIO pin if GPIOER [1] is set to 1 (GPIO1 enable) [10:9] GPIO23 00 RW GPIO2 and GPIO3 output pin selection Please select correct GPIO2/GPIO3 pins location based on hardware design circuit and also make sure GPIOER [2] or GPIOER [3] is enabled. GPIO2 GPIO3 00 EECK EECS 01 SD14 SD15 10 SD6 SD7 11 N/A N/A [11] Reserved 0 R Reserved [13:12] GPIO_Wakeup_Sta 00 R GPIO1 ~GPIO0 Wakeup Status Register tus[1:0] 1: Wakeup State 0: Normal State [15:14] Reserved 00 R Reserved 95 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.54 Page 4 Offset 0x0A: SPI Configuration Register (SPICR) Bit Name Default R/W Function Value [0] SPI_r_compression 0 RW SPI Register compression 1: Enable 0: Disable [1] SPI_q_compression 0 RW SPI RX/TX Queue Compression 1: Enable 0: Disable [2] Reserved 0 RW Reserved [3] RBRE 0 RW Register Burst Read Enable. 1: It indicates SPI register access at Burst read mode. 0. It indicates SPI register access at Single read mode. [4] R Power management mode. PMM 0 1: It indicates chip at PMM status (no core clock). 0: It indicates chip at normal operation mode. [5] Reserved 0 RW Reserved [6:7] Reserved 00 R Reserved [8] Loopback 0 RW SPI loopback mode enable 1: Enable 0: Disable [9] Reserved 0 R Reserved [10] SPICoreCLK Reset 1 WC Reset SPI core clock domain related logic [11] SPI SPICLK Reset 1 WC Reset SPI SPI Clock domain related logic [15:12] Reserved 0x000 R Reserved 96 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.55 Page 4 Offset 0x0C: SPI Interrupt Status and Mask Register (SPIISMR) Bit Name [0] NWA_P_Int [1] UDC_P_Int [2] NBA_P_Int [3] [4] [5] [6] [7] Reserved Reserved Reserved Reserved Reserved Mask NWA_P Int [8] Mask UDC_P Int [9] Mask NBA_P Int [10] [11] [12] [13] [14] [15] Reserved Reserved Reserved Reserved Reserved Default R/W Function Value 0 R/WC Non-Word Access Interrupt for primary SPI: If the data transfer for RXQ/TXQ is Non-word (for example odd bytes), this bit will be asserted. 1: Data access RXQ/TXQ end at odd byte. 0: Data access RXQ/TXQ end at words. 0 R/WC Un-Define Command Interrupt for primary SPI: After Slave received un-define command, SPI slave will arise this bit. 1: SPI slave receive un-define command. 0: SPI receive correct command. If SPI slave receive un-define command, it will ignore all TX data in this access. 0 R/WC Non-Byte Access Interrput for primary SPI:If the data transfer is Non-byte (for example 1~7 bits), this bit will be asserted. 1: Data access with non-byte edge. 0: Data access with byte edge. 0 R/WC Reserved. 0 R/WC Reserved 0 R/WC Reserved 0 R/WC Reserved 0 R/WC Reserved 1 R/W Primary “Non-Word Access” interrupt Mask bit for primary SPI. 1: Mask Primary Non-word access interrupt. 0: Allow Primary Non-word access interrupt. 1 R/W Primary “Un-Define Command” interrupt Mask bit for primary SPI. 1:Mask Primary un-define commands interrupt. 0: Allow Primary un-define commands interrupt. 1 R/W Primary “Non-Byte Access” interrupt Mask bit for primary SPI. 1: Mask Primary Non-byte access interrupt. 0: Allow Primary Non-byte access interrupt. 1 R/W Reserved 1 R/W Reserved 1 R/W Reserved 1 R/W Reserved 1 R/W Reserved 97 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.56 Page 4 Offset 0x12: COE RX Control Register 0(COERCR0) Bit Name [0] RXIPCE [1] RXIPVE [2] RXV6PE [3] RXTCPE [4] RXUDPE [5] RXICMP [6] RXIGMP [7] RXICV6 [8] RXTCPV6 [9] RXUDPV6 [10] RXICMV6 [11] RXIGMV6 [12] RXICV6V6 [14:13] Reserved [15] FOPC Default R/W Function Value 0 RW Enable Ipv4 checksum check. 1: Enables IP packet checksum check. 0: Disable IP packet checksum check 0 RW Enable IP version check. 1: Enables IP packet version field check. 0: Disables IP packet version field check. 0 RW Enable Ipv6 header parsing function. 1: Enables Ipv6 supporting. 0: Disable Ipv6 supporting. 0 RW Enable TCP packet checksum check in RX path. 1: Enables the TCP packet checksum check function. 0: Disables the TCP packet checksum check function. 0 RW Enable UDP packet checksum check in RX path. 1: Enables the UDP packet checksum check function. 0: Disables the UDP packet checksum check function. 0 RW Enable ICMP packet checksum check in RX path. 1: Enables the ICMP packet checksum check function. 0: Disables the ICMP packet checksum check function. 0 RW Enable IGMP packet checksum check in RX path. 1: Enables the IGMP packet checksum check function. 0: Disables the IGMP packet checksum check function. 0 RW Enable ICMPv6 packet checksum check in RX path. 1: Enables the ICMPv6 packet checksum check function. 0: Disables the ICMPv6 packet checksum check function. 0 RW Enable TCP packet checksum check in RX path for Ipv6 packet. 1: Enables the TCP packet checksum check function for Ipv6 packet. 0: Disables the TCP packet checksum check function for Ipv6 packet. 0 RW Enable UDP packet checksum check in RX path for Ipv6 packet. 1: Enables the UDP packet checksum check function for Ipv6 packet. 0: Disables the UDP packet checksum check function for Ipv6 packet. 0 RW Enable ICMP packet checksum check in RX path for Ipv6 packet. 1: Enables the ICMP packet checksum check function for Ipv6 packet. 0: Disables the ICMP packet checksum check function for Ipv6 packet. 0 RW Enable IGMP packet checksum check in RX path for Ipv6 packet. 1: Enables the IGMP packet checksum check function for Ipv6 packet. 0: Disables the IGMP packet checksum check function for Ipv6 packet. 0 RW Enable ICMPv6 packet checksum check in RX path for Ipv6 packet. 1: Enables the ICMPv6 packet checksum check function for Ipv6 packet. 0: Disables the ICMPv6 packet checksum check function for Ipv6 packet. 00 RW Reserved 0 RW Enable Fixed Offset Partial Checksum mode. 1: Enable Fixed Offset Partial Checksum mode. If enabled this bit, COE RX part will calculate partial checksum from fixed offset 14 (bytes) to the end of packet (CRC is NOT included). Other bits should be disabled when FOPC turned ON. 0: Disable FOPC mode 98 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.57 Page 4 Offset 0x14: COE RX Control Register 1(COERCR1) Bit Name [0] IPCEDP [1] IPVEDP [2] V6VEDP [3] TCPEDP [4] UDPEDP [5] ICMPDP [6] IGMPDP [7] ICV6DP [8] RX64TE [9] RXPPPE [10] TCP6DP [11] UDP6DP [12] IC6DP [13] IG6DP [14] ICV66DP Default R/W Function Value 0 RW Drop received packet with IP checksum error. 1: Drop received IP packets with IP checksum error. 0: Do not drop received IP packets with IP checksum error, but indicate checksum error in RX header. 0 RW Drop received packet with IP version error. 1: Drop received IP packets with IP version error. 0: Do not drop received IP packets with IP version error, but indicate version error in RX header. 0 RW Drop received packet with Ipv6 version error. 1: Drop received Ipv6 packets with Ipv6 version error. 0: Do not drop received Ipv6 packets with Ipv6 version error, but indicate version error in RX header. 0 RW Drop received packet with TCP checksum error. 1: Drop received TCP packets with TCP checksum error. 0: Do not drop received TCP packets with TCP checksum error, but indicate checksum error in RX header. 0 RW Drop received packet with UDP checksum error. 1: Drop received UDP packets with UDP checksum error. 0: Do not drop received UDP packets with UDP checksum error, but indicate checksum error in RX header. 0 RW Drop received packet with ICMP checksum error. 1: Drop received ICMP packets with ICMP checksum error. 0: Do not drop received ICMP packets with ICMP checksum error, but indicate checksum error in RX header. 0 RW Drop received packet with IGMP checksum error. 1: Drop received IGMP packets with IGMP checksum error. 0: Do not drop received IGMP packets with IGMP checksum error, but indicate checksum error in RX header. 0 RW Drop received packet with ICMPv6 checksum error. 1: Drop received ICMPv6 packets with ICMPv6 checksum error. 0: Do not drop received ICMPv6 packets with ICMPv6 checksum error, but indicate checksum error in RX header. 0 RW Support Ipv6 in Ipv4 tunnel mode. 0: COE will not check L4 checksum in a Ipv6 in Ipv4 tunnel packet. 1: COE will check L4 checksum in a Ipv6 in Ipv4 tunnel packet. 0 RW L2 parser support PPPoE encapsulated packet in RX path. 1: COE support PPPoE encapsulated packet in RX path. 0: COE do not support PPPoE encapsulated packet in RX path. 0 RW Drop received packet with TCP checksum error for Ipv6 packet. 1: Drop received TCP packets with TCP checksum error for Ipv6 packet. 0: Do not drop received TCP packets with TCP checksum error, but indicate checksum error in RX header for Ipv6 packet. 0 RW Drop received packet with UDP checksum error for Ipv6 packet. 1: Drop received UDP packets with UDCP checksum error for Ipv6 packet. 0: Do not drop received UDP packets with UDP checksum error, but indicate checksum error in RX header for Ipv6 packet. 0 RW Drop received packet with ICMP checksum error for Ipv6 packet. 1: Drop received ICMP packets with ICMP checksum error for Ipv6 packet. 0: Do not drop received ICMP packets with ICMP checksum error, but indicate checksum error in RX header for Ipv6 packet. 0 RW Drop received packet with IGMP checksum error for Ipv6 packet. 1: Drop received IGMP packets with IGMP checksum error for Ipv6 packet. 0: Do not drop received IGMP packets with IGMP checksum error, but indicate checksum error in RX header for Ipv6 packet. 0 RW Drop received packet with ICMPv6 checksum error for Ipv6 packet. 1: Drop received ICMPv6P packets with ICMPv6 checksum error for Ipv6 packet. 0: Do not drop received ICMPv6 packets with ICMPv6 99 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller checksum error, but indicate checksum error in RX header for Ipv6 packet. [15] Reserved 0 RW Reserved 6.1.58 Page 4 Offset 0x16: COE TX Control Register 0(COETCR0) Bit Name [0] TXIP [1] TXTCP [2] TXUDP [3] TXICMP [4] TXIGMP [5] TXICV6 [7:6] [8] Reserved TXTCPV6 [9] TXUDPv6 [10] TXICMV6 [11] TXIGMV6 [12] TXICV6V6 [15:13] Reserved Default R/W Function Value 0 RW Enable Ipv4 checksum insertion function. 1: Enables Ipv4 packet checksum insertion function. 0: Disables Ipv4 packet checksum insertion function. 0 RW Enable TCP checksum insertion function. 1: Enables TCP packet checksum insertion function. 0: Disables TCP packet checksum insertion function. 0 RW Enable UDP checksum insertion function. 1: Enables UDP packet checksum insertion function. 0: Disables UDP packet checksum insertion function. 0 RW Enable ICMP checksum insertion function. 1: Enables ICMP packet checksum insertion function. 0: Disables ICMP packet checksum insertion function. 0 RW Enable IGMP checksum insertion function. 1: Enables IGMP packet checksum insertion function. 0: Disables IGMP packet checksum insertion function. 0 RW Enable ICMPv6 checksum insertion function. 1: Enables ICMPv6 packet checksum insertion function. 0: Disables ICMPv6 packet checksum insertion function. 0 RW Reserved 0 RW Enable TCP checksum insertion function for Ipv6 packet. 1: Enables TCP packet checksum insertion function for Ipv6 packet. 0: Disables TCP packet checksum insertion function for Ipv6 packet. 0 RW Enable UDP checksum insertion function for Ipv6 packet. 1: Enables UDP packet checksum insertion function for Ipv6 packet. 0: Disables UDP packet checksum insertion function for Ipv6 packet. 0 RW Enable ICMP checksum insertion function for Ipv6 packet. 1: Enables ICMP packet checksum insertion function for Ipv6 packet. 0: Disables ICMP packet checksum insertion function for Ipv6 packet. 0 RW Enable IGMP checksum insertion function for Ipv6 packet. 1: Enables IGMP packet checksum insertion function for Ipv6 packet. 0: Disables IGMP packet checksum insertion function for Ipv6 packet. 0 RW Enable ICMPv6 checksum insertion function for Ipv6 packet. 1: Enables ICMPv6 packet checksum insertion function for Ipv6 packet. 0: Disables ICMPv6 packet checksum insertion function for Ipv6 packet. 000 RW Reserved 100 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.59 Page 4 Offset 0x18: COE TX Control Register 1(COETCR1) Bit Name [0] TX64TE [1] TXPPPE [15:2] Reserved Default R/W Function Value 0 RW Support Ipv6 in Ipv4 tunnel mode. 0: COE will not insert L4 checksum in a Ipv6 in Ipv4 tunnel packet. 1: COE will insert L4 checksum in a Ipv6 in Ipv4 tunnel packet. 0 RW L2 parser support PPPoE encapsulated packet in TX path. 0: COE support PPPoE encapsulated packet in TX path. 0: COE do not support PPPoE encapsulated packet in TX path. 0 RW Reserved 6.1.60 Page 5 Offset 0x02: Wakeup Frame Timer Register (WFTR) Bit Name [3:0] WKTimer[3:0] [15:4] Reserved Default R/W Function Value 00 RW Mask Wakeup Timer: Mask wakeup event trigger to host timer.(Due to some system took a long time to enter suspend state) NOTE: Make sure change the setting to 0xC or oxD when the AX88796C is in the wakeup mode and power saving function is turn on this will help when the chip change the speed to reduce the power consumption when unplug the cable. [3:0] Delay TimeUnit 0000 0 ms 0001 2 ms 0010 4 ms 0011 8 ms 0100 16 ms 0101 32 ms 0110 64 ms 0111 128 ms 1000 256 ms 1001 512 ms 1010 1024 ms 1011 2048 ms 1100 4096 ms 1101 8192 ms 1110 16384 ms 1111 32768 ms 0x000 RW Reserved 101 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.61 Page 5 Offset 0x04: Wakeup Frame Cascade Command Register (WFCCR) Bit Name [6:0] WFCSCD [7] [8] Reserved DA Match [9] MC Match [15:10] Reserved Default R/W Function Value 00 RW Byte Mask Cascade Command for wake-up frame filter Bit-0: cascade wake-up filter 1 and 0 Bit-1: cascade wake-up filter 2 and 1 Bit-2: cascade wake-up filter 3 and 2 Bit-3: cascade wake-up filter 4 and 3 Bit-4: cascade wake-up filter 5 and 4 Bit-5: cascade wake-up filter 6 and 5 Bit-6: cascade wake-up filter 7 and 6 Note: (1) If both Bit 0 and Bit 1 set ‘1’, Byte Mask 2 and Byte Mask 1 and Byte Mask 0 are cascaded to become one wake-up frame filter that allows defining up to 96 masked bytes. (2) If both Bit 1 and Bit 2 set ‘1’, Byte Mask 3 and Byte Mask 2 and Byte Mask 1 are cascaded to become one wake-up frame filter that allows defining up to 96 masked bytes. (3) If Bit 3 ~ Bit 0 set ‘1’, Byte Mask 3 ~Byte Mask 0 are cascaded to become one wake-up frame filter that allows defining up to 128 masked bytes. (4) If Bit 6 ~ Bit 0 set ‘1’, Byte Mask 7 ~Byte Mask 0 are cascaded to become one wake-up frame filter that allows defining up to 256 masked bytes maximum. 0 RW Reserved 0 RW 1: DA match only enable. When receiving frame has DA matching Node ID register, then the packet is considered as valid wakeup frame. 0: DA match only disable. 0 RW 1: Multicast address match only enable. When receiving frame is a multicast frame and meets Multicast Filter Array, the packet is considered as valid wakeup frame. 0: Multicast address match only disable. 00 RW Reserved 102 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.62 Page 5 Offset 0x06: Wakeup Frame Command 0 ~ 3 Register (WFCR03) Bit [3:0] Name WFCMD0 Default R/W Function Value 0x0 RW Byte Mask Command for wake-up frame filter 0. Host continue write 4 times to completed 32-bits of Byte Mask Command of 3, 2, 1, 0 filter and Mask cascade commend. Bit0: wake-up frame filter enable 1: Enable. 0: Disable. Bit1: destination match enable 1: The DA field of received packet will be compared with the MAC address of AX88796C. When receiving frame with DA matching Node ID register and the wakeup frame filter is also matched, then the packet is considered as valid wakeup frame. 0: When receiving frame with any DA value and the wakeup frame filter is matched, then the packet is considered as valid wakeup frame. Bit2: Multicast match enable [7:4] WFCMD1 [11:8] WFCMD2 [15:12] WFCMD3 0x0 0x0 0x0 1: The DA field of received packet will be examined if it is a multicast frame and compared with the Multicast Filter Array. When receiving frame is a multicast frame, meets Multicast Filter Array, and also matches the wakeup frame filter, the packet is considered as valid wakeup frame. 0: When receiving frame with any DA value matches the wakeup frame filter, the packet is considered as valid wakeup frame. Bit3: Microsoft Windows 7 ARP and NS offload function enable 1:Enable Microsoft Windows 7 ARP and NS offload function function 0:disable Microsoft Windows 7 ARP and NS offload function function RW Byte Mask Command for wake-up frame filter 1. RW Byte Mask Command for wake-up frame filter 2. RW Byte Mask Command for wake-up frame filter 3. 103 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.63 Page 5 Offset 0x08: Wakeup Frame Command 4 ~ 7 Register (WFCR47) Bit [3:0] Name WFCMD4 Default R/W Function Value 0x0 RW Byte Mask Command for wake-up frame filter 0. Host continue write 4 times to completed 32-bits of Byte Mask Command of 7, 6, 5, 4 filter and Mask cascade commend. Bit0: wake-up frame filter enable Bit1: destination match enable Bit2: Multicast match enable [7:4] [11:8] [15:12] WFCMD5 WFCMD6 WFCMD7 0x0 0x0 0x0 Bit3: Microsoft Windows 7 ARP and NS offload function enable 1:Enable Microsoft Windows 7 ARP and NS offload function function 0:disable Microsoft Windows 7 ARP and NS offload function function RW Byte Mask Command for wake-up frame filter 5. RW Byte Mask Command for wake-up frame filter 6. RW Byte Mask Command for wake-up frame filter 7. 6.1.64 Page 5 Offset 0x0A: Wakeup Frame 0 Byte Mask [15:0] Register (WF0BMR0) Bit [15:0] Name WFBM0 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 0 [15:0] 6.1.65 Page 5 Offset 0x0C: Wakeup Frame 0 Byte Mask [31:16] Register (WF0BMR1) Bit [15:0] Name Default R/W Function Value WFBM0 [31:16] 0x0000 RW Byte mask for wake-up frame filter 0 [31:16] 6.1.66 Page 5 Offset 0x0E: Wakeup Frame 0 CRC Register (WF0CR) Bit [15:0] Name WFCRC0 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 0. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 104 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.67 Page 5 Offset 0x10: Wakeup Frame 0 Offset Byte Register (WF0OBR) Bit Name [7:0] WFOB0 [15:8] WFLB0 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 0. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 0. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.68 Page 5 Offset 0x12: Wakeup Frame 1 Byte Mask [15:0] Register (WF1BMR0) Bit [15:0] Name WFBM1 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 1 [15:0] 6.1.69 Page 5 Offset 0x14: Wakeup Frame 1 Byte Mask [31:16] Register (WF1BMR1) Bit [15:0] Name Default R/W Function Value WFBM1 [31:16] 0x0000 RW Byte mask for wake-up frame filter 1 [31:16] 6.1.70 Page 5 Offset 0x16: Wakeup Frame 1 CRC Register (WF1CR) Bit [15:0] Name WFCRC1 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 1. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 105 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.71 Page 5 Offset 0x18: Wakeup Frame 1 Offset Byte Register (WF1OBR) Bit Name [7:0] WFOB1 [15:8] WFLB1 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 1. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 1. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.72 Page 5 Offset 0x1A: Wakeup Frame 2 Byte Mask [15:0] Register (WF2BMR0) Bit [15:0] Name WFBM2 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 2 [15:0] 6.1.73 Page 5 Offset 0x1C: Wakeup Frame 2 Byte Mask [31:16] Register (WF2BMR1) Bit [15:0] Name Default R/W Function Value WFBM2 [31:16] 0x0000 RW Byte mask for wake-up frame filter 2 [31:16] 6.1.74 Page 6 Offset 0x02: Wakeup Frame 2 CRC Register (WF2CR) Bit [15:0] Name WFCRC2 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 2. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 106 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.75 Page 6 Offset 0x04: Wakeup Frame 2 Offset Byte Register (WF2OBR) Bit Name [7:0] WFOB2 [15:8] WFLB2 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 2. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 2. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.76 Page 6 Offset 0x06: Wakeup Frame 3 Byte Mask [15:0] Register (WF3BMR0) Bit [15:0] Name WFBM3 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 3 [15:0] 6.1.77 Page 6 Offset 0x08: Wakeup Frame 3 Byte Mask [31:16] Register (WF3BMR1) Bit [15:0] Name Default R/W Value WFBM3 [31:16] 0x0000 Function RW Byte mask for wake-up frame filter 3 [31:16] 6.1.78 Page 6 Offset 0x0A: Wakeup Frame 3 CRC Register (WF3CR) Bit [15:0] Name WFCRC3 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 3. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 107 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.79 Page 6 Offset 0x0C: Wakeup Frame 3 Offset Byte Register (WF3OBR) Bit Name [7:0] WFOB3 [15:8] WFLB3 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 3. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 3. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.80 Page 6 Offset 0x0E: Wakeup Frame 4 Byte Mask [15:0] Register (WF4BMR0) Bit [15:0] Name WFBM4 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 4 [15:0] 6.1.81 Page 6 Offset 0x10: Wakeup Frame 4 Byte Mask [31:16] Register (WF4BMR1) Bit [15:0] Name Default R/W Function Value WFBM4 [31:16] 0x0000 RW Byte mask for wake-up frame filter 4 [31:16] 6.1.82 Page 6 Offset 0x12: Wakeup Frame 4 CRC Register (WF4CR) Bit [15:0] Name WFCRC4 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 4. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 108 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.83 Page 6 Offset 0x14: Wakeup Frame 4 Offset Byte Register (WF4OBR) Bit Name [7:0] WFOB4 [15:8] WFLB4 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 4. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 4. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.84 Page 6 Offset 0x16: Wakeup Frame 5 Byte Mask [15:0] Register (WF5BMR0) Bit [15:0] Name WFBM5 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 5 [15:0] 6.1.85 Page 6 Offset 0x18: Wakeup Frame 5 Byte Mask [31:16] Register (WF5BMR1) Bit [15:0] Name Default R/W Function Value WFBM5 [31:16] 0x0000 RW Byte mask for wake-up frame filter 5 [31:16] 6.1.86 Page 6 Offset 0x1A: Wakeup Frame 5 CRC Register (WF5CR) Bit [15:0] Name WFCRC5 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 5. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 109 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.87 Page 6 Offset 0x1C: Wakeup Frame 5 Offset Byte Register (WF5OBR) Bit Name [7:0] WFOB5 [15:8] WFLB5 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 5. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 5. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.88 Page 7 Offset 0x02: Wakeup Frame 6 Byte Mask [15:0] Register (WF6BMR0) Bit [15:0] Name WFBM6 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 6 [15:0] 6.1.89 Page 7 Offset 0x04: Wakeup Frame 6 Byte Mask [31:16] Register (WF6BMR1) Bit [15:0] Name Default R/W Function Value WFBM6 [31:16] 0x0000 RW Byte mask for wake-up frame filter 6 [31:16] 6.1.90 Page 7 Offset 0x06: Wakeup Frame 6 CRC Register (WF6CR) Bit [15:0] Name WFCRC6 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 6. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 110 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.91 Page 7 Offset 0x08: Wakeup Frame 6 Offset Byte Register (WF6OBR) Bit Name [7:0] WFOB6 [15:8] WFLB6 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 6. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 6. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.92 Page 7 Offset 0x0A: Wakeup Frame 7 Byte Mask [15:0] Register (WF7BMR0) Bit [15:0] Name WFBM7 [15:0] Default R/W Function Value 0x0000 RW Byte mask for wake-up frame filter 7 [15:0] 6.1.93 Page 7 Offset 0x0C: Wakeup Frame 7 Byte Mask [31:16] Register (WF7BMR1) Bit [15:0] Name Default R/W Function Value WFBM7 [31:16] 0x0000 RW Byte mask for wake-up frame filter 7 [31:16] 6.1.94 Page 7 Offset 0x0E: Wakeup Frame 7 CRC Register (WF7CR) Bit [15:0] Name WFCRC7 Default R/W Function Value 0x0000 RW Byte mask CRC for wake-up frame filter 7. Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame. CRC-16 Polynomials = X^16 + X^15 + X^2 + 1. If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is used for verification. 111 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.95 Page 7 Offset 0x10: Wakeup Frame 7 Offset Byte Register (WF7OBR) Bit Name [7:0] WFOB7 [15:8] WFLB7 Default R/W Function Value 0x00 RW Byte mask Offset for wake-up frame filter 7. This defines the offset of the first byte in the incoming frame from which the CRC-16 is calculated for the wakeup frame recognition. Each offset value represents two bytes in the frame. For example: The offset value of 0 is the first byte of the incoming frame’s destination address. The offset value of 1 is the 3rd byte of the incoming frame, etc. 0x00 RW Mask Last Byte for wake-up frame filter 7. This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7 CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is used to verify correctness. 6.1.96 Page 7 Offset 0x12: Wakeup Frame Reply 0 ~ 1 Register (WFR01) Bit Name [7:0] WFR0 [7:0] [15:8] WFR1 [7:0] Default R/W Function Value 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 0x00 Reply TX Page point: RW Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 112 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.97 Page 7 Offset 0x14: Wakeup Frame Reply 2 ~ 3 Register (WFR23) Bit Name [7:0] WFR2 [7:0] [15:8] WFR3 [7:0] Default R/W Function Value 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 6.1.98 Page 7 Offset 0x16: Wakeup Frame Reply 4 ~ 5 Register (WFR45) Bit Name [7:0] WFR4 [7:0] [15:8] WFR5 [7:0] Default R/W Function Value 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 113 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.1.99 Page 7 Offset 0x18: Wakeup Frame Reply 6 ~ 7 Register (WFR67) Bit Name [7:0] WFR6 [7:0] [15:8] WFR7 [7:0] Default R/W Function Value 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 0x00 RW Reply TX Page point: Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM. Bit 6~5: Reply type. 00: Original packet in TX buffer. 01: Neighbor advertisement (partial checksum 0). 10: Neighbor advertisement (partial checksum 1). 11: ARP. 6.1.100 Page 7 Offset 0x1A: Wakeup Frame Partial Checksum 0 Register (WFPC0) Bit [15:0] Name WFPC0 [7:0] Default R/W Function Value 0x00 RW Calculated partial checksum of neighbor advertisement packet. 6.1.101 Page 7 Offset 0x1C: Wakeup Frame Partial Checksum 1 Register (WFPC1) Bit [15:0] Name WFPC1 [7:0] Default R/W Function Value 0x00 RW Calculated partial checksum of neighbor advertisement packet. 114 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.2 PHY Register Detailed Description The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each field of the registers. Address Name Description 0 MR0 Control 1 MR1 Status 2 MR2 PHY Identifier 1 3 MR3 PHY Identifier 2 4 MR4 Auto-negotiation Advertisement 5 MR5 Auto-negotiation Link Partner Ability 6 MR6 Auto-negotiation Expansion Default value 0x3100 0x7809 0x003B 0x1891 0x01E1 0x0000 0x0000 TAB - 15 THE EMBEDDED PHY REGISTERS Key to default: Reset value 1: Bit set to logic one 0: Bit set to logic zero X: No set value Access type RO: Read only RW: Read or write Attribute SC: Self-clearing PS: Value is permanently set LL: Latch low LH: Latch high 115 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.2.1 MR0: Basic Mode Control Register Address 00h Bit Bit Name 15 Reset 14 13 12 11 10 9 8 Default 0, RW Description Reset: 1: Software reset 0: Normal operation Loopback 0, RW Loopback: 1: Loopback enabled 0: Normal operation Speed selection 1, RW Speed selection: 1: 100 Mb/s 0: 10 Mb/s This bit must set to 1 while bit 12 (Auto-negotiation enable) is set to 1. Auto-negotiation 1, RW Auto-negotiation enable: enable 1: Auto-negotiation enabled. Bit 8 of this register is ignored and Bit 13 of this register must set to 1. 0: Auto-negotiation disabled. Bits 8 and 13 of this register determine the link speed and mode. Power down 0, RW Power down: 1: Power down 0: Normal operation Isolate (PHYAD = Isolate: 00000), RW 1: Isolate 0: Normal operation Restart 0, RW / SC Restart auto-negotiation: auto-negotiation 1: Restart auto-negotiation 0: Normal operation Duplex mode 1, RW Duplex mode: 1: Full duplex operation 0: Normal operation 7 Collision test 6:0 Reserved 0, RW X, RO Collision test: 1: Collision test enabled 0: Normal operation Reserved: Write as 0, read as “don’t care”. 116 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.2.2 MR1: Basic Mode Status Register Address 01h Bit Bit Name 15 100BASE-T4 Default Description 0, RO / PS 100BASE-T4 capable: 0: This PHY is not able to perform in 100BASE-T4 mode. 14 100BASE-TX full 1, RO / PS 100BASE-TX full-duplex capable: duplex 1: This PHY is able to perform in 100BASE-TX full-duplex mode. 13 100BASE-TX half 1, RO / PS 100BASE-TX half-duplex capable: duplex 1: This PHY is able to perform in 100BASE-TX half-duplex mode. 12 10BASE-T full 1, RO / PS 10BASE-T full-duplex capable: duplex 1: This PHY is able to perform in 10BASE-T full-duplex mode. 11 10BASE-T half 1, RO / PS 10BASE-T half-duplex capable: duplex 1: This PHY is able to perform in 10BASE-T half-duplex mode. 10:7 Reserved 0, RO Reserved. Write as 0, read as “don’t care”. 6 MF preamble 0, RO / PS Management frame preamble suppression: suppression 0: This PHY will not accept management frames with preamble suppressed. 5 Auto-negotiation 0, RO Auto-negotiation completion: complete 1: Auto-negotiation process completed 0: Auto-negotiation process not completed 4 Remote fault (Not 0, RO / LH Remote fault: supported) 1: Remote fault condition detected (cleared on read or by a chip reset) 0: No remote fault condition detected 3 Auto-negotiation 1, RO / PS Auto configuration ability: ability 1: This PHY is able to perform auto-negotiation. 2 Link status 0, RO / LL Link status: 1: Valid link established (100Mb/s or 10Mb/s operation) 0: Link not established 1 Jabber detect 0, RO / LH Jabber detection: 1: Jabber condition detected 0: No Jabber condition detected 0 Extended capability 1, RO / PS Extended capability: 1: Extended register capable 0: Basic register capable only 117 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.2.3 MR2: PHY Identifier Register 1 Address 02h Bit Bit Name 15:0 OUI_MSB 6.2.4 6.2.5 Description OUI most significant bits: Bits 3 to 18 of the OUI are mapped to bits 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored. MR3: PHY Identifier Register 2 Address 03h Bit Bit Name 15:10 OUI_LSB 9:4 3:0 Default 0x003B, RO / PS VNDR_MDL MDL_REV Default 00_0110, RO / PS 00_1001, RO / PS 0001, RO / PS Description OUI least significant bits: Bits 19 to 24 of the OUI are mapped to bits 15 to 10 of this register respectively. Vendor model number. Model revision number. MR4: Auto Negotiation Advertisement Register Address 04h Bit Bit Name Default 15 NP 0, RO / PS 14 ACK 0, RO 13 RF 0, RW 12:11 Reserved 10 Pause X, RW 1, RW 9 T4 0, RO/PS 8 TX_FD 1, RW 7 TX_HD 1, RW 6 10_FD 1, RW 5 10_HD 1, RW 4:0 Selector 0_0001, RW Description Next page indication: 0: No next page available. The PHY does not support the next page function. Acknowledgement: 1: Link partner ability data reception acknowledged 0: Not acknowledged Remote fault: 1: Fault condition detected and advertised 0: No fault detected Reserved. Write as 0, read as “don’t care”. Pause: 1: Pause operation enabled for full-duplex links 0: Pause operation not enabled 100BASE-T4 support: 0: 100BASE-T4 not supported 100BASE-TX full-duplex support: 1: 100BASE-TX full-duplex supported by this device 0: 100BASE-TX full-duplex not supported by this device 100BASE-TX half-duplex support: 1: 100BASE-TX half-duplex supported by this device 0: 100BASE-TX half-duplex not supported by this device 10BASE-T full-duplex support: 1: 10BASE-T full-duplex supported by this PHY 0: 10BASE-T full-duplex not supported by this PHY 10BASE-T half-duplex support: 1: 10BASE-T half-duplex supported by this PHY 0: 10BASE-T half-duplex not supported by this PHY Protocol selection bits: These bits contain the binary encoded protocol selector supported by this PHY. [0 0001] indicates that this PHY supports IEEE 802.3u CSMA/CD. 118 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 6.2.6 MR5: Auto Negotiation Link Partner Ability Register Address 05h Bit Bit Name 15 NP Default 0, RO 14 ACK 0, RO 13 RF 0, RO 12:11 Reserved 10 Pause X, RO 0, RO 9 T4 0, RO 8 TX_FD 0, RO 7 TX_HD 0, RO 6 10_FD 0, RO 5 10_HD 0, RO 4:0 Selector 0_0000, RO 6.2.7 Description Next page indication: 1: Link partner next page enabled 0: Link partner not next page enabled Acknowledgement: 1: Link partner ability for reception of data word acknowledged 0: Not acknowledged Remote fault: 1: Remote fault indicated by link partner 0: No remote fault indicated by link partner Reserved. Write as 0, read as “don’t care”. Pause: 1: Pause operation supported by link partner 0: Pause operation not supported by link partner 100BASE-T4 support: 1: 100BASE-T4 supported by link partner 0: 100BASE-T4 not supported by link partner 100BASE-TX full-duplex support: 1: 100BASE-TX full-duplex supported by link partner 0: 100BASE-TX full-duplex not supported by link partner 100BASE-TX half-duplex support: 1: 100BASE-TX half-duplex supported by link partner 0: 100BASE-TX half-duplex not supported by link partner 10BASE-T full-duplex support: 1: 10BASE-T full-duplex supported by link partner 0: 10BASE-T full-duplex not supported by link partner 10BASE-T half-duplex support: 1: 10BASE-T half-duplex supported by link partner 0: 10BASE-T half-duplex not supported by link partner Protocol selection bits: Link partner’s binary encoded protocol selector. MR6: Auto Negotiation Expansion Register Address 06h Bit 15:5 4 Bit Name Reserved PDF Default 0, RO 0, RO / LH 3 LP_NP_AB 0, RO 2 NP_AB 0, RO / PS 1 Page_RX 0, RO / LH 0 LP_AN_AB 0, RO Description Reserved. Write as 0, read as “don’t care”. Parallel detection fault: 1: Fault detected via the parallel detection function 0: No fault detected Link partner next page enable: 1: Link partner next page enabled 0: Link partner not next page enabled PHY next page enable: 0: PHY not next page enabled New page reception: 1: New page received 0: New page not received Link partner auto-negotiation enable: 1: Auto-negotiation supported by link partner 119 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 7.0 Electrical Specifications 7.1 DC Characteristics 7.1.1 Absolute Maximum Ratings Description VCCK (Core power supply) VCCIO (power supply for 3.3/2.5/1.8V I/O) VCCIO (Input voltage of 3.3/2.5/1.8V I/O ) Storage Temperature IIN (DC input current) IOUT (Output short circuit current) 7.1.2 Rating -0.3 to 2.16 -0.3 to 4.0 -0.3 to 4.0 -65 to 150 20 20 Units V V V C mA mA General Operating Condition Description Operating Temperature Symbol Ta Junction Temperature Supply Voltage for core (VCCK, VCC18A) Supply Voltage (VCC3A3, VCC3R3) Tj VCC18 Min 0 -40 -40 +1.62 Typ VCC33 +2.97 +3.30 +3.63 +25 +1.8 Max 70 85 +125 +1.98 120 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. Units C C V V AX88796C Low-Power SPI or Non-PCI Ethernet Controller 7.1.3 DC Characteristics of 3.3V I/O (VCCIO = 3.3V) Symbol Parameter Conditions VCCIO Power supply of 3.3V I/O 3.3V I/O VCCK Power supply of internal core cells and 1.8V I/O-to-core interface Tj Junction temperature Vil Input low voltage LVTTL spec. Vih Input high voltage Vt- Schmitt-trigger negative threshold LVTTL spec. voltage Vt+ Schmitt-trigger negative threshold voltage Vol Output low voltage Iol = 2 ~ 12 mA Voh Output high voltage Ioh = -2 ~ -12 mA Rpu Input pull-up resistance Vin = 0V Rpd Input pull-down resistance Vin = VCCIO Iin Input leakage current Vin = VCCIO or 0V Input leakage current with pull-up Vin = 0V resistance Input leakage current with pull-down Vin = VCCIO resistance IOZ Tri-state output leakage current Min 2.97 1.62 Typ 3.3 1.8 Max 3.63 1.98 Unit V V -40 25 125 0.8 ℃ V V V 2.0 0.8 2.0 2.4 40 40 -5 75 75 ±1 0.4 190 190 5 V V KΩ KΩ μA -15 -45 -90 μA 15 45 90 μA -10 ±1 10 μA 121 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 7.1.4 DC Characteristics of 2.5V I/O (VCCIO = 2.5V) Symbol Parameter Conditions VCCIO Power supply of 2.5V I/O 2.5V I/O VCCK Power supply of internal core cells and 1.8V I/O-to-core interface Tj Junction temperature Vil Input low voltage CMOS spec. Vih Input high voltage Vt- Schmitt-trigger negative voltage Schmitt-trigger negative voltage Output low voltage Output high voltage Vt+ Vol Voh Rpu Rpd Iin IOZ threshold CMOS spec. Min Typ Max 2.25 1.62 2.5 1.8 2.75 1.98 -40 25 125 0.25* VCCIO 0.625* VCCIO 0.25* VCCIO ℃ V V V 1.85 - 0.625* VCCIO 0.4 - 40 40 -5 110 110 ±1 290 290 5 KΩ KΩ μA -7 -23 -62 μA 7 23 62 μA -10 ±1 10 μA threshold Iol =1.1 ~ 6.68mA Ioh = -1.1 ~ -6.6mA Input pull-up resistance Vin = 0V Input pull-down resistance Vin = VCCIO Input leakage current Vin = VCCIO or 0V Input leakage current with pull-up Vin = 0V resistance Input leakage current with pull-down Vin = VCCIO resistance Tri-state output leakage current Unit V V 122 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. V V AX88796C Low-Power SPI or Non-PCI Ethernet Controller 7.1.5 DC Characteristics of 1.8 V I/O (VCCIO = 1.8V) Symbol Parameter Conditions VCCIO Power supply of 1.8V I/O 1.8V I/O VCCK Power supply of internal core cells and 1.8V I/O-to-core interface Tj Junction temperature Vil Input low voltage CMOS spec. Vih Input high voltage Vt- Schmitt-trigger negative voltage Schmitt-trigger negative voltage Output low voltage Output high voltage Vt+ Vol Voh Rpu Rpd Iin IOZ threshold CMOS spec. Min Typ Max 1.62 1.62 1.8 1.8 1.98 1.98 -40 25 125 0.3* VCCIO 0.7* VCCIO 0.3* VCCIO ℃ V V V threshold Iol = 0.7 ~ 4.2mA Ioh = -0.7 ~ -4.2mA Input pull-up resistance Vin = 0V Input pull-down resistance Vin = VCCIO Input leakage current Vin = VCCIO or 0V Input leakage current with pull-up Vin = 0V resistance Input leakage current with pull-down Vin = VCCIO resistance Tri-state output leakage current Unit V V 0.7* VCCIO 80 200 80 200 -5 ±1 0.7* VCCIO 0.4 - V V 510 510 5 KΩ KΩ μA -3 -9 -25 μA 3 9 25 μA -10 ±1 10 μA 123 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 7.1.6 DC Characteristics of Voltage Regulator Symbol Description VCC3R3 Power supply of on-chip voltage regulator. Operating junction temperature. Driving current. Tj Iload V18F Vdrop △V18F (△VCC3R3 x V18F) △V18F (△Iload x V18F) △V18F △Tj Iq_25℃ Iq_125℃ Cout ESR Conditions Min Typ Max Unit 3.0 3.3 3.9 V -4 0 25 125 ℃ - - 150 mA 1.71 1.8 1.89 V - - 0.2 V - 0.2 0.4 %/V VCC3R3 = 3.3V, 1mA ≦ Iload ≦ 150mA Temperature coefficient. VCC3R3 = 3.3V, -40℃ ≦ Tj ≦ 125℃ Quiescent current at 25 ℃. VCC3R3 = 3.3V - 0.02 0.05 %/mA - 0.4 - - 66 96 μA Quiescent current at 125 VCC3R3 = 3.3V ℃. - 82 120 μA Output external capacitor. Allowable effective series resistance of external capacitor. - 3.3 0.5 1 ΜF Ω Normal operation Output voltage of on-chip VCC3R3 = 3.3V voltage regulator. Dropout voltage. △ V18F = -1%, Iload = 10mA Line regulation. VCC3R3 = 3.3V, Iload = 10mA Load regulation. mV/℃ 7.2 Thermal Characteristics Description Thermal resistance of junction to case Thermal resistance of junction to ambient Symbol ΘJC ΘJA Note:  JA ,  JC defined as below T  TA T  TC ,  JC = J  JA = J P P TJ: maximum junction temperature TC: the top center of compound surface temperature Rating 18.7 49.2 Units °C/W °C/W TA: ambient or environment temperature P: input power (watts) 124 Copyright © 2010-2013 ASIX Electronics Corporation. All rights reserved. AX88796C Low-Power SPI or Non-PCI Ethernet Controller 7.3 Power Consumption  Device only Power measurements base on 3.3V/25 °C condition. Item Symbol 10BASE-T 100BASE-TX 1 2 3 4 5 6 VCCIO VCC3A3 VCC3R3* VCCK VCC18A Total Idle Full Op. 6 6 14 14 24 25 18 18 6 7 44 45 145 149 Idle Full Op. 5 5 13 13 78 79 40 40 38 39 96 97 317 320 Cable-Off Power Saving Mode PS1 PS2 2 1 10 4 20 2 15 1 5 1 32 7 106 23 Wake-On-LAN Sleep Units 10M 1 10 17 12 5 28 92 Mode 0.04 0.06μ 0.09