AT24HC02B_08

1. Features • Write Protect Pin for Hardware Data Protection – Utilizes Different Array Protection Compared to the AT24C02B • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 256 x 8 (2K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V) and 400 kHz (1.8V, 2.5V, 2.7V) Clock Rate 8-byte Page Partial Page Writes Allowed Self-timed Write Cycle (5 ms Max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years • 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages • Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers • • • • • • • • • Two-wire Serial EEPROM 2K (256 x 8) AT24HC02B 2. Description The AT24HC02B provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24HC02B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 1.8V (1.8V to 5.5V) version. Table 2-1. Pin Name A0–A2 SDA SCL WP Pin Configuration Function Address Inputs Serial Data Serial Clock Input Write Protect A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead TSSOP 8-lead PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Rev. 5134E–SEEPR–3/08 Absolute Maximum Ratings* Operating Temperature ......................................−55°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 2-1. VCC GND WP SCL SDA Block Diagram START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING DATA RECOVERY INC X DEC EEPROM LOAD DATA WORD ADDR/COUNTER Y DEC SERIAL MUX DIN DOUT DOUT/ACK LOGIC 2 AT24HC02B 5134E–SEEPR–3/08 AT24HC02B 3. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that must be hardwired for the AT24HC02B. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 8). WRITE PROTECT (WP): The AT24HC02B has a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when connected to ground (GND). When the WP pin is connected to VCC, the write protection feature is enabled and operates as shown. Table 3-1. Write Protect Part of the Array Protected WP Pin Status At VCC At GND 24HC02B Upper Half (1K) Array Normal Read/Write Operations 3 5134E–SEEPR–3/08 4. Memory Organization AT24HC02B, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8 bytes each. Random word addressing requires an 8-bit data word address. Table 4-1. Pin Capacitance(1) Applicable over recommended operating range from TAI = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Table 4-2. DC Characteristics Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol VCC1 VCC2 VCC3 VCC4 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level (1) Input High Level (1) Test Condition Min 1.8 2.5 2.7 4.5 Typ Max 5.5 5.5 5.5 5.5 Units V V V V mA mA µA µA µA µA µA µA V V V V READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS −0.6 VCC x 0.7 IOL = 2.1 mA IOL = 0.15 mA 0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05 1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V 1. VIL min and VIH max are reference only and are not tested. 4 AT24HC02B 5134E–SEEPR–3/08 AT24HC02B Table 4-3. AC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.8, 2.5, 2.7 Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time(1) Inputs Fall Time (1) 5.0-volt Min Max 1000 0.4 0.4 Units kHz µs µs 40 0.05 0.5 0.25 0.25 0 100 0.55 ns µs µs µs µs µs ns 0.3 100 .25 50 µs ns µs ns 5 1 Million ms Write Cycles Min Max 400 1.2 0.6 50 0.1 1.2 0.6 0.6 0 100 0.3 300 0.6 50 5 0.9 Stop Setup Time Data Out Hold Time Write Cycle Time 5.0V, 25°C, Byte Mode 1. This parameter is ensured by characterization only. 5 5134E–SEEPR–3/08 5. Device Operation CLOCK and DATA TRANSITIONS: T he SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-1). Data changes during SCL high periods will indicate a start or stop condition as defined below. Figure 5-1. Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 5-2). Figure 5-2. Start and Stop Definition SDA SCL START STOP STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5-2). ACKNOWLEDGE: A ll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24HC02B features a low-power standby mode that is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion of any internal operations. 6 AT24HC02B 5134E–SEEPR–3/08 AT24HC02B 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) Look for SDA high in each cycle while SCL is high, (c) Create a start condition as SDA is high. The device is ready for next communication after above steps have been completed. Figure 5-3. Software Reset Start bit Dummy Clock Cycles Start bit Stop bit SCL 1 2 3 8 9 SDA Figure 5-4. Bus Timing tF tHIGH tLOW tR SCL tSU.STA tHD.STA tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Figure 5-5. Write Cycle Timing SCL SDA 8th BIT ACK WORDn twr STOP CONDITION Notes: (1) START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5134E–SEEPR–3/08 Figure 5-6. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 6. Device Addressing The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 6-1. Figure 6-1. Device Address 2K 1 MSB 0 1 0 A2 A1 A0 R/W LSB The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must compare to their corresponding hardwired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state. 8 AT24HC02B 5134E–SEEPR–3/08 AT24HC02B 7. Write Operations BYTE WRITE: A w rite operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time, the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, see Figure 7-1 on page 9. Figure 7-1. Byte Write S T A R T S DA LINE M S B RA /C WK A C K A C K W R I T E S T O P DEVICE ADDRE SS WORD ADDRE SS DATA PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition, see Figure 7-2. Figure 7-2. Page Write S T A R T S DA LINE M S B RA /C WK A C K A C K A C K A C K W R I T E W ORD ADDRE SS ( n) S T O P DEVICE ADDRE SS DATA (n) DATA (n + 1) DATA (n + x) The data word address lower three (2K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: O nce the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0” allowing the read or write sequence to continue. 9 5134E–SEEPR–3/08 8. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: T he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition, see Figure 8-1. Figure 8-1. Current Address Read S T A R T S DA LINE M S B RA /C WK DATA N O A C K R E A D S T O P DEVICE ADDRE SS RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition, see Figure 8-2. Figure 8-2. Random Read S T A R T S DA LINE M S B R AM / CS WKB A C K M S B A C K DATA n N O A C K W R I T E S T A R T D EVICE ADDRE SS R E A D S T O P DEVICE ADDRE SS WORD ADDRE SS n D UMMY WRITE 10 AT24HC02B 5134E–SEEPR–3/08 AT24HC02B SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition, see Figure 8-3. Figure 8-3. Sequential Read 11 5134E–SEEPR–3/08 9. AT24HC02B Ordering Information Ordering Code AT24HC02B-PU (Bulk form only) AT24HC02BN-SH-B(1) (NiPdAu Lead Finish) AT24HC02BN-SH-T(2) (NiPdAu Lead Finish) AT24HC02B-TH-B AT24HC02B-TH-T (1) Voltage 1.8 1.8 1.8 1.8 1.8 1.8 Package 8P3 8S1 8S1 8A2 8A2 Die Sale Operation Range Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) (NiPdAu Lead Finish) (NiPdAu Lead Finish) (2) AT24HC02B-W-11(3) Notes: 1. “-B” denotes bulk. Industrial Temperature (−40°C to 85°C) 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8S1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options −1.8 Low Voltage (1.8V to 5.5V) 12 AT24HC02B 5134E–SEEPR–3/08 AT24HC02B 10. Part marking scheme 10.1 8-PDIP Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| H 2 B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 10.2 8-SOIC Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| H 2 B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 13 5134E–SEEPR–3/08 10.3 8-TSSOP Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| H 2 B 1 Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: 2010 2011 2012 2013 WW = SEAL WEEK 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: TOP MARK 50 = Week 50 52 = Week 52 |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| P H |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---|