AT32UC3B0512_11

Features • High Performance, Low Power AVR®32 UC 32-Bit Microcontroller – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.39 DMIPS / MHz • Up to 83 DMIPS Running at 60 MHz from Flash • Up to 46 DMIPS Running at 30 MHz from Flash – Memory Protection Unit Multi-hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 7 Peripheral DMA Channels Improves Speed for Peripheral Communication Internal High-Speed Flash – 512K Bytes, 256K Bytes, 128K Bytes, 64K Bytes Versions – Single Cycle Access up to 30 MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 96K Bytes (512KB Flash), 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB Flash) Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing Independant CPU Frequency from USB Frequency – Watchdog Timer, Real-Time Clock Timer Universal Serial Bus (USB) – Device 2.0 and Embedded Host Low Speed and Full Speed – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-chip Transceivers Including Pull-Ups – USB Wake Up from Sleep Functionality One Three-Channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, PWM, Capture and Various Counting Capabilities One 7-Channel 20-bit Pulse Width Modulation Controller (PWM) Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces – Support for Hardware Handshaking, RS485 Interfaces and Modem Line One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible One 8-channel 10-bit Analog-To-Digital Converter, 384ks/s 16-bit Stereo Audio Bitstream DAC – Sample Rate Up to 50 KHz QTouch® Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch® and QMatrix® Acquisition • • 32-bit AVR® Microcontroller AT32UC3B0512 AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1512 AT32UC3B1256 AT32UC3B1128 AT32UC3B164 • • • • • • • Summary • • • • • • 32059K–03/2011 AT32UC3B • On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins) • 5V Input Tolerant I/Os, including 4 high-drive pins • Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply 2 32059K–03/2011 AT32UC3B 1. Description The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 60 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3B incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access controller enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The PWM modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. One PWM channel can trigger ADC conversions for more accurate close loop control implementations. The AT32UC3B also features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like USART, SPI or TWI, other interfaces like flexible Synchronous Serial Controller and USB are available. The USART supports different communication modes, like SPI mode. The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I2S, UART or SPI. The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The Embedded Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. AT32UC3B integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The Nanotrace interface enables trace feature for JTAG-based debuggers. 3 32059K–03/2011 AT32UC3B 2. Overview 2.1 Blockdiagram Block diagram TCK Figure 2-1. MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 2+ OCD AVR32 UC CPU MEMORY PROTECTION UNIT MEMORY INTERFACE TDO TDI TMS JTAG INTERFACE LOCAL BUS INTERFACE FAST GPIO INSTR INTERFACE DATA INTERFACE 16/32/96 KB SRAM USB INTERFACE DMA S M S FLASH CONTROLLER VBUS D+ DID VBOF M M M S 64/128/ 256/512 KB FLASH HIGH SPEED BUS MATRIX M REGISTERS BUS HSB S S CONFIGURATION PB HSB HSB-PB BRIDGE B GENERAL PURPOSE IOs HSB-PB BRIDGE A PB PERIPHERAL DMA CONTROLLER PA PB EXTINT[7..0] KPS[7..0] NMI EXTERNAL INTERRUPT CONTROLLER REAL TIME COUNTER PDC USART1 RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS[3..0] GENERAL PURPOSE IOs INTERRUPT CONTROLLER PA PB USART0 USART2 PDC WATCHDOG TIMER 115 kHz RCOSC XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 SERIAL PERIPHERAL INTERFACE SYNCHRONOUS SERIAL CONTROLLER PDC TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER 32 KHz OSC OSC0 OSC1 PLL0 PLL1 GCLK[3..0] RESET_N A[2..0] B[2..0] CLK[2..0] PDC TWO-WIRE INTERFACE ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC PULSE WIDTH MODULATION CONTROLLER PDC SCL SDA PDC AD[7..0] ADVREF PDC DATA[1..0] DATAN[1..0] TIMER/COUNTER PWM[6..0] 4 32059K–03/2011 AT32UC3B 3. Configuration Summary The table below lists all AT32UC3B memory and package configurations: Table 3-1. Feature Flash SRAM GPIO External Interrupts TWI USART Peripheral DMA Channels SPI Full Speed USB SSC Audio Bitstream DAC Timer/Counter Channels PWM Channels Watchdog Timer Real-Time Clock Timer Power Manager 1 Mini-Host + Device 1 0 3 7 1 1 1 PLL 80-240 MHz (PLL0/PLL1) Crystal Oscillators 0.4-20 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 115 kHz (RCSYS) Crystal Oscillators 0.4-20 MHz (OSC1) 10-bit ADC number of channels JTAG Max Frequency Package TQFP64, QFN64 1 Configuration Summary AT32UC3B0512 AT32UC3B0256/128/64 AT32UC3B1512 AT32UC3B1256/128/64 512 KB 96KB 44 8 256/128/64 KB 32/32/16KB 512 KB 96KB 28 6 1 3 7 1 Device 0 256/128/64 KB 32/16/16KB 0 Oscillators 8 1 60 MHz 6 TQFP48, QFN48 5 32059K–03/2011 AT32UC3B 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 4-1. TQFP64 / QFN64 Pinout VDDIO PA23 PA22 PA21 PA20 PB07 PA29 PA28 PA19 PA18 PB06 PA17 PA16 PA15 PA14 PA13 GND DP DM VBUS VDDPLL PB08 PB09 VDDCORE PB10 PB11 PA24 PA25 PA26 PA27 RESET_N VDDIO 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PA31 PA30 PA08 PA07 PA06 PA05 PA04 PA03 VDDCORE PB01 PB00 PA02 PA01 PA00 TCK GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDDIO PA12 PA11 PA10 PA09 PB05 PB04 PB03 PB02 GND VDDCORE VDDIN VDDOUT VDDANA ADVREF GNDANA 6 32059K–03/2011 AT32UC3B Figure 4-2. TQFP48 / QFN48 Pinout VDDIO PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 GND DP DM VBUS VDDPLL VDDCORE PA24 PA25 PA26 PA27 RESET_N VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 12 11 10 9 8 7 6 5 4 3 2 1 PA08 PA07 PA06 PA05 PA04 PA03 VDDCORE PA02 PA01 PA00 TCK GND 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 VDDIO PA12 PA11 PA10 PA09 GND VDDCORE VDDIN VDDOUT VDDANA ADVREF GNDANA Note: On QFN packages, the exposed pad is not connected to anything. 4.2 4.2.1 Peripheral Multiplexing on I/O lines Multiplexed signals Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C or D (D is only available for UC3Bx512 parts). The following table define how the I/O lines on the peripherals A, B,C or D are multiplexed by the GPIO. GPIO Controller Function Multiplexing Function D 64-pin 3 4 5 9 10 11 12 PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 ADC - AD[0] ADC - AD[1] EIC - EXTINT[0] EIC - EXTINT[1] PM - GCLK[0] PM - GCLK[1] ADC - AD[2] ADC - AD[3] USBB - USB_ID USBB - USB_VBOF USART1 - DCD USART1 - DSR ABDAC - DATA[0] ABDAC - DATAN[0] ABDAC - DATA[1] ABDAC - DATAN[1] Function A Function B Function C (only for UC3Bx512) Table 4-1. 48-pin 3 4 5 7 8 9 10 7 32059K–03/2011 AT32UC3B Table 4-1. 11 12 20 21 22 23 25 26 27 28 29 30 31 32 33 34 35 43 44 45 46 GPIO Controller Function Multiplexing 13 14 28 29 30 31 33 34 35 36 37 39 40 44 45 46 47 59 60 61 62 41 42 15 16 6 7 24 25 26 27 38 43 54 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 PWM - PWM[0] PWM - PWM[1] TWI - SCL TWI - SDA USART0 - RTS USART0 - CTS EIC - NMI SPI0 - MOSI SPI0 - SCK SPI0 - NPCS[0] SPI0 - NPCS[1] USART0 - RXD USART0 - TXD USART1 - CLK PWM - PWM[2] PWM - PWM[6] USART1 - TXD USART1 - RXD SPI0 - MISO USBB - USB_ID USBB - USB_VBOF USART0 - CLK TC - CLK0 ADC - AD[6] ADC - AD[7] TC - A0 TC - B0 EIC - EXTINT[6] EIC - EXTINT[7] USART1 - CTS USART1 - RTS SSC - RX_CLOCK SSC - RX_DATA SSC RX_FRAME_SYNC ADC - AD[4] ADC - AD[5] SPI0 - NPCS[2] SPI0 - NPCS[3] TC - A2 TC - B2 PWM - PWM[2] PWM - PWM[3] PWM - PWM[4] TC - CLK1 TC - CLK2 PWM - PWM[5] PWM - PWM[6] TC - CLK0 TC - A1 TC - B1 SPI0 - NPCS[1] SPI0 - NPCS[0] PWM - PWM[3] USART2 - TXD USART2 - RXD PWM - PWM[4] TC - CLK1 EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] TC - A1 TC - B1 SPI0 - NPCS[3] SPI0 - NPCS[2] USART1 - DCD USART1 - DSR USART1 - DTR USART1 - DTR USART1 - RI USART1 - CTS USART1 - RTS PWM - PWM[0] PWM - PWM[1] USART0 - CLK EIC - EXTINT[2] USART2 - CLK PWM - PWM[4] SPI0 - SCK SPI0 - MISO SPI0 - MOSI USART2 - RXD USART2 - TXD ADC - TRIGGER EIC - EXTINT[3] EIC - EXTINT[4] EIC - EXTINT[5] TC - A0 TC - B0 SPI0 - MISO SPI0 - MOSI PM - GCLK[2] PWM - PWM[6] USART2 - CTS USART2 - RTS USART1 - TXD USART1 - RXD TC - CLK2 PWM - PWM[5] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] ABDAC - DATA[0] ABDAC - DATAN[0] ABDAC - DATA[1] ABDAC - DATA[1] ABDAC - DATAN[1] ABDAC - DATAN[0] USART1 - RXD SSC RX_FRAME_SYNC SSC - TX_CLOCK SSC - TX_DATA SSC TX_FRAME_SYNC ABDAC - DATA[0] PWM - PWM[0] PWM - PWM[1] SSC - RX_DATA USART1 - TXD SSC - RX_CLOCK PM - GCLK[2] SSC RX_FRAME_SYNC SSC - RX_CLOCK 8 32059K–03/2011 AT32UC3B Table 4-1. GPIO Controller Function Multiplexing 55 57 58 PB09 PB10 PB11 GPIO 41 GPIO 42 GPIO 43 SSC - TX_CLOCK SSC - TX_DATA SSC TX_FRAME_SYNC USART1 - RI TC - A2 TC - B2 EIC - SCAN[7] USART0 - RXD USART0 - TXD ABDAC - DATAN[1] 4.2.2 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the I/O Controller configuration. Table 4-2. 64QFP/QFN 2 3 4 5 JTAG Pinout 48QFP/QFN 2 3 4 5 Pin name TCK PA00 PA01 PA02 JTAG pin TCK TDI TDO TMS 4.2.3 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 4-3. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] Nexus OCD AUX port connections AXS=0 PB05 PB04 PB03 PB02 PB01 PB00 PA31 PA15 PA30 PB06 PB07 AXS=1 PA14 PA08 PA07 PA06 PA05 PA04 PA03 PA15 PA13 PA09 PA10 4.2.4 Oscillator Pinout The oscillators are not mapped to the normal A, B or C functions and their muxings are controlled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this. 9 32059K–03/2011 AT32UC3B Table 4-4. Oscillator pinout QFP64 pin 39 41 22 31 30 40 42 23 31 Pad PA18 PA28 PA11 PA19 PA29 PA12 Oscillator pin XIN0 XIN1 XIN32 XOUT0 XOUT1 XOUT32 QFP48 pin 30 4.3 High Drive Current GPIO Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical Characteristics section). Table 4-5. High Drive Current GPIO GPIO Name PA20 PA21 PA22 PA23 5. Signals Description The following table gives details on the signal name classified by peripheral. Table 5-1. Signal Name Signal Description List Function Power Type Active Level Comments VDDPLL PLL Power Supply Power Input Power Input Power Input Power Input Power Input 1.65V to 1.95 V VDDCORE Core Power Supply 1.65V to 1.95 V VDDIO I/O Power Supply 3.0V to 3.6V VDDANA Analog Power Supply 3.0V to 3.6V VDDIN Voltage Regulator Input Supply 3.0V to 3.6V 10 32059K–03/2011 AT32UC3B Table 5-1. Signal Name VDDOUT GNDANA GND Signal Description List (Continued) Function Voltage Regulator Output Analog Ground Ground Type Power Output Ground Ground Clocks, Oscillators, and PLL’s Active Level Comments 1.65V to 1.95 V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO0 - MDO5 MSEO0 - MSEO1 EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Output Output Power Manager - PM Low Low GCLK0 - GCLK2 RESET_N Generic Clock Pins Reset Pin Output Input External Interrupt Controller - EIC Low EXTINT0 - EXTINT7 KPS0 - KPS7 NMI External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose I/O pin- GPIOA, GPIOB PA0 - PA31 PB0 - PB11 Parallel I/O Controller GPIOA Parallel I/O Controller GPIOB I/O I/O 11 32059K–03/2011 AT32UC3B Table 5-1. Signal Name Signal Description List (Continued) Function Type Serial Peripheral Interface - SPI0 Active Level Comments MISO MOSI NPCS0 - NPCS3 SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC Low RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TIMER A0 A1 A2 B0 B1 B2 CLK0 CLK1 CLK2 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input I/O I/O I/O I/O I/O I/O Input Input Input Two-wire Interface - TWI SCL SDA Serial Clock Serial Data I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2 CLK CTS Clock Clear To Send I/O Input 12 32059K–03/2011 AT32UC3B Table 5-1. Signal Name DCD DSR DTR RI RTS RXD TXD Signal Description List (Continued) Function Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Transmit Data Output Input Output Analog to Digital Converter - ADC Type Active Level Comments Only USART1 Only USART1 Only USART1 Only USART1 AD0 - AD7 Analog input pins Analog input Analog input 2.6 to 3.6V ADVREF Analog positive reference voltage input Audio Bitstream DAC - ABDAC DATA0 - DATA1 DATAN0 - DATAN1 D/A Data out D/A Data inverted out Output Output Pulse Width Modulator - PWM PWM0 - PWM6 PWM Output Pins Output Universal Serial Bus Device - USBB DDM DDP VBUS USBID USB_VBOF USB Device Port Data USB Device Port Data + USB VBUS Monitor and Embedded Host Negociation ID Pin of the USB Bus USB VBUS On/off: bus power control port Analog Analog Analog Input Input output 5.1 JTAG pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. These 3 pins can be used as GPIO-pins. At reset state, these pins are in GPIO mode. TCK pin cannot be used as GPIO pin. JTAG interface is enabled when TCK pin is tied low. 13 32059K–03/2011 AT32UC3B 5.2 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 5.3 TWI pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as GPIO pins. 5.4 GPIO pins All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset Value” of the GPIO Controller user interface table. 5.5 High drive pins The four pins PA20, PA21, PA22, PA23 have high drive output capabilities. 5.6 5.6.1 Power Considerations Power Supplies The AT32UC3B has several types of power supply pins: • • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. VDDANA: Powers the ADC Voltage is 3.3V nominal. VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal. VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. VDDPLL: Powers the PLL. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO and VDDPLL. The ground pin for VDDANA is GNDANA. For QFN packages, the center pad must be left unconnected. Refer to ”Electrical Characteristics” on page 35 for power consumption on the various supply pins. The main requirement for power supplies connection is to respect a star topology for all electrical connection. 14 32059K–03/2011 AT32UC3B Figure 5-1. Power Supply Single Power Supply Dual Power Supply 3.3V VDDANA 3.3V VDDANA VDDIO VDDIO ADVREF ADVREF VDDIN 1.8V Regulator VDDIN 1.8V Regulator VDDOUT 1.8 V VDDOUT VDDCORE VDDCORE VDDPLL VDDPLL 5.6.2 5.6.2.1 Voltage Regulator Single Power Supply The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be externally connected to the 1.8V domains. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and GND as close to the chip as possible Figure 5-2. Supply Decoupling 3.3V CIN2 CIN1 VDDIN 1.8V Regulator VDDOUT 1.8V COUT2 COUT1 15 32059K–03/2011 AT32UC3B Refer to Section 9.3 on page 38 for decoupling capacitors values and regulator characteristics. For decoupling recommendations for VDDIO, VDDANA, VDDCORE and VDDPLL, please refer to the Schematic checklist. 5.6.2.2 Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current. To avoid over consumption during the power up sequence, VDDIO and VDDCORE voltage difference needs to stay in the range given Figure 5-3. Figure 5-3. 4 Extra consumption on VDDIO VDDIO versus VDDCORE during power up sequence 3.5 3 2.5 VDDIO (V) 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 VDDCORE (V) 1.2 1.4 1.6 1.8 2 Extra consumption on VDDCORE 5.6.3 Analog-to-Digital Converter (ADC) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. Figure 5-4. ADVREF Decoupling 3.3V C VREF2 ADVREF C VREF1 Refer to Section 9.4 on page 38 for decoupling capacitors values and electrical characteristics. In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption. 16 32059K–03/2011 AT32UC3B 6. Processor and Architecture Rev: 1.0.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 6.1 Features • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extention with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection – – – – – 6.2 AVR32 Architecture AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 17 32059K–03/2011 AT32UC3B The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 6.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet. Figure 6-1 on page 19 displays the contents of AVR32UC. 18 32059K–03/2011 AT32UC3B Figure 6-1. Interrupt controller interface Overview of the AVR32UC CPU Reset interface OCD interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master High Speed Bus 6.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 6-2 on page 20 shows an overview of the AVR32UC pipeline stages. CPU Local Bus Data RAM interface CPU Local Bus master 19 32059K–03/2011 AT32UC3B Figure 6-2. The AVR32UC Pipeline MUL Multiply unit IF ID Regf ile Read A LU Regf ile w rite A LU unit Pref etch unit Decode unit Load-store unit LS 6.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 6.3.3 Java Support AVR32UC does not provide Java hardware acceleration. 6.3.4 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 6.3.5 20 32059K–03/2011 AT32UC3B The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 6-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported alignment Word Word 6.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 6.3.7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 21 32059K–03/2011 AT32UC3B 6.4 6.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 6-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 6.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 6-4 on page 22 and Figure 6-5 on page 23. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 6-4. Bit 31 The Status Register High Halfword Bit 16 - LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 22 32059K–03/2011 AT32UC3B Figure 6-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 6.4.3 6.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 6-2 on page 23. Table 6-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 6.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 23 32059K–03/2011 AT32UC3B All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 6.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 6-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 JAVA_LV1 JAVA_LV2 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 24 32059K–03/2011 AT32UC3B Table 6-3. Reg # 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 System Registers (Continued) Address 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 360 364 Name JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 25 32059K–03/2011 AT32UC3B Table 6-3. Reg # 92 93 94 95 96 97 98 99 100 101 102 103-191 192-255 System Registers (Continued) Address 368 372 376 380 384 388 392 396 400 404 408 448-764 768-1020 Name MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR Reserved IMPL Function MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Reserved for future use IMPLEMENTATION DEFINED 6.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 6-4 on page 29. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. 6.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. 26 32059K–03/2011 AT32UC3B The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 6.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 6-4, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete i nstruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 6.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 6.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the 27 32059K–03/2011 AT32UC3B status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 6.5.5 Entry Points for Events Several different event handler entry points exists. In AVR32UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 6-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 6-4. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit. 28 32059K–03/2011 AT32UC3B Table 6-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x8000_0000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC of offending instruction PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction 29 32059K–03/2011 AT32UC3B 6.6 Module Configuration All AT32UC3B parts do not implement the same CPU and Architecture Revision. Table 6-5. CPU and Architecture Revision Architecture Revision 2 1 1 1 Part Name AT32UC3Bx512 AT32UC3Bx256 AT32UC3Bx128 AT32UC3Bx64 30 32059K–03/2011 AT32UC3B 7. Memories 7.1 Embedded Memories • Internal High-Speed Flash 512KBytes (AT32UC3B0512, AT32UC3B1512) 256 KBytes (AT32UC3B0256, AT32UC3B1256) 128 KBytes (AT32UC3B0128, AT32UC3B1128) 64 KBytes (AT32UC3B064, AT32UC3B164) • - 0 Wait State Access at up to 30 MHz in Worst Case Conditions • - 1 Wait State Access at up to 60 MHz in Worst Case Conditions • - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • - 100 000 Write Cycles, 15-year Data Retention Capability • - 4 ms Page Programming Time, 8 ms Chip Erase Time • - Sector Lock Capabilities, Bootloader Protection, Security Bit • - 32 Fuses, Erased During Chip Erase • - User Page For Data To Be Preserved During Chip Erase • Internal High-Speed SRAM, Single-cycle access at full speed – 96KBytes ((AT32UC3B0512, AT32UC3B1512) – 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128) – 16KBytes (AT32UC3B064 and AT32UC3B164) – – – – 7.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical address space is mapped as follows: Table 7-1. AT32UC3B Physical Memory Map Embedded SRAM 0x0000_0000 AT32UC3B0512 AT32UC3B1512 AT32UC3B0256 AT32UC3B1256 96 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes Embedded Flash 0x8000_0000 512 Kbytes 256 Kbytes 128 Kbytes 64 Kbytes HSB-PB Bridge A 0xFFFF_0000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes HSB-PB Bridge B 0xFFFE_0000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Device Start Address USB Data 0xD000_0000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Size AT32UC3B0128 AT32UC3B1128 AT32UC3B064 AT32UC3B164 31 32059K–03/2011 AT32UC3B 7.3 Peripheral Address Map Peripheral Address Mapping Address 0xFFFE0000 Table 7-2. Peripheral Name USB USB 2.0 Interface - USB 0xFFFE1000 HMATRIX 0xFFFE1400 HSB Matrix - HMATRIX HFLASHC 0xFFFF0000 Flash Controller - HFLASHC PDCA 0xFFFF0800 Peripheral DMA Controller - PDCA INTC 0xFFFF0C00 Interrupt controller - INTC PM 0xFFFF0D00 Power Manager - PM RTC 0xFFFF0D30 Real Time Counter - RTC WDT 0xFFFF0D80 Watchdog Timer - WDT EIM 0xFFFF1000 External Interrupt Controller - EIM GPIO 0xFFFF1400 General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Serial Peripheral Interface - SPI0 USART0 0xFFFF1800 USART1 0xFFFF1C00 USART2 0xFFFF2400 SPI0 0xFFFF2C00 TWI 0xFFFF3000 Two-wire Interface - TWI PWM 0xFFFF3400 Pulse Width Modulation Controller - PWM SSC 0xFFFF3800 Synchronous Serial Controller - SSC TC Timer/Counter - TC 32 32059K–03/2011 AT32UC3B Table 7-2. Peripheral Address Mapping 0xFFFF3C00 ADC 0xFFFF4000 Analog to Digital Converter - ADC ABDAC Audio Bitstream DAC - ABDAC 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 7-3. Port 0 Local bus mapped GPIO registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x4000_0040 0x4000_0044 0x4000_0048 0x4000_004C 0x4000_0050 0x4000_0054 0x4000_0058 0x4000_005C 0x4000_0060 0x4000_0140 0x4000_0144 0x4000_0148 0x4000_014C 0x4000_0150 0x4000_0154 0x4000_0158 0x4000_015C 0x4000_0160 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 1 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 33 32059K–03/2011 AT32UC3B 8. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to section Power Manager (PM). 8.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal RC Oscillator. 8.2 Fetching of initial instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. When powering up the device, there may be a delay before the voltage has stabilized, depending on the rise time of the supply used. The CPU can start executing code as soon as the supply is above the POR threshold, and before the supply is stable. Before switching to a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above the minimum level. 34 32059K–03/2011 AT32UC3B 9. Electrical Characteristics 9.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on GPIO Pins with respect to Ground for TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 ............................................................ -0.3 to 3.6V Voltage on GPIO Pins with respect to Ground except for TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 ....................................... -0.3 to 5.5V Maximum Operating Voltage (VDDCORE, VDDPLL) ..... 1.95V Maximum Operating Voltage (VDDIO,VDDIN,VDDANA).. 3.6V Total DC Output Current on all I/O Pin for 48-pin package ....................................................... 200 mA for 64-pin package ....................................................... 265 mA 35 32059K–03/2011 AT32UC3B 9.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 9-1. Symbol VVDDCORE VVDDPLL VVDDIO VIL DC Characteristics Parameter DC Supply Core DC Supply PLL DC Supply Peripheral I/Os Input Low-level Voltage All I/O pins except TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 All I/O pins except TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 TCK, RESET_N PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 IOL= -4mA for all I/O except PA20, PA21, PA22, PA23 IOL= -8mA for PA20, PA21, PA22, PA23 IOL= -4mA for all I/O except PA20, PA21, PA22, PA23 VVDDIO -0.4 VVDDIO -0.4 -4 -8 4 8 1 7 7 7 7 Conditions Min. 1.65 1.65 3.0 -0.3 Typ. Max. 1.95 1.95 3.6 +0.8 Unit V V V V AT32UC3B064 AT32UC3B0128 AT32UC3B0256 AT32UC3B164 AT32UC3B1128 AT32UC3B1256 2.0 5.5 V 2.0 3.6 V VIH Input High-level Voltage 2.0 5.5 V AT32UC3B0512 AT32UC3B1512 2.5 3.6 V 2.0 3.6 V 0.4 0.4 V V V V mA mA mA mA µA pF pF pF pF VOL Output Low-level Voltage VOH Output High-level Voltage IOL= -8mA for PA20, PA21, PA22, PA23 All I/O pins except PA20, PA21, PA22, PA23 IOL Output Low-level Current PA20, PA21, PA22, PA23 All I/O pins except for PA20, PA21, PA22, PA23 Output High-level Current PA20, PA21, PA22, PA23 Input Leakage Current Pullup resistors disabled QFP64 QFP48 IOH ILEAK CIN Input Capacitance QFN64 QFN48 36 32059K–03/2011 AT32UC3B Table 9-1. Symbol DC Characteristics Parameter Conditions AT32UC3B064 AT32UC3B0128 AT32UC3B0256 AT32UC3B164 AT32UC3B1128 AT32UC3B1256 All I/O pins except RESET_N, TCK, TDI, TMS pins RESET_N pin, TCK, TDI, TMS pins All I/O pins except PA20, PA21, PA22, PA23, RESET_N, TCK, TDI, TMS pins PA20, PA21, PA22, PA23 RESET_N pin, TCK, TDI, TMS pins AT32UC3B064 AT32UC3B0128 AT32UC3B0256 AT32UC3B164 AT32UC3B1128 AT32UC3B1256 On VVDDCORE = 1.8V, device in static mode All inputs driven including JTAG; RESET_N=1 On VVDDCORE = 1.8V, device in static mode All inputs driven including JTAG; RESET_N=1 TA = 25°C Min. 13 Typ. 19 Max. 25 Unit KΩ 5 12 25 KΩ RPULLUP Pull-up Resistance 10 15 20 KΩ AT32UC3B0512 AT32UC3B1512 5 5 7.5 10 12 25 KΩ KΩ 6 µA TA = 85°C 42.5 µA ISC Static Current TA = 25°C 7.5 µA AT32UC3B0512 AT32UC3B1512 TA = 85°C 39 µA 37 32059K–03/2011 AT32UC3B 9.3 Regulator Characteristics Electrical Characteristics Parameter Supply voltage (input) Supply voltage (output) Maximum DC output current Static Current of internal regulator VVDDIN = 3.3V Low Power mode (stop, deep stop or static) at TA = 25°C 10 Conditions Min. 3 1.70 Typ. 3.3 1.8 Max. 3.6 1.85 100 Unit V V mA µA Table 9-2. Symbol VVDDIN VVDDOUT IOUT ISCR Table 9-3. Symbol CIN1 CIN2 COUT1 COUT2 Decoupling Requirements Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Conditions Typ. 1 4.7 470 2.2 Technology NPO X7R NPO X7R Unit nF µF pF µF 9.4 9.4.1 Analog Characteristics ADC Reference Electrical Characteristics Parameter Analog voltage reference (input) Conditions Min. 2.6 Typ. Max. 3.6 Unit V Table 9-4. Symbol VADVREF Table 9-5. Symbol CVREF1 CVREF2 Decoupling Requirements Parameter Voltage reference Capacitor 1 Voltage reference Capacitor 2 Conditions Typ. 10 1 Technology NPO NPO Unit nF uF 9.4.2 Table 9-6. Symbol BOD BOD Level Values Parameter Value 00 0000b 01 0111b Conditions Min. Typ. 1.44 1.52 1.61 1.71 Max. Unit V V V V BODLEVEL 01 1111b 10 0111b Table 9-6 describes the values of the BODLEVEL field in the flash FGPFR register. 38 32059K–03/2011 AT32UC3B Table 9-7. Symbol TBOD BOD Timing Parameter Minimum time with VDDCORE < VBOD to detect power failure Conditions Falling VDDCORE from 1.8V to 1.1V Min. Typ. 300 Max. 800 Unit ns 9.4.3 Table 9-8. Symbol VDDRR VDDFR Reset Sequence Electrical Characteristics Parameter VDDCORE rise rate to ensure poweron-reset VDDCORE fall rate to ensure poweron-reset Rising threshold voltage: voltage up to which device is kept under reset by POR on rising VDDCORE Falling threshold voltage: voltage when POR resets device on falling VDDCORE On falling VDDCORE, voltage must go down to this value before supply can rise again to ensure reset signal is released at VPOR+ Minimum time with VDDCORE < VPORTime for reset signal to be propagated to system Time for Cold System Startup: Time for CPU to fetch its first instruction (RCosc not calibrated) Time for Hot System Startup: Time for CPU to fetch its first instruction (RCosc calibrated) 480 Rising VDDCORE: VRESTART -> VPOR+ Falling VDDCORE: 1.8V -> VPOR+ Conditions Min. 2.5 0.01 400 Typ. Max. Unit V/ms V/ms VPOR+ 1.4 1.55 1.65 V VPOR- 1.2 1.3 1.4 V VRESTART Falling VDDCORE: 1.8V -> VRESTART Falling VDDCORE: 1.8V -> 1.1V -0.1 0.5 V TPOR TRST 15 200 400 µs µs TSSU1 960 µs TSSU2 420 µs 39 32059K–03/2011 AT32UC3B Figure 9-1. VDDCORE MCU Cold Start-Up RESET_N tied to VDDIN VPORVRESTART VPOR+ RESET_N Internal POR Reset TPOR Internal MCU Reset TRST TSSU1 Figure 9-2. VDDCORE MCU Cold Start-Up RESET_N Externally Driven VPORVRESTART VPOR+ RESET_N Internal POR Reset TPOR Internal MCU Reset TRST TSSU1 Figure 9-3. VDDCORE MCU Hot Start-Up RESET_N BOD Reset WDT Reset TSSU2 Internal MCU Reset In dual supply configuration, the power up sequence must be carefully managed to ensure a safe startup of the device in all conditions. The power up sequence must ensure that the internal logic is safely powered when the internal reset (Power On Reset) is released and that the internal Flash logic is safely powered when the CPU fetch the first instructions. 40 32059K–03/2011 AT32UC3B Therefore VDDCORE rise rate (VDDRR) must be equal or superior to 2.5V/ms and VDDIO must reach VDDIO mini value before 500 us (< TRST + TSSU1) after VDDCORE has reached VPOR+ min value. Figure 9-4. Dual Supply Configuration V D D IO m in V D D IO V p o r+ m in VDDCORE 2. 5 V V DD /m R sm R ini m um