AT60142F-DD15M-E

Features • Operating Voltage: 3.3V • Access Time: – 15 ns (AT60142F) • Very Low Power Consumption • • • • • • • • • – Active: 650 mW (Max) @ 15 ns, 540 mW (Max) @ 25 ns – Standby: 3.3 mW (Typ) Wide Temperature Range: -55 to +125°C TTL-Compatible Inputs and Outputs Asynchronous Designed on 0.25 µm Radiation Hardened Process No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019 500 Mils Wide FP36 Package ESD Better than 4000V Quality Grades: ESCC with 9301/052, QML-Q or V with smd 5962-05208 Description The AT60142F is a very low power CMOS static RAM organized as 524 288 x 8 bits. Atmel brings the solution to applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. Utilizing an array of six transistors (6T) memory cells, the AT60142F combines an extremely low standby supply current (Typical value = 1 mA) with a fast access time at 15 ns or better over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. The AT60142F is processed according to the methods of the latest revision of the MIL PRF 38535 or ESCC 9000. It is produced on a radiation hardened 0.25 µm CMOS process. Rad Hard 512K x 8 Very Low Power CMOS SRAM AT60142F Rev. 4408G–AERO–04/09 1 AT60142F Block Diagram Pin Configuration A0 A1 A2 A3 A4 CS I/O1 I/O2 Vcc GND I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O8 I/O7 GND Vcc I/O6 I/O5 A14 A13 A12 A11 A10 N/C 36 - pin -Flatpack - 500 Mils 2 4408G–AERO–04/09 Pin Description Table 1. Pin Names Name A0 - A18 I/O1 - I/O8 CS WE OE Vcc GND Description Address Inputs Data Input/Output Chip Select Write Enable Output Enable Power Supply Ground Table 2. Truth Table(1) CS H L L L Note: WE X H L H OE X L X H Inputs/Outputs Z Data Out Data In Z Mode Deselect/ Power-down Read Write Output Disable 1. L=low, H=high, X= L or H, Z=high impedance. 3 AT60142F 4408G–AERO–04/09 AT60142F Electrical Characteristics Absolute Maximum Ratings* Supply Voltage to GND Potential: ....................... -0.5V + 4.6V Voltage range on any input: ...................... GND -0.5V to 4.6V Voltage range on any ouput: ..................... GND -0.5V to 4.6V Storage Temperature: ................................... -65⋅C to + 150⋅C Output Current from Output Pins: ................................ 20 mA Electrostatic Discharge Voltage: ............................... > 4000V (MIL STD 883D Method 3015.3) *NOTE: Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. Military Operating Range Operating Voltage Military 3.3 + 0.3V Operating Temperature -55°C to + 125°C Recommended DC Operating Conditions Parameter Vcc GND VIL VIH Description Supply voltage Ground Input low voltage Input high voltage Min 3 0.0 GND - 0.3 2.2 Typ 3.3 0.0 0.0 – Max 3.6 0.0 0.8 VCC + 0.3 Unit V V V V Capacitance Parameter Cin(1) Cout(1) Note: Description Input capacitance Output capacitance Min – – Typ – – Max 12 12 Unit pF pF 1. Guaranteed but not tested. 4 4408G–AERO–04/09 DC Parameters Parameter IIX (1) Description Input leakage current Output leakage current Output low voltage Output high voltage Minimum -1 -1 – 2.4 Typical – – – – Maximum 1 1 0.4 – Unit μA μA V V IOZ(1) VOL(2) VOH(3) 1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled. 2. 3. VCC min. IOL = 8 mA VCC min. IOH = -4 mA. Consumption Symbol ICCSB (1) ICCSB1 (2) Description Standby Supply Current Standby Supply Current TAVAV/TAVAW Test Condition – AT60142F-15 2 Unit mA Value max – 15 ns 25 ns 50 ns 1 µs 15 ns 25 ns 50 ns 1 µs 1.8 180 150 75 10 150 130 120 100 mA max ICCOP(3) Read Dynamic Operating Current mA max ICCOP(4) Write Dynamic Operating Current mA max 1. 2. 3. 4. CS >VIH CS > VCC - 0.3V F = 1/TAVAV, Iout = 0 mA, WE = OE = VIH, VIN = GND/VCC, VCC max. F = 1/TAVAW, Iout = 0 mA, WE = VIL, OE = VIH , VIN = GND/VCC, VCC max. 5 AT60142F 4408G–AERO–04/09 AT60142F Data Retention Mode Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. During data retention chip select CS must be held high within VCC to VCC -0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power-up and power-down transitions CS and OE must be kept between VCC + 0.3V and 70% of VCC. 4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages (3V). Figure 1. Data Retention Timing Data Retention Characteristics Parameter VCCDR Description VCC for data retention Chip deselect to data retention time Operation recovery time Data retention current TAVAV = Read cycle time. CS = VCC, VIN = GND/VCC. Min 2.0 Typ TA = 25°C – Max – Unit V tCDR 0.0 – – ns tR ICCDR (2) 1. 2. tAVAV – (1) – 0.700 – 1.3 ns mA 6 4408G–AERO–04/09 AC Characteristics Temperature Range:................................................ -55 +125°C Supply Voltage:........................................................ 3.3 +0.3V Input Pulse Levels: .................................................. GND to 3.0V Input Rise and Fall Times:....................................... 3ns (10 - 90%) Input and Output Timing Reference Levels: ............ 1.5V Output Loading IOL/IOH:............................................ See Figure 1 Figure 2. AC Test Loads Waveforms 7 AT60142F 4408G–AERO–04/09 AT60142F Write Cycle Symbol TAVAW TAVWL TAVWH TDVWH TELWH TWLQZ TWLWH TWHAX TWHDX TWHQX Notes: Parameter Write cycle time Address set-up time Address valid to end of write Data set-up time CS low to write end Write low to high Z(1) Write pulse width Address hold from end of write Data hold time Write high to low Z(1) AT60142F-15 15 0 8 7 12 6 8 0 0 3 Unit ns ns ns ns ns ns ns ns ns ns Value min min min min min max min min min min 1. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 7.) Figure 3. Write Cycle 1. WE Controlled, OE High During Write E Figure 4. Write Cycle 2. WE Controlled, OE Low E 8 4408G–AERO–04/09 Figure 5. Write Cycle 3. CS Controlled(1) E Note: The internal write time of the memory is defined by the overlap of CS Low and W LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. Data out is high impedance if OE= VIH. 9 AT60142F 4408G–AERO–04/09 AT60142F Read Cycle Symbol TAVAV TAVQV TAVQX TELQV TELQX TEHQZ TGLQV TGLQX TGHQZ Note: Parameter Read cycle time Address access time Address valid to low Z Chip-select access time CS low to low Z(1) CS high to high Z(1) Output Enable access time OE low to low Z(1) OE high to high Z (1) AT60142F-15 15 15 5 15 5 6 6 2 5 Unit ns ns ns ns ns ns ns ns ns Value min max min max min max max min max 1. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 7.) Figure 6. Read Cycle nb 1: Address Controlled (CS = OE = VIL, WE = VIH) Figure 7. Read Cycle nb 2: Chip Select Controlled (WE = VIH) 10 4408G–AERO–04/09 Ordering Information Part Number AT60142F-DC15M-E 5962-0520802QXC 5962-0520802VXC 5962R0520802VXC 930105202 AT60142F-DS15M-E 5962-0520802QYC 5962-0520802VYC 5962R0520802VYC AT60142F-DS15-SCC(3) AT60142F-DD15M-E Note: (1) (1) (2) Temperature Range 25°C -55° to +125°C -55° to +125°C -55° to +125°C -55° to +125°C 25°C -55° to +125°C -55° to +125°C -55° to +125°C -55° to +125°C 25°C -55° to +125°C Speed 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V 15 ns/3.3V Package FP36.5 FP36.5 FP36.5 FP36.5 FP36.5 FP36.5 grounded lid FP36.5 grounded lid FP36.5 grounded lid FP36.5 grounded lid FP36.5 grounded lid Die Die Flow Engineering Samples QML Q QML V QML V RHA ESCC Engineering Samples QML Q QML V QML V RHA ESCC Engineering Samples QML V AT60142F-DD15MSV 1. Contact Atmel for availability. 2. Will be replaced by SMD part number when available. 3. Will be replaced by ESCC part number when available. 11 AT60142F 4408G–AERO–04/09 AT60142F Package Drawings 36-lead Flat Pack (500 Mils) Notes: 1. package DC : lid is NOT connected to GROUND 2. package DS : lid is connected to GROUND Document Revision History Changes from Rev. E to Rev. F Changes from Rev F to Rev. G 1. Split datasheet into two separate documents: removed AT60142FT from this document. Please refer to document 7726 on the Atmel web site. 1. Suppression of version AT60142G 2. Update of Absolute Maximum Ratings section 12 4408G–AERO–04/09 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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