• • • • • • • • • • • • • •
Programmable AVR® 8-bit Flash Microcontroller Transmitter IC Frequency: 315 MHz (ATA6285) and 433 MHz (ATA6286) Support ASK/FSK Modulation with Integrated FSK Switch 6 dBm Output Power with Typically 8.5 mA Active Current Consumption in Transmission Mode Low-power Microcontroller Requires Typically 0.6 µA Sleep Current with Active Interval Timer Interfaces for Simple Capacitive Sensors (2 pF to 6 pF) One Interface Can Be Configured for Motion Wake-up (3 pF to 5 pF) Typically 25 mbar ADC Resolution for Pressure Measurement with Dedicated Sensor Type Low-power Measurement Mode for Directly Connected Capacitive Sensors Typically 200 µA at 1 MHz System Clock Programmable 125 kHz Wake-up Receiver Channel with Typically 1.7 µA Current Consumption in Listing Mode 2V to 3.6V Operation Voltage for Single Li-cell Power Supply –40°C to +125°C Operation Temperature and –40°C to +150°C Storage Temperature Less then 10 External Passive Components QFN32 (5 mm × 5 mm) Package
TPMS Control and Transmitter IC ATA6285 ATA6286 Summary Preliminary
ATA6285 and ATA6286 are highly integrated smart RF micro transmitter ICs for 315 MHz and 433 MHz, suited for ASK and FSK with typically 20 Kbits/s data rate in Manchester mode. The devices combine the functionality of the RF transmitter ICs ATA5756/ATA5757 with the programmable low-power AVR 8-bit Flash microcontroller in a single QFN32 package (5 mm × 5 mm). The ATA6285 and ATA6286 include a dedicated ADC interface for simple capacitive sensors as well as an on-chip temperature sensor. Three sensor interfaces are available for a capacitive range of 2 pF to 16 pF, where one channel can be configured as motion wake-up in the range of 3 pF to 5 pF. The ICs are suited for use in tire pressure monitoring (TPMS) sensor gauges in combination with external sensor devices. The programmable AVR 8-bit Flash microcontroller includes 8 Kbytes of in-system self-programmable Flash memory and an 320-Bytes EEPROM, thus allowing the system integrator to install field-programmable firmware to enable system flexibility on different platforms. ATA6285 and ATA6286 can be configured to guarantee extremely low power consumption in sleep mode and measurement mode. They also include a programmable 125 kHz wake-up receiver channel for extremely low current consumption in listening mode. The ICs are designed for use in applications with typically less then 10 passive components: one external crystal for the sensor gauge, several capacitors, a single LiMnO2 battery coin cell, a single-ended antenna for the data transmission and an LF ferrite coil for the wake-up channel. ATA6285 and ATA6286 support TPMS-specific low-current modes even with an active brown-out detection and an interval timer.
NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office.
Tire Pressure Monitoring System (TPMS)
XZ Motion sensor
16 15 14 13 12 11 10 9 17 8 18 19 20 21 22 23 7 6
5 4 3 2
24 1 25 26 27 28 29 30 31 32
RF loop antenna ISP interface
In-System-Programmable Flash interface
Crystal Frequency 13.56 MHz for 433 MHz application Crystal Frequency 13.125 MHz for 315 MHz application
2.2 Block Diagram
ATA6285/ATA6286 Block Diagram (MCP)
PB3 (MOSI) PB4 (MISO) PB5 (SCK) PB7 (NSS)
LF1 LF2 LF Receiver 125 kHz SPI Oscillator Voltage monitor S0 S1 S2 Timer block Watchdog oscillator Sensor interface/ input multiplexer AVR Core Watchdog timer EEPROM
Clock management and monitoring
PC2 PC1 PC0
VCO Temperature sensor SRAM Flash Power Supervision POR/ BOD/ TSD and RESET
The ATA6285/ATA6286 are Smart RF Micro Transmitter ICs in MCP (Multi Chip Package) technology. Table 2-1 shows the internal assembly of the MCP.
AVR – Pin
Inter-die Connection Description of the MCP
ATA5756/ATA5757 – Pin EN – Enable input CLK – Clock output signal ASK – Input signal FSK – Input signal
PD3 (INT1) – External interrupt input 1 PD4 (ECIN1) – External clock input 1 PD5 (T2O1) – Timer2 modulator output 1 PD6 (T2O2) – Timer2 modulator output 2
PB2 (T2I) XTO2 PB7 (NSS) PB6 PB1 (T3O) ANT1 ANT2 PB5 (SCK) PB4 (MISO) 7 6 5 4 3 2 PB3 (MOSI) NRESET VSRF PD7 (SDIN) XTO1 PD2 (INTO) GND PB0 (T3ICP) GND GND
S1 S2 GND LF1 LF2 VCC PC2 PC1 PC0 18 19 20 21 22 23 PD0 (T2ICP)
16 15 14 13 12 11 10 9 8 17
S0 PD1 (T3I)
1 24 25 26 27 28 29 30 31 32 GND
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note:
Pin Name PB4 PB5 ANT2 ANT1 PB1 PB6 PB7 XT02 PB2 XT01 VS_RF GND NRESET GND S0 S1 S2 GND Alternate Function 1 MISO SCK – – T3O – NSS – T2I – – – debugWIRE – – – – – Alternate Function 2 PCINT4 PCINT5 – – PCINT1 PCINT6 PCINT7 – PCINT2 – – – – – – – – – SPI Switch for FSK modulation Timer2 external input clock Connection for crystal Power supply voltage for RF Power supply ground for RF Reset input/debugWIRE interface Power supply ground Sensor input 0 – Pressure Sensor (Cap.) Sensor input 1 – X – Motion Sensor (Cap.) Sensor input 2 – Z - Motion Sensor (Cap.) Power supply ground Function SPI SPI RF-antenna 2. Emitter of antenna output stage RF-antenna 1. Open collector antenna output Timer3 output Comment Port B4 Port B5 RF pin RF pin Port B1 Port B6 Port B7 RF pin Port B2 RF pin RF pin RF pin
1. Internal inter-die connection of the MCP
Pin Number 19 20 21 22 23 24 25 26 27 28 29 Inter-die(1) Inter-die(1) Inter-die(1) Inter-die(1) 30 31 32 Note:
Pin Description (Continued)
Pin Name LF1 LF2 VCC PC2 PC1 PC0 PD0 PD1 PB0 GND GND PD3 PD4 PD5 PD6 PD7 PD2 PB3 Alternate Function 1 – – – – CLKO ECIN0 T2ICP T3I T3ICP – – INT1 ECIN1 T2O1 T2O2 SDIN INT0 MOSI Alternate Function 2 – – – PCINT10 PCINT9 PCINT8 PCINT16 PCINT17 PCINT0 – – PCINT19 PCINT20 PCINT21 PCINT22 PCINT23 PCINT18 PCINT3 Function LF-receiver input 1 LF-receiver input 2 Power supply voltage (VCC + AVCC) System clock output External Clock input 0 Timer2 external input capture Timer3 external input clock Timer3 external input capture Power supply ground Power supply ground External Interrupt 1 → Inter-die connection External Clock input 1 → Inter-die connection Timer2 Modulator output 1 → Inter-die connection Timer2 Modulator output 2 → Inter-die connection SSI –Serial Data Input External interrupt input 0 SPI Port D2 Port D4 Port D5 Port D6 Port D7 Port D2 Port B3 Port C2 Port C1 Port C1 Port D0 Port D1 Port B0 Comment
1. Internal inter-die connection of the MCP
VCC Supply voltage
Port B (PB7..0) Port B is a 5(8)-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PB7, PB6 and PB2 ports are only used as internal I/O ports for inter-die connections. The Port B output buffers have symmetrical drive characteristics with both high sink and source current capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmegaT.
Port C (PC2..0) Port C is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source current capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..0) Port D is a 7(1)-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PD(6..3) pins are used as internal inter-die connection I/O ports. The Port D output buffers have symmetrical drive characteristics with both high sink and source current capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmegaT.
NRESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses then defined minimum pulse length are not guaranteed to generate a reset.
LF (2..1) Input coil pins for the LF-Receiver.
S (2..0) Measuring input pins for external capacitance sensor elements.
ANT(2, 1) RF-Antenna pins.
XTO(0, 1) External crystal for the internal RF transmitter IC.
3. Low Power AVR 8-bit Microcontroller
• High Performance, Extremely Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture
– 131 Powerful Instructions – 32 × 8 General Purpose Working Registers – Fully Static Operation – On-chip 2-cycle Multiplier Non-volatile Program and Data Memories – 8 Kbytes of In-system Self-programmable Flash – Optional Boot Code Section with Independent Lock Bits – 320 (256 + 64) Bytes EEPROM – 512 Bytes Internal SRAM – Programming Lock for Software Security Peripheral Features – Programmable Watchdog/Interval Timer with Separate, Internally Calibrated and Extremely Low-power Oscillator – Two 16-bit Timer/Counter with Compare Mode, Capture Mode, and On-chip Digital Data Modulator Circuitry – Integrated On-chip Temperature Sensor with Thermal Shutdown Function – Sensor Interface for External Pressure Sensor and XZ- Motion Sensor – Highly Sensitive 1D LF-receiver – Programmable Voltage Monitor – System Clock Management and Clock Monitoring – Master/Slave SPI Serial Interface – Integrated Debug-Wire-Interface – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Three Sleep Modes: Idle, Sensor Noise Reduction, and Power-down I/O and Package – 15 Programmable I/O Lines
The embedded core is an extremely low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AVR core achieves throughputs approaching 1 MIPS per MHz allowing the designer to optimize power consumption versus processing speed.
Figure 3-1. Microcontroller Block Diagram
Watchdog timer 0
Clock management and monitoring
Power Supervision POR/ BOD/ TSD and RESET
VCC GND RESET
debugWIRE AVR Core Program logic
AVCC 16 bit T/ C2 12 bit T1 Sensor value processing AGND Temperature sensor MUX and sensor input
16 bit T/ C3
PORT C (x)
PORT B (x)
PORT D (x)
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The embedded architecture provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 320 (256 + 64) bytes EEPROM, 512 bytes SRAM, 11(19) general purpose I/O lines, 32 general purpose working registers, On-chip Debugging support and programming, two flexible Timer/Counters with compare modes, internal and external interrupts, a sensor interface for external pressure sensor and Acceleration/Motion sensor, a programmable Watchdog Timer with internal calibrated Oscillator, an SPI serial port, and three software selectable power saving modes. The device is manufactured using Atmel®’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmegaT is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation Kits.
4. UHF ASK/FSK Transmitter for ATA6285/ATA6286
• PLL Transmitter IC with Single-ended Output • High output Power (6 dBm) at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Typical Values • Divide by 24 (ATA6285) and 32 (ATA6286) Blocks for 13 MHz Crystal Frequencies and for Low XTO
• Modulation Scheme ASK/FSK with Internal FSK Switch • Up to 20 Kbits/s Manchester Coding, Up to 40 Kbits/s NRZ Coding • Power-down Idle and Power-up Modes to Adjust Corresponding Current Consumption through
ASK/FSK/Enable Input Pins
• ENABLE Input for Parallel Usage of Controlling Pins in a 3-wire Bus System • CLK Output Switches ON if the Crystal Current Amplitude Has Reached 35% to 80% of its Final
• Crystal Oscillator Time until CLK Output Is Activated, Typically 0.6 ms
• Low Parasitic FSK Switch Integrated • Very Short and Reproducible Time to Transmit Typically < 0.85 ms • 13.125 MHz/13.56 MHz Crystals Give Opportunity for Small Package Sizes
The ATA6285/ATA6286 is a PLL transmitter part which has been developed for the demands of RF low-cost transmission systems at data rates up to 20 Kbits/s Manchester coding and 40 Kbits/s NRZ coding. The transmitting frequency range is 313 MHz to 317 MHz (ATA6285) and 432 MHz to 448 MHz (ATA6286), respectively. It can be used in both FSK and ASK systems. Due to its shorten crystal oscillator settling time it is well suited for Tire Pressure Monitoring (TPMS) and for Passive Entry Go applications.
1 Li cell
System Block Diagram
UHF ASK/FSK TPM Transmitter Part of ATA6285/ATA6286
UHF ASK/FSK Receiver
PLL Antenna VCO VCO Antenna
Digital Control Logic RF Receiver (LNA, Mixer, VCO, PLL, IF Filter, RSSI Amp., Demodulator) XTO
Power Supply Microcontroller Microcontroller Interface 4 to 8
4.4 General Description
This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmitters for TPM and RKE applications. The VCO is locked to 24 × f X T A L /32 x f X T A L f or ATA6285/ATA6286. Thus, a 13.125 MHz/13.56 MHz crystal is needed for a 315 MHz/ 433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal connected in series to GND are needed as external elements in an ASK system. The internal FSK switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter time will result. The CLK output is switched on if the amplitude of the current flowing through the crystal has reached 35% to 80% of its final value. This is synchronized with the 1.64 MHz/1.69 MHz CLK output. As a result, the first period of the CLK output is always a full period. The PLL is then locked < 250 µs after CLK output activation. This means an additional wait time of ≥ 250 µs is necessary before the PA can be switched on and the data transmission can start. This results in a significantly lower time of about 0.85 ms between enabling the ATA6285/ATA6286 and the beginning of the data transmission which saves battery power especially in tire pressure monitoring systems. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance and therefore the output power can be controlled via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency for the power amplifier results if an optimized load impedance of ZLoad, opt = 380Ω + j340Ω (ATA6285) at 315 MHz and ZLoad, opt = 280Ω + j310Ω (ATA6286) at 433.92 MHz is used at the 3V supply voltage.
If ASK = Low, FSK = Low and ENABLE = open or Low, the circuit is in power-down mode consuming only a very small amount of current so that a lithium cell used as power supply can work for many years. If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input pins. This means, the IC can be switched on by either the FSK of the ASK input. If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO and power amplifier are off and the microcontroller ports controlling the ASK and FSK inputs can be used to control other devices. This can help to save ports on the microcontroller in systems where other devices with 3-wire interface are used. With FSK = High and ASK = Low and ENABLE = open or High, the PLL and the XTO are switched on and the power amplifier is off. When the amplitude of the current through the crystal has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The CLK output stays Low until the CLK driver has been activated. The driver is activated synchronously with the CLK output frequency, hence, the first pulse on the CLK output is a complete period. The PLL is then locked within < 250 µs after the CLK driver has been activated, and the transmitter is then ready for data transmission.
With ASK = High the power amplifier is switched on. This is used to perform the ASK modulation. During ASK modulation the IC is enabled with the FSK or the ENABLE pin. With FSK = Low the switch at pin XTO2 is closed, with FSK = High the switch is open. To achieve a faster start-up of the crystal oscillator, the FSK pin should be High during start-up of the XTO because the series resistance of the resonator seen from pin XTO1 is lower if the switch is off. The different modes of the ATA6285/ATA6286 are listed in Table 4-1.
ASK Pin Low Low Low High High Low/High High
FSK Pin Low Low High Low High High Low/High ENABLE Pin Low/open High High/open High/open High/open Low Low Mode Power-down mode, FSK switch High Z Power-up, PA off, FSK switch Low Z Power-up, PA off, FSK switch High Z Power-up, PA on, FSK switch Low Z Power-up, PA on, FSK switch High Z Idle mode, FSK switch High Z Idle mode, FSK switch High Z
Transmission with ENABLE = Open ASK Mode The ATA6285/ATA6286 is activated by ENABLE = open, FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA6285/ATA6286 is switched to power-down mode with FSK = Low. Figure 4-2. Timing ASK Mode with ENABLE Open
∆TXTO FSK > 250 µs
Power-down Power-up, PA off Power-up, PA on (High) Power-up, PA off (Low) Power-down
188.8.131.52 FSK Mode The ATA6285/ATA6286 is activated by FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready. After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The ATA6285/ATA6286 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. After transmission, FSK stays High and ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA6285/ATA6286 is switched to power-down mode with FSK = Low. Figure 4-3. Timing FSK Mode with ENABLE Open
∆TXTO FSK > 250 µs
Power-down Power-up, PA off Power-up, Power-up, PA off PA on (fRF = High) (fRF = Low) Power-down
Transmission with ENABLE = High FSK Mode The ATA6285/ATA6286 is activated by ENABLE = High, FSK = High and ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The ATA6285/ATA6286 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA6285/ATA6286 is switched to power-down mode with ENABLE = Low and FSK = Low.
Timing FSK Mode with ENABLE Connected to the Microcontroller
∆TXTO > 250 µs
Power-down Power-up, PA off Power-up, Power-up, PA on PA off (fRF = High) (fRF = Low) Power-down
ASK Mode The ATA6285/ATA6286 is activated by ENABLE = High, FSK = High and ASK = Low. After activation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA6285/ATA6286 is switched to power-down mode with ENABLE = Low and FSK = Low. Figure 4-5. Timing ASK Mode with ENABLE Connected to the Microcontroller
∆TXTO > 250 µs
Power-down Power-up, PA off Power-up, PA on (High) Power-up, PA off (Low) Power-down
4.5.3 Accuracy of Frequency Deviation The accuracy of the frequency deviation using the XTAL pulling method is about ±20% if the following tolerances are considered. One important aspect is that the values of C0 and CM of typical crystals are strongly correlated which reduces the tolerance of the frequency deviation. Figure 4-6. Tolerances of Frequency Modulation
VS CStray XTAL CM LM RS C4
C0 Crystal equivalent circuit
Using a crystal with a motional capacitance of CM = 4.37 fF ±15%, a nominal load capacitance of CLNOM = 18 pF and a parallel capacitance of C 0 = 1.30 pF correlated with CM r esults in C0 = 297 × CM (the correlation has a tolerance of 10%, so C0 = 267 to 326 × CM). If using the internal FSK switch with CSwitch = 0.9 pF ±20% and estimated parasitics of CStray = 0.7 pF ±10%, the resulting C4 and C5 values are C4 = 10 pF ±1% and C5 = 15 pF ±1% for a nominal frequency deviation of ±19.3 kHz with worst case tolerances of ±15.8 kHz to ±23.2 kHz. 4.5.4 Accuracy of the Center Frequency The imaginary part of the impedance in large signal steady state oscillation IMXTO, seen into the pin 7 (XTO1), causes some additional frequency tolerances, due to pulling of the XTO oscillation frequency. These tolerances have to be added to the tolerances of the crystal itself (adjustment tolerance, temperature stability and ageing) and the influence to the center frequency due to tolerances of C4, C5, CSwitch and C Stray. The nominal value of IMXTO = 110Ω, C Switch and C Stray should be absorbed into the C4 and C5 values by using a crystal with known frequency and choosing C4 and C5, so that the XTO center frequency equals the crystal frequency, and the frequency deviation is as expected. Then, from the nominal value, the IMXTO has ±90Ω tolerances, using the pulling formula P = –IMXTO × CM × Pi × fXTO with fXTO = 13.56 MHz and CM = 4.4 fF an additional frequency tolerance of P = ±16.86 ppm results. If using crystals with other CM the additional frequency tolerance can be calculated in the same way. For example, a lower C M = 3.1 fF will reduce the frequency tolerance to 11.87 ppm, where a higher C M = 5.5 fF increases the tolerance to 21.07 ppm. CLK Output An output CLK signal of 1.64 MHz (ATA6285 operating at 315 MHz) and 1.69 MHz (ATA6286 operating at 433.92 MHz) is provided for a connected microcontroller. The delivered signal is CMOS-compatible with a High and Low time of >125 ns if the load capacitance is lower than 20 pF. The CLK output is Low in power-down mode due to an internal pull-down resistor. After enabling the PLL and XTO the signal stays Low until the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. Then, the CLK output is activated synchronously with its output signal so that the first period of the CLK output signal is a full period.
Clock Pulse Take-over by Microcontroller The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x microcontroller family provides the special feature of starting with an integrated RC oscillator to switch on the ATA6285/ATA6286 external clocking and to wait automatically until the CLK output of the ATA6285/ATA6286 is activated. After a time period of 250 µs the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of Z Load, opt = 3 80 Ω + j 340 Ω ( ATA6286) at 315 MHz and ZLoad, opt = 280Ω + j310Ω (ATA6285) at 433.92 MHz. A low resistive path to VS is required to deliver the DC current. The power amplifier delivers a current pulse and the maximum output power is delivered to a resistive load if the 0.66 pF output capacitance of the power amplifier is compensated by the load impedance. At the ANT1 pin, the RF output amplitude is about VS – 0.5V. The load impedance is defined as the impedance seen from the ATA6285’s ANT1, ANT2 into the matching network. Do not mix up this large-signal load impedance with a small-signal input impedance delivered as an input characteristic of RF amplifiers. The latter is measured from the application into the IC instead of from the IC into the application for a power amplifier. The 0.66 pF output capacitance absorbed into the load impedance a real impedance of 684Ω (ATA6285) at 315 MHz and 623Ω (ATA6286) at 433.92 MHz should be measured with a network analyses at pin 5 (ANT1) with the ATA6285/ATA6286 soldered, an optimized antenna connected and the power amplifier switched off. Less output power is achieved by lowering the real parallel part where the parallel imaginary part should be kept constant. Lowering the real part of the load impedance also reduces the supply voltage dependency of the output power. Output power measurement can be done with the circuit as shown in Output Power Measurement. Please note that the component values must be changed to compensate the individual board parasitics until the ATA6285/ATA6286 has the right load impedance. Also, the damping of the cable used to measure the output power must be calibrated. Figure 4-7. Output Power Measurement ATA6285/ATA6286
C1 = 1 nF L1 = 68 nH/ 39 nH ANT1 ZLopt ANT2 C2 = 2.2 pF/ 1.8 pF Z = 50Ω Rin 50Ω Power meter
5. Ordering Information
Extended Type Number ATA6285-PNPW ATA6286-PNPW ATA6285-PNQW ATA6286-PNQW Package QFN32 QFN32 QFN32 QFN32 Frequency 315 MHz 433 MHz 315 MHz 433 MHz MOQ Packaging unit: 1,500 Packaging unit: 1,500 6,000 6,000 Remarks Taped and reeled Taped and reeled Taped and reeled Taped and reeled
6. Package Information
Package: QFN_ 5 x 5_32L Exposed pad 3.6 x 3.6 Dimensions in mm Not indicated tolerances ±0.05 Top 32 1 Pin1 identification 24 25 32 1 Bottom 3.6±0.15
8 16 9 0.5 nom. 3.5
Drawing-No.: 6.543-5124.01-4 Issue: 1; 28.11.05 0.23±0.07
technical drawings according to DIN specifications
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