ATA6823_09

Features • PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors • A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge • Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS • 5V/3.3V Regulator and Current Limitation Function • Reset Derived From 5V/3.3V Regulator Output Voltage • Sleep Mode With Supply Current of Typically < 45 µA, Wake-up by Signal on Pins EN2 • • • • • • or on LIN Interface A Programmable Window Watchdog Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Warning and Protection (Shutdown) LIN 2.1 Compliant 3.3V/5V Regulator with Trimmed Band Gap QFN32 Package H-bridge Motor Driver ATA6823 1. Description The ATA6823 is designed for several body and powertrain applications. The IC is used to drive a continuous current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the IC by providing a PWM signal and a direction signal and allows the use of the IC in a motor-control application. The PWM control is performed by the low-side switch; the high-side switch is permanently on in the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and interface high level). The window watchdog has a programmable time, programmable by choosing a certain value of the external watchdog resistor RWD, internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.1 is integrated. 4856H–AUTO–07/09 Figure 1-1. Block Diagram M CP VRES CPLO Charge Pump CPIH RGATE H2 RGATE H1 S1 S2 RGATE L1 RGATE L2 PGND GND HS Driver 2 HS Driver 1 LS Driver 1 LS Driver 2 VBAT OT UV DG3 DG2 DG1 CC CC timer VG PBAT VBAT VINT 12V Regulator Supervisor OTP 12 bit OV Vint 5V Regulator Oscillator Logic Control WD timer EN2 CP VBAT VBG VBATSW VCC 5V Regulator LIN Bandgap VCC WD EN1 VCC VMODE /RESET DIR PWM RX TX LIN Battery Microcontroller 2 ATA6823 4856H–AUTO–07/09 ATA6823 2. Pin Configuration Figure 2-1. Pinning QFN32 EN2 VBATSW VBAT VCC PGND L1 L2 PBAT VMODE VINT RWD CC /RESET WD GND LIN 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6823 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 TX DIR PWM EN1 RX DG3 DG2 DG1 VG CPLO CPHI VRES H2 S2 H1 S1 Note: YWW ATA6823 ZZZZZ AL Date code (Y = Year - above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Description Symbol VMODE VINT RWD CC /RESET WD GND LIN TX DIR PWM EN1 RX DG3 DG2 DG1 S1 H1 S2 H2 VRES I/O I I/O I I/O O I I I/O I I I I O O O O I/O O I/O O I/O Function Selector for VCC and interface logic voltage level Blocking capacitor 220 nF/10V/X7R Resistor defining the watchdog interval RC combination to adjust cross conduction time Reset signal for microcontroller Watchdog trigger signal Ground for chip core LIN-bus terminal Transmit signal to LIN bus from microcontroller Defines the rotation direction for the motor PWM input controls motor speed Microcontroller output to keep the chip in Active mode Receive signal from LIN bus for microcontroller Diagnostic output 3 Diagnostic output 2 Diagnostic output 1 Source voltage H-bridge, high-side 1 Gate voltage H-bridge, high-side 1 Source voltage H-bridge, high-side 2 Gate voltage H-bridge, high-side 2 Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R 3 4856H–AUTO–07/09 Table 2-1. Pin 22 23 24 25 26 27 28 29 30 31 32 Pin Description (Continued) Symbol CPHI CPLO VG PBAT L2 L1 PGND VCC VBAT VBATSW EN2 I/O I O I/O I O O I O I O I Function Charge pump capacitor 220 nF/25V/X7R Blocking capacitor 470 nF/25V/X7R Power supply (after reverse protection) for charge pump and H-bridge Gate voltage H-bridge, low-side 2 Gate voltage H-bridge, low-side 1 Power ground for H-bridge and charge pump 5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7R Supply voltage for IC core (after reverse protection) 100Ω PMOS switch from VVBAT Enable input 4 ATA6823 4856H–AUTO–07/09 ATA6823 3. Functional Description 3.1 3.1.1 Power Supply Unit with Supervisor Functions Power Supply The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2). A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor provides the necessary low-voltage supply needed for the wake-up process. The low-power band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the internal regulator. Note: The internal supply voltage VINT must not be used for any other supply purpose! Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator. A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the voltage is too low. There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset going to sleep mode, VBATSW turns OFF. The signal can be used to switch on external voltage regulators, etc. 3.1.2 Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz. 3.1.3 Temperature Supervisor There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry and to protect the external NMOSFET transistors. In case of detected overtemperature (150°C), the diagnostic pin DG3 will be switched to “H” to signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (165°C), the VCC regulator and all drivers including the LIN transceiver will be switched OFF immediately and /RESET will go LOW. Both temperature thresholds are correlated. The absolute tolerance is ±10°C and there is a built-in hysteresis of about 10°C to avoid fast oscillations. After cooling down below the 155°C threshold; the IC will go into Active mode. The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically 165°C. 5 4856H–AUTO–07/09 3.2 Sleep Mode To be able to guarantee the low quiescent current of the inactive IC, a Sleep mode is established. In Sleep mode it is possible to wake-up the IC by using the pins EN2 or LIN. In Sleep mode, the following blocks are active: • Band gap • Internal 5V regulator (VINT) with external blocking capacitor of 220 nF • Input structure for detecting the EN2 pins threshold • Wake-up block of the LIN receive part 3.3 Wake-up and Sleep Mode Strategy The IC has two modes: Sleep and Active. The change between the modes is described below. The default state after power-on is Active mode. The wake-up procedure brings the IC from a standby mode (Sleep) to an active mode (Active). The internal 5V supply VINT, the EN2 pin input structure and a certain part of the LIN receiver are permanently active to ensure a proper startup of the system. The Go to Active and Go to Sleep procedures are implemented as follows: • Go to Active by activating pin EN2 The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists of a comparator with built-in hysteresis. It is ESD-protected by diodes against GND and VVBAT; for this reason the input voltage level must be positive and not higher than VVBAT. Pulling the EN2 pin up to the VVBAT level will drive the IC into Active mode. EN2 is debounced with a time constant of 20 µs, based on a 100 kHz clock. • Go to Active using the LIN interface The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode, the LIN receiver is partially active. The wake-up by LIN requires 2 steps: 1. If the voltage on pin LIN is below a value of V/DATwake (about VVBAT – 2V) the receive part of the LIN interface is active (not to be confused with Active mode of the whole IC). The active receive part is able to detect a valid LOW on the LIN pin. 2. If LIN = LOW during a filter time twakeLIN (typically 70 µs) the IC will change to Active mode. A short change back to HIGH during the filter time will reset the filter. This information is stored in a latch after entering Active mode If the change to Active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without disturbing the Active mode. • Stay in Active via EN1 The input EN1 is intended to keep the IC in Active Mode via a signal from the microcontroller. The input is ESD-protected by diodes against GND and VCC. Therefore, the input voltage must be positive and not higher than VCC. EN1 cannot be used to switch from Sleep to Active because the VCC regulator is off in the Sleep mode and VCC will be zero. • Go to Sleep A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time t gotosleep (typically 20 µs) switches the IC to Sleep mode. 6 ATA6823 4856H–AUTO–07/09 ATA6823 Figure 3-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the activated receive block of the LIN interface. After going to Active mode, the VCC regulator starts working. Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for longer than tdb) if EN1 was in a valid HIGH state (HIGH for longer than tdb) before. Figure 3-1. Wake-up by pin LIN Active Mode Sleep Mode Active Mode EN1 VCC LIN Tgotosleep = 20 µs Twakelin = 70 µs Regulator Wake-up Time 3.4 5V/3.3V VCC Regulator The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage. The output voltage accuracy is in general < ±3%; in the 5V mode with VVBAT < 9V it is limited to < 5%. To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 100 mA to 350 mA. The delivered voltage will break down and a reset may occur. Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink. A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low. 7 4856H–AUTO–07/09 Figure 3-2. Correlation between VCC Output Voltage and Reset Threshold 5.15V 4.9V VCC1 4.85V VtHRESH 4.1V VCC1-VtHRESH = VCC1 - VtHRESH The voltage difference between the regulated output voltage and the upper reset threshold voltage is higher than 75 mV (VMODE = HIGH) and higher than 50 mV (VMODE = LOW). 3.5 Reset and Watchdog Management The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external resistor RWD. The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time window of TWD. In order to save current consumption, the watchdog is switched off during Sleep mode. Figure 3-3. Timing Diagram of the Watchdog Function tres tresshort /RESET td t1 t2 t1 t2 td WD 3.5.1 Timing Sequence For example, with an external resistor RWD = 33 kΩ ±1% we get the following typical parameters of the watchdog. TOSC = 12.32 µs, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms ±10% The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%. 8 ATA6823 4856H–AUTO–07/09 ATA6823 After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the microcontroller for tres and wait td for the rising edge on WD. Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the time frame of t2 = 9.61 ms. The trigger event will restart the watchdog sequence. Figure 3-4. TWD versus RWD 60 50 max typ TWD (ms) 40 30 min 20 10 0 10 20 30 40 50 60 70 80 90 100 RWD (kΩ) If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence is similar to the power-on reset. The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can also vary by ±10%. The following calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide. t1min = 0.90 × t1 = 10.87 ms, t1max = 1.10 × t1 = 13.28 ms t2min = 0.90 × t2 = 8.65ms, t2max = 1.10 × t2 = 10.57 ms Twdmax = t1min + t2min = 10.87 ms + 8.65 ms = 19.52 ms Twdmin = t1max = 13.28 ms Twd = 16.42 ms ±3.15 ms (±19.1%) Figure 3-4 above shows the typical watchdog period TWD depending on the value of the external resistor ROSC. A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth). 9 4856H–AUTO–07/09 3.6 LIN Transceiver A bi-directional bus interface is implemented for data transfer between the LIN bus and the local LIN protocol controller. The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. 3.6.1 Transmit Mode During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin LIN. To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping unit. Transmission will be interrupted in the following cases: • Thermal shutdown active or overtemperature LIN active • Sleep mode Figure 3-5. Definition of Bus Timing Parameters tBit TX (input to transmitting Node) tBit tBit tBus_dom(max) tBus_rec(min) THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min) Thresholds of receiving node 1 Thresholds of receiving node 2 tBus_dom(min) RX (output of receiving Node 1) tBus_rec(max) trx_pdf(1) RX (output of receiving Node 2) trx_pdr(1) trx_pdr(2) trx_pdf(2) 10 ATA6823 4856H–AUTO–07/09 ATA6823 The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an active diode. This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP). No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC is used for LIN master nodes, it is necessary that the BUS pin be terminated via an external 1 kΩ resistor in series with a diode to VBAT. 3.6.2 TXD Dominant Time-out Function The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced low longer than tdom > 18.4 ms, the pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (> 10 µs) before switching LIN to dominant again. 3.7 3.7.1 Control Inputs EN1, EN2, DIR, PWM Pins EN1, EN2 Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2 can withstand a voltage up to 40V. Internal pull-down resistors are included. 3.7.2 Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included. 3.7.3 Pin PWM Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included. Table 3-1. ON 0 1 1 DIR X 0 1 Status of the IC Depending on Control Inputs and Detected Failures Driver Stage for External Power MOS H1 OFF ON /PWM L1 OFF OFF PWM H2 OFF /PWM ON L2 OFF PWM OFF Standby mode Motor PWM forward Motor PWM reverse X PWM PWM Comments PWM Control Inputs The internal signal ON is high when • At least one valid trigger has been accepted (SYNC = 1) • VVBAT is inside the specified range (UV = 0 and nOV = 1) • The charge pump has reached its minimum voltage (CPOK = 1) and • The device is not overheated (OT2 = 0) In case of a short circuit, the appropriate transistor is switched off after a debounce time of about 10 µs. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination. 11 4856H–AUTO–07/09 Table 3-2. CPOK 0 X X X X Note: Status of the Diagnostic Outputs Device Status OT1 X 1 X X OV X X 1 X UV X X X 1 SC X X X X Diagnostic Outputs DG1 – – – – DG2 1 – 1 1 – DG3 – 1 – – – Charge pump failure Overtemperature warning Overvoltage Undervoltage Short circuit Comments X X X 1 1 X represents: don't care – no effect) OT1: Overtemperature warning OV: Overvoltage of VBAT UV: Undervoltage of VBAT SC: Short circuit CPOK: Charge pump OK In order to be able to distinguish between a wake-up from LIN or from EN2, the source of wake-up is flagged in DG1 until the first valid trigger (LIN = 0, EN2 = 1). 3.8 VG Regulator The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V. 3.9 Charge Pump The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the output voltage on the reservoir capacitor is VVBAT plus VG. The charge pump is clocked with a dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC level. 3.10 Thermal Shutdown There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at 150°C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature 165°C the VCC regulator will be switched off and a reset occurs. 3.11 H-bridge Driver The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS. The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the forward and reverse direction (see Table 3-1 on page 11). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in both directions. 12 ATA6823 4856H–AUTO–07/09 ATA6823 3.11.1 Cross Conduction Time To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in the following way: tCC (µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15 µs) The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level. The resistor RCC must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the CCC value has to be ≤ 5 nF. Use of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50% level. Figure 3-6. Timing of the Drivers PWM or DIR 50% t tLxHL tLxf tLxLH tLxr 80% Lx 20% tCC t tHxLH tHxr tHxHL tHxf tCC 80% Hx 20% t The delays tHxLH and tLxLH include the cross conduction time tCC. 13 4856H–AUTO–07/09 3.12 Short Circuit Detection To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time > tSC (typically 10 µs) the signal SC (short circuit) will be set and the drivers will be switched off immediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, the bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on again. There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time > tSC the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared as above. 14 ATA6823 4856H–AUTO–07/09 ATA6823 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description Pin Name Min. Max. Unit Ground GND 0 0 V Power ground PGND –0.3 +0.3 V Reverse protected battery voltage VBAT –0.3 +40 V Reverse protected battery voltage PBAT –0.3 +40 V V Digital output /RESET –0.3 VVCC + 0.3 V Digital output DG1, DG2, DG3 –0.3 VVCC + 0.3 4.9V output, external blocking capacitor VINT –0.3 +5.5 V Cross conduction time capacitor/resistor CC –0.3 VVINT + 0.3 V combination Digital input coming from microcontroller WD –0.3 VVINT + 0.3 V V Watchdog timing resistor RWD –0.3 VVCC + 0.3 Digital input direction control DIR –0.3 VVCC + 0.3 V V Digital input PWM control + Test mode PWM –0.3 VVCC + 0.3 + 0.3 V Digital input for enable control EN1 –0.3 VVCC Digital input for enable control EN2 –0.3 VVBAT + 0.3 V 5V regulator output VCC –0.3 +5.5 V V Digital input VMODE –0.3 VVINT + 0.3 12V output, external blocking capacitor VG –0.3 +16 V V Digital output RX –0.3 VVCC + 0.3 V Digital input TX –0.3 VVCC + 0.3 VVBAT + 2 V LIN data pin LIN –27(1) Source external high-side NMOS S1, S2 –2 +40(3) V VVG + 0.3 V Gates external low-side NMOS L1, L2 VPGND – 0.3 VSx + 16(2) V Gates of external high-side NMOS H1, H2 VSx – 1(2) Charge pump CPLO –0.3 VPBAT + 0.3 V V Charge pump CPHI –0.3 VVRES + 0.3 (4) V Charge pump output VRES –0.3 +40 V Switched VBAT VBATSW –0.3 VVBAT + 0.3 –40 +150 °C Storage temperature ϑ STORE Notes: 1. For VVBAT ≤ 13.5V 2. x = 1.2 3. t < 0.5s 4. Load dump of t < 0.5s tolerated 5. Thermal Resistance Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient when heat slug is soldered to PCB(1) Note: Symbol Rthjc Rthja Value VTHOV 7 –40 150 165 Max. VTHOV VTHUV