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ATA8202-PXQW - UHF ASK/FSK Receiver - ATMEL Corporation

型  号:
ATA8202-PXQW
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674.44KB 共44页
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ATMEL[ATMELCorporation]
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http://www.atmel.com/
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ATA8202-PXQW - UHF ASK/FSK Receiver - ATMEL Corporation
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Features • Transparent RF Receiver ICs for 315 MHz (ATA8201) and 433.92 MHz (ATA8202) With High Receiving Sensitivity • Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter • High FSK/ASK Sensitivity:–105 dBm (ATA8201, FSK, 9.6 Kbits/s, Manchester, BER 10-3) –114 dBm (ATA8201, ASK, 2.4 Kbits/s, Manchester, BER 10-3) –104 dBm (ATA8202, FSK, 9.6 Kbits/s, Manchester, BER 10-3) –113 dBm (ATA8202, ASK, 2.4 Kbits/s, Manchester, BER 10-3) Supply Current: 6.5 mA in Active Mode (3V, 25°C, ASK Mode) Data Rate: 1 Kbit/s to 10 Kbits/s Manchester ASK, 1 Kbit/s to 20 Kbits/s Manchester FSK With Four Programmable Bit Rate Ranges Switching Between Modulation Types ASK/FSK and Different Data Rates Possible in ≤ 1 ms Typically, Without Hardware Modification on Board to Allow Different Modulation Schemes Low Standby Current: 50 µA at 3V, 25°C ASK/FSK Receiver Uses a Low-IF Architecture With High Selectivity, Blocking, and Low Intermodulation (Typical 3-dB Blocking 68.0 dBC at ±3 MHz/74.0 dBC at ±20.0 MHz, System I1dBCP = –31 dBm/System IIP3 = –24 dBm) Telegram Pause Up to 52 ms Supported in ASK Mode Wide Bandwidth AGC to Handle Large Out-of-band Blockers above the System I1dBCP 440-kHz IF Frequency With 30-dB Image Rejection and 420-kHz IF Bandwidth to Support PLL Transmitters With Standard Crystals or SAW-based Transmitters RSSI (Received Signal Strength Indicator) With Output Signal Dynamic Range of 65 dB Low In-band Sensitivity Change of Typically ±2.0 dB Within ±160-kHz Center Frequency Change in the Complete Temperature and Supply Voltage Range Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer Fast and Stable XTO Start-up Circuit (> –1.4 kΩ Worst-case Start Impedance) Clock Generation for Microcontroller ESD Protection at all Pins (±4 kV HBM, ±200V MM, ±500V FCDM) Dual Supply Voltage Range: 2.7V to 3.3V or 4.5V to 5.5V Temperature Range: –40°C to +85°C Small 5 mm × 5 mm QFN24 Package • • • UHF ASK/FSK Receiver ATA8201 ATA8202 • • • • • • • • • • • • • • Applications • • • • • • • Industrial/Aftermarket Keyless Entry and Tire Pressure Monitoring Systems Alarm, Telemetering and Energy Metering Systems Remote Control Systems for Consumer and Industrial Markets Access Control Systems Home Automation Home Entertainment Toys 4971C–INDCO–04/09 Benefits • Supports Header and Blanking Periods of Protocols Common in RKE and TPM Systems (Up to 52 ms in ASK Mode) • All RF Relevant Functions are Integrated. The Single-ended RF Input is Suited for Easy • • • • Adaptation to λ / 4 or Printed-loop Antennas Allows a Low-cost Application With Only 8 Passive Components Optimal Bandwidth Maximizes Sensitivity while Maintaining SAW Transmitter Compatibility Clock Output Provides an External Microcontroller Crystal-precision Time Reference Well Suited for Use With PLL Transmitter ATA8401/ATA8402/ATA8403/ATA8404/ATA8405 2 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 1. General Description The ATA8201/ATA8202 is a UHF ASK/FSK transparent receiver IC with low power consumption supplied in a small QFN24 package (body 5 mm × 5 mm, pitch 0.65 mm). ATA8202 is used in the 433 MHz to 435 MHz band of operation, and ATA8201 in 313 MHz to 317 MHz. For improved image rejection and selectivity, the IF frequency is fixed to 440 kHz. The IF block uses an 8th-order band pass yielding a receive bandwidth of 420 kHz. This enables the use of the receiver in both SAW- and PLL-based transmitter systems utilizing various types of data-bit encoding such as pulse width modulation, Manchester modulation, variable pulse modulation, pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq® are easily supported due to the receiver’s ability to hold the current data slicer threshold for up to 52 ms when incoming RF telegrams contain a blanking interval. This feature eliminates erroneous noise from appearing on the demodulated data output pin, and simplifies software decoding algorithms. The decoding of the data stream must be carried out by a connected microcontroller device. Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching. ATA8201 and ATA8202 support Manchester bit rates of 1 Kbit/s to 10 Kbits/s in ASK and 1 Kbit/s to 20 Kbits/s in FSK mode. The four discrete bit rate passbands are selectable and cover 1.0 Kbit/s to 2.5 Kbits/s, 2.0 Kbits/s to 5.0 Kbits/s, 4.0 Kbits/s to 10.0 Kbits/s, and 8.0 Kbits/s to 10.0 Kbits/s or 20.0 Kbits/s (for ASK or FSK, respectively). The receiver contains an RSSI output to provide an indication of received signal strength and a SENSE input to allow the customer to select a threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are selected by the connected microcontroller device via pins ASK_NFSK, BR0, and BR1. Figure 1-1. System Block Diagram ATA8201/ATA8202 Digital Control Logic Power Supply Antenna RF Receiver (LNA, Mixer, VCO, PLL, IF Filter, RSSI Amp., Demodulator) Microcontroller 4 ... 8 Microcontroller Interface XTO 3 4971C–INDCO–04/09 Figure 1-2. Pinning QFN24 ASK_NFSK DATA_OUT CDEM BR1 BR0 TEST2 TEST1 CLK_OUT CLK_OUT_CTRL1 CLK_OUT_CTRL0 ENABLE 1 2 3 4 5 6 24 23 22 21 20 19 18 17 16 15 14 7 8 13 9 10 11 12 RX TEST3 RSSI SENSE_CTRL SENSE LNA_IN LNA_GND GND DVCC Table 1-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Description Symbol TEST2 TEST1 CLK_OUT CLK_OUT_CTRL1 CLK_OUT_CTRL0 ENABLE XTAL2 XTAL1 DVCC VS5V VS3V_AVCC GND LNA_GND LNA_IN SENSE SENSE_CTRL RSSI TEST3 RX BR0 BR1 ASK_NFSK CDEM DATA_OUT GND Function Test pin, during operation at GND Test pin, during operation at GND Output to clock a connected microcontroller Input to control CLK_OUT (MSB) Input to control CLK_OUT (LSB) Input to enable the XTO Reference crystal Reference crystal Digital voltage supply blocking Power supply input for voltage range 4.5V to 5.5V Power supply input for voltage range 2.7V to 3.3V Ground RF ground RF input Sensitivity control resistor Sensitivity selection Low: Normal sensitivity, High: Reduced sensitivity Output of the RSSI amplifier Test pin, during operation at GND Input to activate the receiver Bit rate selection, LSB Bit rate selection, MSB FSK/ASK selection Low: FSK, High: ASK Capacitor to adjust the lower cut-off frequency data filter Data output Ground/backplane (exposed die pad) 4 ATA8201/ATA8202 4971C–INDCO–04/09 VS3V_AVCC XTAL2 XTAL1 VS5V ATA8201/ATA8202 Figure 1-3. Block Diagram ASK FSK ASK/FSK Control IF Amp SENSE SENSE_CTRL IF Filter GND LPF Standby Logic Control RX Data Slicer CDEM ASK/FSK Demodulator Power Supply VS3V_AVCC VS5V ASK_NFSK DATA_OUT BR0 BR1 DVCC IF Amp XTO Div. by 3, 6, 12 CLK_OUT_CTRL1 CLK_OUT_CTRL0 CLK_OUT RSSI LPF LNA_IN LNA_GND PLL (/24, /32) XTO ENABLE TEST1 LNA VCO TEST2 TEST3 XTAL2 XTAL1 5 4971C–INDCO–04/09 2. RF Receiver As seen in Figure 1-3 on page 5, the RF receiver consists of a low-noise amplifier (LNA), a local oscillator, and the signal processing part with mixer, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter, and data slicer. In receive mode, the LNA pre-amplifies the received signal which is converted down to a 440-kHz intermediate frequency (IF), then filtered and amplified before it is fed into an FSK/ASK demodulator, data filter, and data slicer. The received signal strength indicator (RSSI) signal is available at the pin RSSI. 2.1 Low-IF Receiver The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking, selectivity, supply voltage, and supply current specification needed to design, e.g., an industrial/ aftermarket integrated receiver for RKE and TPM systems. A benefit of the integrated receive filter is that no external components needed. At 315 MHz, the ATA8201 receiver (433.92 MHz for the ATA8202 receiver) has a typical system noise figure of 6.0 dB (7.0 dB), a system I1dBCP of –31 dBm (–30 dBm), and a system IIP3 of –24 dBm (–23 dBm). The signal path is linear for out-of-band disturbers up to the I1dBCP and hence there is no AGC or switching of the LNA needed, and a better blocking performance is achieved. This receiver uses an IF (intermediate frequency) of 440 kHz, the typical image rejection is 30 dB and the typical 3-dB IF filter bandwidth is 420 kHz (f IF = 440 kHz ± 210 kHz, flo_IF = 230 kHz and fhi_IF = 650 kHz). The demodulator needs a signal-to-noise ratio of 8.5 dB for 10 Kbits/s Manchester with ±38 kHz frequency deviation in FSK mode, thus, the resulting sensitivity at 315 MHz (433.92 MHz) is typically –105 dBm (–104 dBm). Due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated IF filter, the receiver has a better selectivity and blocking performance than more complex double superhet receivers, without using external components and without numerous spurious receiving frequencies. A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct conversion receivers where every pulse or amplitude modulated signal (especially the signals from TDMA systems like GSM) demodulates to the receiving signal band at second-order non-linearities. 6 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 2.2 Input Matching at LNA_IN The measured input impedances as well as the values of a parallel equivalent circuit of these impedances can be seen in Table 2-1. The highest sensitivity is achieved with power matching of these impedances to the source impedance. Table 2-1. Measured Input Impedances of the LNA_IN Pin fRF [MHz] 315 433.92 ZIn(RF_IN) [Ω] (72.4 – j298) (55 – j216) RIn_p//CIn_p [pF] 1300Ω//1.60 900Ω//1.60 The matching of the LNA input to 50Ω is done using the circuit shown in Figure 2-1 and the values of the matching elements given in Table 2-2. The reflection coefficients were always ≤ –10 dB. Note that value changes of C1 and L1 may be necessary to compensate individual board layout parasitics. The measured typical FSK and ASK Manchester-code sensitivities with a bit error rate (BER) of 10–3 are shown in Table 2-3 and Table 2-4 on page 8. These measurements were done with wire-wound inductors having quality factors reported in Table 2-2, resulting in estimated matching losses of 0.8 dB at 315 MHz and 433.92 MHz. These losses can be estimated when calculating the parallel equivalent resistance of the inductor with Rloss = 2 × π × f × L × QL and the matching loss with 10 log(1+RIn_p / Rloss). Figure 2-1. Input Matching to 50Ω RFIN C1 ATA8201/ATA8202 14 LNA_IN L1 Table 2-2. 315 Input Matching to 50Ω C1 [pF] 2.2 2.2 L1 [nH] 68 36 QL1 20 15 fRF [MHz] 433.92 7 4971C–INDCO–04/09 Table 2-3. Measured Typical Sensitivity FSK, ±38 kHz, Manchester, BER = 10–3 BR_Range_0 1.0 Kbit/s –108 dBm –107 dBm BR_Range_0 2.5 Kbits/s –108 dBm –107 dBm BR_Range_1 5 Kbits/s –107 dBm –106 dBm BR_Range_2 10 Kbits/s –105 dBm –104 dBm BR_Range_3 10 Kbits/s –104 dBm –103 dBm BR_Range_3 20 Kbits/s –104 dBm –103 dBm RF Frequency 315 MHz 433.92 MHz Table 2-4. Measured Typical Sensitivity 100% ASK, Manchester, BER = 10–3 BR_Range_0 1.0 Kbit/s –114 dBm –113 dBm BR_Range_0 2.5 Kbits/s –114 dBm –113 dBm BR_Range_1 5 Kbits/s –113 dBm –112 dBm BR_Range_2 10 Kbits/s –111 dBm –110 dBm BR_Range_3 10 Kbits/s –109 dBm –108 dBm RF Frequency 315 MHz 433.92 MHz Conditions for the sensitivity measurement: The given sensitivity values are valid for Manchester-modulated signals. For the sensitivity measurement the distance from edge to edge must be evaluated. As can be seen in Figure 6-1 on page 25, in a Manchester-modulated data stream, the time segments TEE and 2 × TEE occur. To reach the specified sensitivity for the evaluation of TEE and 2 × TEE in the data stream, the following limits should be used (TEE min, TEE max, 2 × TEE min, 2 × TEE max). Table 2-5. Bit Rate 1.0 Kbit/s 2.4 Kbits/s 5.0 Kbits/s 9.6 Kbits/s Limits for Sensitivity Measurements TEE Min 260 µs 110 µs 55 µs 27 µs TEE Typ 500 µs 208 µs 100 µs 52 µs TEE Max 790 µs 310 µs 155 µs 78 µs 2 × TEE Min 800 µs 320 µs 160 µs 81 µs 2 × TEE Typ 1000 µs 416 µs 200 µs 104 µs 2 × TEE Max 1340 µs 525 µs 260 µs 131 µs 2.3 Sensitivity Versus Supply Voltage, Temperature and Frequency Offset To calculate the behavior of a transmission system, it is important to know the reduction of the sensitivity due to several influences. The most important are frequency offset due to crystal oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage dependency of the noise figure, and IF-filter bandwidth of the receiver. Figure 2-2 and Figure 2-3 on page 9 show the typical sensitivity at 315 MHz, ASK, 2.4 Kbits/s and 9.6 Kbits/s, Manchester, Figure 2-4 and Figure 2-5 on page 10 show a typical sensitivity at 315 MHz, FSK, 2.4 Kbits/s and 9.6 Kbits/s, ±38 kHz, Manchester versus the frequency offset between transmitter and receiver at Tamb = +25°C and supply voltage VS = VS3V_AVCC = VS5V = 3.0V. 8 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 Figure 2-2. Measured Sensitivity (315 MHz, ASK, 2.4 Kbits/s, Manchester) Versus Frequency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA8201, ASK, 2.4 kB/s (Manchester), BR = 0 -118.00 -117.00 Input Sensitivity (dBm) -116.00 -115.00 -114.00 -113.00 -112.00 -111.00 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -300 3.0V/25˚C -200 -100 0 100 200 300 delta RF (kHz) at 315 MHz Figure 2-3. Measured Sensitivity (315 MHz, ASK, 9.6 Kbits/s, Manchester) Versus Frequency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA8201, ASK, 9.6 Kbits/s (Manchester), BR = 2 -115.0 0 -114.0 0 Input Sensitivity (dBm) -113.0 0 -112.0 0 -111.0 0 -110.0 0 -10 9.0 0 -10 8.0 0 -10 7.0 0 -10 6.0 0 -10 5.0 0 -10 4.0 0 -10 3.0 0 -10 2.00 -10 1.0 0 -10 0.0 0 -300 -200 3.0V/25˚C -100 0 100 200 300 delta RF (kHz) at 315 MHz 9 4971C–INDCO–04/09 Figure 2-4. Measured Sensitivity (315 MHz, FSK, 2.4 Kbits/s, ±38 kHz, Manchester) Versus Frequency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 2.4 Kbits/s (Manchester), BR0 -112.00 Input Sensitivity (dBm) -111.00 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -102.00 -101.00 -100.00 -99.00 -98.00 -300 3.0V/25˚C -200 -100 0 100 200 300 delta RF (kHz) at 315 MHz Figure 2-5. Measured Sensitivity (315 MHz, FSK, 9.6 Kbits/s, ±38 kHz, Manchester) Versus Frequency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 9.6 Kbits/s (Manchester), BR = 2 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -102.00 -101.00 -100.00 -99.00 -98.00 -97.00 -96.00 -95.00 -300 -200 -100 0 100 200 300 Input Sensitivity (dBm) 3.0V/25˚C delta RF (kHz) at 315 MHz 10 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 As can be seen in Figure 2-5 on page 10, the supply voltage has almost no influence. The temperature has an influence of about ±1.0 dB, and a frequency offset of ±160 kHz also influences by about ±1 dB. All these influences, combined with the sensitivity of a typical IC (–105 dB), are then within a range of –103.0 dBm and –107.0 dBm over temperature, supply voltage, and frequency offset. The integrated IF filter has an additional production tolerance of ±10 kHz, hence, a frequency offset between the receiver and the transmitter of ±160 kHz can be accepted for XTAL and XTO tolerances. Note: For the demodulator used in the ATA8201/ATA8202, the tolerable frequency offset does not change with the data frequency. Hence, the value of ±160 kHz is valid for 1 Kbit/s to 10 Kbits/s. This small sensitivity change over supply voltage, frequency offset, and temperature is very unusual in such a receiver. It is achieved by an internal, very fast, and automatic frequency correction in the FSK demodulator after the IF filter, which leads to a higher system margin. This frequency correction tracks the input frequency very quickly. If, however, the input frequency makes a larger step (for example, if the system changes between different communication partners), the receiver has to be restarted. This can be done by switching back to Standby mode and then again to Active mode (pin RX 1 →0 →1) or by generating a positive pulse on pin ASK_NFSK (0 →1 →0). 2.4 RX Supply Current Versus Temperature and Supply Voltage Table 2-7 shows the typical supply current of the receiver in Active mode versus supply voltage and temperature with VS = VS3V_AVCC = VS5V. Table 2-6. Measured Current in Active Mode ASK VS = VS3V_AVCC = VS5V 3.0V 6.5 mA Tamb = 25°C Table 2-7. Measured Current in Active Mode FSK VS = VS3V_AVCC = VS5V 3.0V 6.7 mA Tamb = 25°C 11 4971C–INDCO–04/09 2.5 Blocking, Selectivity As can be seen in Figure 2-6 on page 12, and Figure 2-7 and Figure 2-8 on page 13, the receiver can receive signals 3 dB higher than the sensitivity level in the presence of large blockers of –34.5 dBm or –28 dBm with small frequency offsets of ±3 MHz or ±20 MHz. Figure 2-6, and Figure 2-7 on page 12 show the narrow-band blocking, and Figure 2-8 on page 13 shows the wide-band blocking characteristic. The measurements were done with a useful signal of 315 MHz, FSK, 10 Kbits/s, ±38 kHz, Manchester, BR_Range2 with a level of –105 dBm + 3 dB = –102 dBm, which is 3 dB above the sensitivity level. The figures show how much larger than –102 dBm a continuous wave signal can be, until the BER is higher than 10–3. The measurements were done at the 50Ω input shown in Figure 2-1 on page 7. At 3 MHz, for example, the blocker can be 67.5 dBC higher than –102 dBm, or –102 dBm + 67.5 dBC = –34.5 dBm. Figure 2-6. Close-in 3-dB Blocking Characteristic and Image Response at 315 MHz 70.0 60.0 Blocking Level (dBC) 50.0 40.0 30.0 20.0 10.0 0.0 - 10.0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Distance from Interfering t o Receiving Signal (MHz) Figure 2-7. Narrow-band 3-dB Blocking Characteristic at 315 MHz 80.0 70.0 Blocking Level (dBC) 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 Distance from Interfering to Receiving Signal (MHz) 12 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 Figure 2-8. Wide-band 3-dB Blocking Characteristic at 315 MHz 80.0 70.0 Blocking Level (dBC) 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 Distance from Interfering to Receiving Signal (MHz) Table 2-8 shows the blocking performance measured relative to –102 dBm for some frequencies. Note that sometimes the blocking is measured relative to the sensitivity level 104 dBm (denoted dBS), instead of the carrier –102 dBm (denoted dBC). Blocking 3 dB Above Sensitivity Level With BER < 10–3 Blocking Level –44.5 dBm –44.5 dBm –39.0 dBm –36.0 dBm –34.5 dBm –34.5 dBm –28.0 dBm –28.0 dBm Blocking 57.5 dBC, 60.5 dBS 57.5 dBC, 60.5 dBS 63 dBC, 66 dBS 66 dBC, 69 dBS 67.5 dBC, 70.5 dBS 67.5 dBC, 70.5 dBS 74 dBC, 77 dBS 74 dBC, 77 dBS Table 2-8. Frequency Offset +1.5 MHz –1.5 MHz +2 MHz –2 MHz +3 MHz –3 MHz +20 MHz –20 MHz The ATA8201/ATA8202 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals at –10 dBm. This is often referred to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is 95 dB for 10 Kbits/s Manchester (FSK). This value is useful if the transmitter and receiver are very close to each other. 13 4971C–INDCO–04/09 2.6 In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer If a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the performance of a receiver strongly depends on the circuits after the IF filter. Hence, the demodulator, data filter, and data slicer are important. The data filter of the ATA8201/ATA8202 functions also as a quasi-peak detector. This results in a good suppression of above mentioned disturbers and exhibits a good carrier-to-noise performance. The required useful-signal-to-disturbing-signal ratio, at a BER of 10–3, is less than 14 dB in ASK mode and less than 3 dB (BR_Range_0 to BR_Range_2) and 6 dB (BR_Range_3) in FSK mode. Due to the many different possible waveforms, these numbers are measured for the signal, as well as for disturbers, with peak amplitude values. Note that these values are worst-case values and are valid for any type of modulation and modulating frequency of the disturbing signal, as well as for the receiving signal. For many combinations, lower carrier-to-disturbing-signal ratios are needed. 2.7 RSSI Output The output voltage of the pin RSSI is an analog voltage, proportional to the input power level. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable dynamic range of the RSSI amplifier is 65 dB, the input power range P(RFIN) is –110 dBm to –45 dBm, and the gain is 15 mV/dB. Figure 2-9 shows the RSSI characteristic of a typical device at 315 MHz with VS3V_AVCC = VS5V = 3V and Tamb = 25°C with a matched input as shown in Table 2-2 and Figure 2-1 on page 7. At 433.92 MHz, 1 dB more signal level is needed for the same RSSI results. Figure 2-9. Typical RSSI Characteristic at 315 MHz Versus Temperature and Supply Voltage 1.7 1.6 1.5 1.4 1.3 V_RSSI (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -13 0 -12 0 -110 -10 0 -9 0 -8 0 -70 -6 0 -50 -4 0 -3 0 -2 0 -10 min: -9 dBm max: +9 dBm 3V, 25˚C Pin (dBm) As can be seen in Figure 2-9 on page 14, for single devices there is a variance over temperature and supply voltage range of ±3 dB. The total variance over production, temperature, and supply voltage range is ±9 dB. 14 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 2.8 Frequency Synthesizer The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is divided by the factor 24 (ATA8201) or 32 (ATA8202). The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to the fully integrated loop filter, and thereby generates the control voltage for the VCO. By means of that configuration, the VCO is controlled in a way, such that fLO / 24 (fLO / 32) is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO / 24 (fXTO = fLO / 32). The synthesizer has a phase noise of –130 dBC/Hz at 3 MHz and spurs of –75 dBC. Care must be taken with the harmonics of the CLK output signal, as well as with the harmonics produced by a microprocessor clocked using the signal, as these harmonics can disturb the reception of signals. 3. XTO The XTO is an amplitude-regulated Pierce oscillator type with external load capacitances (2 × 16 pF). Due to additional internal and board parasitics (CP) of approximately 2 pF on each side, the load capacitance amounts to 2 × 18 pF (9 pF total). The XTO oscillation frequency fXTO is the reference frequency for the integer-N synthesizer. When designing the system in terms of receiving and transmitting frequency offset, the accuracy of the crystal and XTO have to be considered. The XTO’s additional pulling (including the RM tolerance) is only ±5 ppm. The XTAL versus temperature, aging, and tolerances is then the main source of frequency error in the local oscillator. The XTO frequency depends on XTAL properties and the load capacitances CL1,2 at pin XTAL1 and XTAL2. The pulling (p) of fXTO from the nominal fXTAL is calculated using the following formula: Cm C LN – C L -6 p = ------- × --------------------------------------------------------------- × 10 ppm 2 ( C O + C LN ) × ( C O + C L ) Cm, the crystal’s motional capacitance; C0, the shunt capacitance; and CLN, the nominal load capacitance of the XTAL, are found in the datasheet. CL is the total actual load capacitance of the crystal in the circuit, and consists of CL1 and CL2 connected in series. Figure 3-1. Crystal Equivalent Circuit Crystal Equivalent Circuit XTAL C0 Lm CL1 CL2 Cm Rm CL = CL1 × CL2/ (CL1 + CL2) 15 4971C–INDCO–04/09 W ith C m ≤ 10 fF, C 0 ≥ 1.0 pF, C LN = 9 pF and C L1,2 = 16 pF ±1%, the pulling amounts to P ≤ ±1 ppm. The C0 of the XTAL has to be lower than CLmin / 2 = 7.9 pF for a Pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is risk of an unstable oscillation. To ensure proper start-up behavior, the small signal gain and the negative resistance provided by this XTO at start is very large. For example, oscillation starts up even in the worst case with a crystal series resistance of 1.5 kΩ at C0 ≤ 2.2 pF with this XTO. The negative resistance is approximately given by ⎧ Z 1 × Z 3 + Z 2 × Z 3 + Z 1 × Z 3 × gm ⎫ Re { Zxtocore } = Re ⎨ ---------------------------------------------------------------------------------------- ⎬ ⎩ Z 1 + Z 2 + Z 3 + Z 1 × Z 2 × gm ⎭ with Z1 and Z2 as complex impedances at pins XTAL1 and XTAL2, hence Z1 = –j / (2 × p × fXTO × CL1) + 5Ω and Z2 = –j / (2 × p × fXTO × CL2) + 5Ω. Z3 consists of crystal C0 in parallel with an internal 110-kΩ resistor, hence Z3 = –j / (2 × p × fXTO × C0) / 110 kΩ, gm is the internal transconductance between XTAL1 and XTAL2, with typically 20 mS at 25°C. With fXTO = 13.5 MHz, gm = 20 mS, CL = 9 pF, and C0 = 2.2 pF, this results in a negative resistance of about 2 kΩ. The worst case for technology, supply voltage, and temperature variations is then always higher than 1.4 kΩ for C0 ≤ 2.2 pF. Due to the large gain at start, the XTO is able to meet a very low start-up time. The oscillation start-up time can be estimated with the time constant τ . 2 τ = -----------------------------------------------------------------------------------------------------------------2 2 4 × π × f XTAL × C m × ( Re ( Z xtocore ) + R m ) After 10τ to 20τ , an amplitude detector detects the oscillation amplitude and sets XTO_OK to High if the amplitude is large enough; this activates the CLK_OUT output if it is enabled via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the DVCC voltage also have to be fulfilled. It is recommended to use a crystal with C m = 3.0 fF to 10 fF, C LN = 9 pF, R m < 120 Ω a nd C0 = 1.0 pF to 2.2 pF. Lower values of Cm can be used, slightly increasing the start-up time. Lower values of C0 or higher values of Cm (up to 15 fF) can also be used, with only little influence on pulling. 16 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 Figure 3-2. XTO Block Diagram CL1 CL2 XTAL1 XTAL2 CLK_OUT_CTRL0 CLK_OUT_CTRL1 CLK_OUT & fFXTO Divider /3, /6, /12 XTO_OK Amplitude Detector Divider /16 fDCLK The relationship between fXTO and the fRF is shown in Table 3-1. Table 3-1. Calculation of fRF fXTO [MHz] 13.57375 13.1433 fRF fXTO × 32 – 440 kHz fXTO × 24 – 440 kHz Frequency [MHz] 433.92 (ATA8202) 315.0 (ATA8201) Attention must be paid to the harmonics of the CLK_OUT output signal fCLK_OUT as well as to the harmonics produced by an microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the RF input. If the CLK_OUT signal is used, it must be carefully laid out on the application PCB. The supply voltage of the microcontroller must also be carefully blocked. 17 4971C–INDCO–04/09 3.1 Pin CLK_OUT Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in Standby and Active modes. The frequency f C L K _ O U T c an be adjusted via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows: Table 3-2. Setting of fCLK_OUT CLK_OUT_CTRL0 0 1 0 1 Function Clock on pin CLK_OUT is switched off (Low level on pin CLK_OUT) fCLK_OUT = fXTO / 3 fCLK_OUT = fXTO / 6 fCLK_OUT = fXTO / 12 CLK_OUT_CTRL1 0 0 1 1 The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recommended that CLK_OUT be switched off during Standby mode. 3.2 Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry is derived from one clock. As seen in Figure 3-2 on page 17, this clock cycle, TDCLK, is derived from the crystal oscillator (XTO) in combination with a divider. f XTO f DCLK = ---------16 TDCLK controls the following application relevant parameters: - Debouncing of the data signal stream - Start-up time of the RX signal path The start-up time and the debounce characteristic depend on the selected bit rate range (BR_Range) which is defined by pins BR0 and BR1. The clock cycle TXDCLK is defined by the following formulas for further reference: BR_Range ⇒ BR_Range 0: TXDCLK = 8 × BR_Range 1: TXDCLK = 4 × BR_Range 2: TXDCLK = 2 × BR_Range 3: TXDCLK = 1 × TDCLK TDCLK TDCLK TDCLK 18 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 4. Sensitivity Reduction The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSense. RSense is connected between the pins SENSE and VS3V_AVCC (see Figure 10-1 on page 29). The output of the comparator is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity. If the level on input pin SENSE_CTRL is low, the receiver operates at full sensitivity. If the level on input pin SENSE_CTRL is high, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of R Sense , the maximum sensitivity by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 2-1 on page 7 and exhibits the best possible sensitivity. If the sensitivity reduction feature is not used, pin SENSE can be left open, pin SENSE_CTRL must be set to GND. To operate with reduced sensitivity, pin SENSE_CTRL must be set to high before the RX signal path will be enabled by setting pin RX to high (see Figure 4-1 on page 20). As long as the RSSI level is lower than VTh_red (defined by the external resistor RSense) no data stream is available on pin DATA_OUT (low level on pin DATA_OUT). An internal RS flip-flop will be set to high the first time the RSSI voltage crosses VTh_red, and from then on the data stream will be available on pin DATA_OUT. From then on the receiver also works with full sensitivity. This makes sure that a telegram will not be interrupted if the RSSI level varies during the transmission. The RS flip-flop can be set back, and thus the receiver switched back to reduced sensitivity, by generating a positive pulse on pin ASK_NFSK (see Figure 4-2 on page 20). In FSK mode, operating with reduced sensitivity follows the same way. 19 4971C–INDCO–04/09 Figure 4-1. Reduced Sensitivity Active ENABLE ASK_NFSK SENSE_CTRL RX VTh_red RSSI tStartup_PLL tStartup_Sig_Proc DATA_OUT Figure 4-2. Restart Reduced Sensitivity ENABLE ASK_NFSK SENSE_CTRL RX VTh_red RSSI tStartup_Sig_Proc DATA_OUT 20 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 5. Power Supply Figure 5-1. VS3V_AVCC SW_DVCC VS5V IN V_REG 3.0V typ. EN RX OUT DVCC Power Supply The supply voltage range of the ATA8201/ATA8202 is 2.7V to 3.3V or 4.5V to 5.5V. Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery applications using a single lithium 3V cell. Pin VS5V is the voltage input for the range 4.5V to 5.5V (car applications) in this case the voltage regulator V_REG regulates VS3V_AVCC to typically 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2 µF has to be connected to VS3V_AVCC (see Figure 10-1 on page 29). DVCC is the internal operating voltage of the digital control logic and is fed via the switch SW_DVCC by VS3V_AVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 9-1 on page 28 and Figure 10-1 on page 29). Pin RX is the input to activate the RX signal processing and set the receiver to Active mode. 5.1 OFF Mode A low level on pin RX and ENABLE will set the receiver to OFF mode (low power mode). In this mode, the crystal oscillator is shut down and no clock is available on pin CLK_OUT. The receiver is not sensitive to a transmitter signal in this mode. Table 5-1. RX 0 Standby Mode ENABLE 0 Function OFF mode 5.2 Standby Mode The receiver activates the Standby mode if pin ENABLE is set to “1”. In Standby mode, the XTO is running and the clock on pin CLK_OUT is available after the start-up time of the XTO ha s elapsed (dependent on pin CLK_OUT_CTRL0 an d CLK_OUT_CTRL1). During Standby mode, the receiver is not sensitive to a transmitter signal. In Standby mode, the RX signal path is disabled and the power consumption IStandby is typically 50 µA (CLK_OUT output off, VS3V_AVCC = VS5V = 3V). The exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the section “Electrical Characteristics: General” on page 30 for the appropriate application case. 21 4971C–INDCO–04/09 Table 5-2. RX 0 Standby Mode ENABLE 1 Function Standby mode Figure 5-2. Standby Mode (CLK_OUT_CTRL0 or CLK_OUT_CTRL1 = 1) CLK_OUT tXTO_Startup ENABLE Standby Mode 5.3 Active Mode The Active mode is enabled by setting the level on pin RX to high. In Active mode, the RX signal path is enabled and if a valid signal is present it will be transferred to the connected microcontroller. Table 5-3. RX 1 Active Mode ENABLE 1 Function Active mode During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing circuit starts up (TStartup_Sig_Proc). After the start-up time, all circuits are in stable condition and ready to receive. The duration of the start-up sequence depends on the selected bit rate range. Figure 5-3. Active Mode CLK_OUT ENABLE RX DATA_OUT tStartup_PLL IStandby Standby Mode IStartup_PLL Startup tStartup_Sig_Proc IActive DATA_OUT valid IActive Active Mode 22 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 Table 5-4. BR1 0 0 1 1 BR0 0 1 0 1 261 µs Start-up Time ATA8202 (433.92 MHz) TStartup_PLL TStartup_Sig_Proc 1096 µs 644 µs 417 µs 304 µs 269 µs ATA8201 (315 MHz) TStartup_PLL TStartup_Sig_Proc 1132 µs 665 µs 431 µs 324 µs Table 5-5. ASK_NFSK 0 1 Modulation Scheme RFIN at Pin LNA_IN fFSK_H fFSK_L fASK on fASK off Level at Pin DATA_OUT 1 0 1 0 23 4971C–INDCO–04/09 6. Bit Rate Ranges Configuration of the bit rate ranges is carried out via the two pins BR0 and BR1. The microcontroller uses these two interface lines to set the corner frequencies of the band-pass data filter. Switching the bit rate ranges while the RF front end is in Active mode can be done on the fly and will not take longer than 100 µs if done while remaining in either ASK or FSK mode. If the modulation scheme is changed at the same time, the switching time is (TStartup_Sig_Proc, see Figure 7-1 on page 26). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sensitivity of the receiver, edge-to-edge transition times of incoming data should not be less than the minimum for the selected BR_Range. Table 6-1. BR Ranges ASK Recommended Bit Rate (Manchester)(1) 1.0 Kbit/s to 2.5 Kbits/s 2.0 Kbits/s to 5.0 Kbits/s 4.0 Kbits/s to 10.0 Kbits/s 8.0 Kbits/s to 10.0 Kbits/s Minimum Edge-to-edge Edge-to-edge Time Period TEE of Time Period TEE of the Data the Data Signal During the Start-up Period(3) Signal(2) 200 µs 100 µs 50 µs 50 µs 200 µs to 500 µs 100 µs to 250 µs 50 µs to 125 µs 50 µs to 62.5 µs BR1 0 0 1 1 BR0 0 1 0 1 BR_Range BR_Range0 BR_Range1 BR_Range2 BR_Range3 Table 6-2. BR Ranges FSK Recommended Bit Rate (Manchester)(1) 1.0 Kbit/s to 2.5 Kbits/s 2.0 Kbits/s to 5.0 Kbits/s 4.0 Kbits/s to 10.0 Kbits/s 8.0 Kbits/s to 20.0 Kbits/s Minimum Edge-to-edge Edge-to-edge Time Period TEE of Time Period TEE of the Data the Data Signal During the Start-up Signal(2) Period(3) 200 µs 100 µs 50 µs 25 µs 200 µs to 500 µs 100 µs to 250 µs 50 µs to 125 µs 25 µs to 62.5 µs BR1 0 0 1 1 Note: Notes: BR0 0 1 0 1 BR_Range BR_Range0 BR_Range1 BR_Range2 BR_Range3 If during the start-up period (TStartup_PLL + TStartup_Sig_Proc) there is no RF signal, the data filter settles to the noise floor, leading to noise on pin DATA_OUT. 1. As can be seen, a bit stream of, for example, 2.5 Kbits/s can be received in BR_Range0 and BR_Range1 (overlapping BR_Ranges). To get the full sensitivity, always use the lowest possible BR_Range (here, BR_Range0). The advantage in the next higher BR_Range (BR_Range1) is the shorter start-up period, meaning lower current consumption during Polling mode. Thus, it is a decision between sensitivity and current consumption. 2. The receiver is also capable of receiving non-Manchester-modulated signals, such as PWM, PPM, VPWM, NRZ. In ASK mode, the header and blanking periods occurring in Keeloq-like protocols (up to 52 ms) are supported. 3. To ensure an accurate settling of the data filter during the start-up period (TStartup_PLL + TStartup_Sig_Proc), the edge-to-edge time TEE of the data signal (preamble) must be inside the given limits during this period. 24 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 Figure 6-1. Examples of Supported Modulation Formats TEE TEE TEE TEE MAN: Logic 0 Logic 1 TEE TEE TEE TEE TEE TEE PWM: Logic 0 Logic 1 Logic 0 TEE TEE Logic 1 TEE VPWM: On Transition Low to High Logic 0 TEE Logic 1 TEE TEE On Transition High to Low TEE TEE TEE TEE TEE TEE PPM: Logic 0 Logic 1 TEE TEE NRZ: Logic 0 Logic 1 Figure 6-2. Supported Header and Blanking Periods Preamble Header Data Burst Guard Time Data Burst 25 4971C–INDCO–04/09 7. ASK_NFSK The ASK_NFSK pin allows the microcontroller to rapidly switch the RF front end between demodulation modes. A logic 1 on this pin selects ASK mode, and a logic 0 FSK mode. The time to change modes (TStartup_Sig_Proc) depends on the bit rate range being selected (not current bit rate range) and is given in Table 5-4 on page 23. This response time is specified for applications that require an ASK preamble followed by FSK data (for typical TPM applications). During TStartup_Sig_Proc, the level on pin DATA_OUT is low. Figure 7-1. ASK Preamble 2.4 Kbits/s followed by FSK Data 9.6 Kbits/s ENABLE RX BR1 BR0 ASK_NFSK DATA_OUT Data valid BR0 TStartup_Sig_Proc Data valid BR3 26 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 8. Polling Current Calculation Figure 8-1. ENABLE RX Polling Cycle IStartup_PLL IActive IStartup_PLL IStandby IStandby TBitcheck (= 1 / Signal_Bitrate (average) TStartup_Sig_Proc (Startup Signal Processing) TStartup_PLL (Startup RF-PLL) IActive ISupply In an industrial or aftermarket RKE and TPM system, the average chip current in Polling mode, IPolling, is an important parameter. The polling period must be controlled by the connected microcontroller via the pins ENABLE and RX. The polling current can be calculated as follows: I Polling = (T Startup_PLL / T Polling_Period ) × I Startup_PLL + (T Startup_Sig_Proc / T Polling_Period ) × I Active + (T Bitcheck / T Polling_Period ) × I Active + (T Polling_Period – T Startup_PLL – T Startup_Sig_Proc – T Bitcheck ) / TPolling_Period × IStandby TStartup_PLL: TStartup_Sig_Proc: TBitcheck: TPolling_Period: IStartup_PLL: IActive: IStandby: Example:depends on 315 MHz/433.92 MHz application. depends on 315 MHz/433.92 MHz application and the selected bit rate range. depends on the signal bit rate (1 / Signal_Bit_Rate). depends on the transmitter telegram (preburst). depends on 3V or 5V application and the setting of pin CLK_OUT. depends on 3V or 5V application, ASK or FSK mode and the setting of pin CLK_OUT. depends on 3V or 5V application and the setting of pin CLK_OUT. 315-MHz application (ATA8201), bit rate: 9.6 Kbits/s, TPolling_Period = 8 ms --> TStartup_PLL = 269 µs = 324 µs (Bit Rate Range 3) --> TStartup_Sig_Proc --> TBitcheck = 104 µs 3V application; ASK mode, CLK_OUT disabled --> IStartup_PLL = 4.5 mA --> IActive = 6.5 mA --> IStandby = 0.05 mA --> IPolling = 0.545 mA 27 4971C–INDCO–04/09 9. 3V Application Figure 9-1. 3V Application 15 nF DATA_OUT CDEM BR1 ASK_NFSK BR0 output TEST2 Microcontroller output RX TEST3 TEST1 RSSI output CLK_OUT ATA8201/ ATA8202 SENSE_CTRL output CLK_OUT_CTRL1 SENSE 2.2 pF input CLK_OUT_CTRL0 VS3V_AVCC ENABLE XTAL2 XTAL1 DVCC VS5V LNA_IN LNA_GND GND RFIN output VSS VCC 68 nH/36 nH 315 MHz/433.92 MHz 68 nF 18 pF 18 pF 68 nF VCC = 2.7V to 3.3V Note: Paddle (backplane) must be connected to GND 28 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 10. 5V Application Figure 10-1. 5V Application With Reduced/Full Sensitivity 15 nF output CDEM DATA_OUT BR1 ASK_NFSK BR0 output TEST2 Microcontroller output RX TEST3 TEST1 RSSI output CLK_OUT ATA8201/ ATA8202 SENSE_CTRL RSense SENSE output CLK_OUT_CTRL1 2.2 pF input CLK_OUT_CTRL0 VS3V_AVCC ENABLE XTAL2 XTAL1 DVCC VS5V LNA_IN LNA_GND GND RFIN output VSS VCC 68 nF 68 nH/36 nH 315 MHz/433.92 MHz 18 pF 18 pF 2.2 µF 68 nF VCC = 4.5V to 5.5V Note: Paddle (backplane) must be connected to GND 29 4971C–INDCO–04/09 11. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Junction temperature Storage temperature Ambient temperature Supply voltage VS5V ESD (Human Body Model ESD S 5.1) every pin ESD (Machine Model JEDEC A115A) every pin ESD (Field Induced Charge Device Model ESD STM 5.3.1-1999) every pin Maximum input level, input matched to 50Ω Symbol Tj Tstg Tamb VS HBM MM FCDM Pin_max –4 –200 –500 –55 –40 Min. Max. +150 +125 +85 +6 +4 +200 +500 0 Unit °C °C °C V kV V V dBm 12. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 25 Unit K/W 13. Electrical Characteristics: General All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters 1 1.1 2 2.1 OFF Mode Supply current in OFF mode Standby Mode RF operating frequency range ATA8201 ATA8202 XTO running VVS3V_AVCC = VVS5V ≤ 3V CLK_OUT disabled XTO running VVS5V = 5V CLK_OUT disabled XTO startup XTAL: Cm = 5 fF, C0 = 1.8 pF, Rm = 15Ω 14 14 10,11 fRF fRF IStandby 313 433 50 317 435 100 MHz MHz µA A A A VVS3V_AVCC = VVS5V ≤ 3V VVS5V = 5V CLK_OUT disabled 10, 11 10 ISOFF 4 4 µA µA A A Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* 2.2 Supply current Standby mode 10,11 IStandby 50 100 µA A 2.3 System start-up time TXTO_Startup 0.3 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 30 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 13. Electrical Characteristics: General (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* From Standby mode to Active mode Active mode start-up time BR_Range_3 ATA5745 ATA5746 Active Mode VVS3V_AVCC = VVS5V = 3V ASK mode CLK_OUT disabled SENSE_CTRL = 0 VVS3V_AVCC = VVS5V = 3V FSK mode CLK_OUT disabled SENSE_CTRL = 0 VVS5V = 5V ASK mode CLK_OUT disabled SENSE_CTRL = 0 VVS5V = 5V FSK mode CLK_OUT disabled SENSE_CTRL = 0 VVS3V_AVCC = VVS5V = 3V TPolling_Period = 8 ms BR_Range_3, ASK mode, CLK_OUT disabled Data rate = 9.6 Kbits/s FSK deviation fDEV = ±38 kHz BER = 10–3 Tamb = 25°C 3.3 Input sensitivity FSK fRF = 315 MHz Bit rate 9.6 Kbits/s BR2 Bit rate 2.4 Kbits/s BR0 FSK deviation ±18 kHz to ±50 kHz Bit rate 9.6 Kbits/s BR2 Bit rate 2.4 Kbits/s BR0 ASK 100% level of carrier, BER = 10–3 Tamb = 25°C Bit rate 9.6 Kbits/s BR2 Bit rate 2.4 Kbits/s BR0 Note: (14) (14) PREF_ASK PREF_ASK –109 –112 –111 –114 –112.5 –115.5 dBm dBm B B (14) (14) PREF_FSK PREF_FSK –101 –104 dBm dBm B B (14) (14) PREF_FSK PREF_FSK –103 –106 –105 –108 –106.5 –109.5 dBm dBm B B 2.4 TStartup_PLL + TStartup_Sig_Proc A 565 593 µs µs 3 10,11 IActive 6.5 mA A 10,11 IActive 6.7 mA A 3.1 Supply current Active mode 10 IActive 6.7 mA A 10 IActive 6.9 mA A 3.2 Supply current Polling mode 10,11 IPolling 545 µA C 3.4 Input sensitivity ASK fRF = 315 MHz *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 31 4971C–INDCO–04/09 13. Electrical Characteristics: General (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Sensitivity change at fRF = 433.92 MHz compared to fRF = 315 MHz Test Conditions fRF = 315 MHz to fRF = 433.92 MHz P = PREF_ASK + ΔPREF1 P = PREF_FSK + ΔPREF1 Pin(1) Symbol ΔPREF1 Min. Typ. Max. Unit Type* 3.5 (14) +1 dB B 3.6 FSK fDEV = ±38 kHz ΔfOFFSET ≤ ±160 kHz Sensitivity change versus ASK 100% ΔfOFFSET ≤ ±160 kHz temperature, supply P = PREF_ASK + ΔPREF1 + voltage and frequency ΔPREF2 offset P = PREF_FSK + ΔPREF1 + ΔPREF2 RSense connected from pin SENSE to pin VS3V_AVCC RSense = 62 kΩ fin = 433.92 MHz Reduced sensitivity RSense = 82 kΩ fin = 433.92 MHz RSense = 62 kΩ fin = 315 MHz RSense = 82 kΩ fin = 315 MHz Reduced sensitivity variation over full operating range RSense = 62 kΩ RSense = 82 kΩ PRed = PRef_Red + PΔRed Maximum frequency difference of fRF between receiver and transmitter in FSK mode (fRF is the center frequency of the FSK signal with fBIT = 10 Kbits/s fDEV = ±38 kHz With up to 2 dB loss of sensitivity. Note that the tolerable frequency offset is 12 kHz lower for fDEV = ±50 kHz than for fDEV = ±38 kHz, hence, ΔfOFFSET ≤ ±148 kHz fRF = 315 MHz fRF = 433.92 MHz (14) ΔPREF2 +4.5 –1.5 B PRef_Red –76 –88 –76 –88 ΔPRed dBm (peak level) dBm dBm dBm dBm C C C C 3.7 –10 +10 dB 3.8 Maximum frequency offset in FSK mode (14) ΔfOFFSET –160 +160 kHz B 3.9 Supported FSK frequency deviation (14) fDEV ±18 ±38 ±50 kHz B 3.10 System noise figure (14) (14) NF NF 6.0 7.0 9 10 dB dB B B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 32 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 13. Electrical Characteristics: General (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters 3.11 Intermediate frequency Test Conditions fRF = 433.92 MHz fRF = 315 MHz 3 dB bandwidth This value is for information only! Note that for crystal and system frequency offset calculations, ΔfOFFSET must be used. Δfmeas1 = 1.8 MHz Δfmeas2 = 3.6 MHz fRF = 315 MHz fRF = 433.92 MHz Δfmeas1 = 1 MHz fRF = 315 MHz fRF = 433.92 MHz fRF = 315 MHz fRF = 433.92 MHz BER < 10 , ASK: 100% FSK: fDEV = ±38 kHz f < 1 GHz f >1 GHz 3.17 LO spurs at LNA_IN fLO = 315.44 MHz 2 × fLO 4 × fLO fLO = 434.36 MHz 2 × fLO 4 × fLO With the complete image band fRF = 315 MHz fRF = 433.92 MHz Peak level of useful signal to peak level of interferer for BER < 10–3 with any modulation scheme of Useful signal to interferer interferer 3.19 ratio FSK BR_Ranges 0, 1, 2 FSK BR_Range_3 ASK (PRF < PRFIN_High) Note: –3 Pin(1) Symbol fIF fIF Min. Typ. 440 440 Max. Unit kHz kHz Type* A A 3.12 System bandwidth (14) SBW 435 kHz A System out-band 3.13 3rd-order input intercept point System outband input 1-dB compression point (14) (14) (14) (14) 14 14 (14) (14) (14) (14) (14) IIP3 IIP3 I1dBCP I1dBCP Zin_LNA Zin_LNA PIN_max PIN_max –24 –23 –31 –30 (72.4 – j298) (55 – j216) +5 +5 –10 –10 –57 –47 –90 –94 –68 –92 –88 –58 –36 –35 dBm dBm dBm dBm Ω Ω dBm dBm dBm dBm dBm C C C C C C C C C C C 3.14 3.15 LNA input impedance 3.16 Maximum peak RF input level, ASK and FSK (14) dBm C 3.18 Image rejection A (14) (14) 24 24 30 30 dB dB A (14) (14) (14) SNRFSK0-2 SNRFSK3 SNRASK 2 4 10 3 6 14 dB dB dB B B B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 33 4971C–INDCO–04/09 13. Electrical Characteristics: General (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions Dynamic range Lower level of range fRF = 315 MHz fRF = 433.92 MHz 3.20 RSSI output Upper level of range fRF = 315 MHz fRF = 433.92 MHz Gain Output voltage range 3.21 Output resistance RSSI pin Sensitivity (BER = 10–3) is reduced by 3 dB if a continuous wave blocking signal at ±Δf is ΔPBlock higher than the useful signal level (Bit rate = 10 Kbits/s, FSK, fDEV ± 38 kHz, Manchester code, BR_Range2) 3.22 Blocking fRF = 315 MHz Δf ± 1.5 MHz Δf ± 2 MHz Δf ± 3 MHz Δf ± 10 MHz Δf ± 20 MHz fRF = 433.92 MHz Δf ± 1.5 MHz Δf ± 2 MHz Δf ± 3 MHz Δf ± 10 MHz Δf ± 20 MHz 3.23 CDEM Capacitor connected to pin 23 (CDEM) 57.5 63.0 67.5 72.0 74.0 56.5 62.0 66.5 71.0 73.0 –5% 15 +5% Pin(1) (14),17 (14),17 Symbol DRSSI PRFIN_Low Min. Typ. 65 –110 Max. Unit dB dBm Type* A A (14),17 (14),17 (14),17 17 PRFIN_High –45 15 dBm mV/dB 1600 mV kΩ A A A C VRSSI RRSSI 350 8 10 12.5 (14) ΔPBlock dBC C (14) ΔPBlock dBC C 23 nF D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 34 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 13. Electrical Characteristics: General (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters 4 4.1 XTO At startup; after startup Transconductance XTO at the amplitude is regulated start to VPPXTAL XTO start-up time Maximum C0 of XTAL Pulling of LO frequency fLO due to XTO, CL1 and CL2 versus temperature and supply changes 1.0 pF ≤ C0 ≤ 2.2 pF Cm = 4.0 fF to 7.0 fF Rm ≤ 120Ω Cm = 5 fF, C0 = 1.8 pF Rm = 15Ω 4.5 Amplitude XTAL after startup V(XTAL1, XTAL2) peak-to-peak value V(XTAL1) peak-to-peak value C0 ≤ 2.2 pF, small signal Maximum series start impedance, this resistance Rm of XTAL at value is important for startup crystal oscillator startup Maximum series resistance Rm of XTAL after startup Nominal XTAL load resonant frequency C0 ≤ 2.2 pF Cm < 14 fF fRF = 433.92 MHz fRF = 315 MHz CLK_OUT_CRTL1 = 0 CLK_OUT_CTRL0 = 0 --> CLK_OUT disabled CLK_OUT_CRTL1 = 0 CLK_OUT_CTRL0 = 1 --> division ratio = 3 CLK_OUT_CRTL1 = 1 CLK_OUT_CTRL0 = 0 --> division ratio = 6 CLK_OUT_CRTL1 = 1 CLK_OUT_CTRL0 = 1 --> division ratio = 12 Note: 7,8 7,8 VPPXTAL VPPXTAL 700 350 mVpp mVpp C C C0 ≤ 2.2 pF Cm < 14 fF Rm ≤ 120Ω 7,8 gm, XTO 20 mS B Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type* 4.2 4.3 7,8 7,8 TXTO_Startup C0max ΔfXTO –5 300 3.8 µs pF A D 4.4 3 +5 ppm C 4.6 7,8 ZXTAL12_START –1400 –2000 Ω B 4.7 7,8 Rm_max fXTAL 15 13.57375 13.1433 120 Ω MHz B 4.8 7,8 D fCLK disabled (low level on pin CLK_OUT) f XTO f CLK = ---------3 3 fCLK_OUT f CLK f XTO = ---------6 MHz A 4.9 External CLK_OUT frequency f XTO f CLK = ---------12 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 35 4971C–INDCO–04/09 13. Electrical Characteristics: General (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. Parameters Test Conditions fRF = 433.92 MHz CLK_OUT division ratio =3 =6 = 12 CLK_OUT has nominal 50% duty cycle fRF = 315 MHz CLK_OUT division ratio =3 =6 = 12 CLK_OUT has nominal 50% duty cycle 4.10 DC voltage after startup 5 Synthesizer At ±fCLK_OUT, CLK_OUT enabled (division ratio = 3) fRF = 315 MHz fRF = 433.92 MHz at ±fXTO fRF = 315 MHz fRF = 433.92 MHz 5.2 5.3 6 Phase noise at 3 MHz Active mode Phase noise at 20 MHz Active mode Microcontroller Interface fCLK_OUT < 4.5 MHz CL = 10 pF CL = Load capacitance on CLK_OUT output rise and pin CLK_OUT fall time 2.7V ≤ VVS5V ≤ 3.3V or 4.5V ≤ VVS5V ≤ 5.5V 20% to 80% VVS5V Internal equivalent capacitance Used for current calculation fRF = 315 MHz fRF = 433.92 MHz Noise floor VDC (XTAL1, XTAL2) XTO running (Standby mode, Active mode) Pin(1) Symbol Min. Typ. Max. Unit Type* 3 fCLK_OUT 4.52458 2.26229 1.13114 MHz D 3 fCLK_OUT 4.3811 2.190 1.0952 MHz D 7,8 VDCXTO –250 –45 mV C SPRX –75 –70 dBC C 5.1 Spurs in Active mode SPRX LRX3M LRX20M –75 –70 dBC A –130 –135 –127 –132 dBC/Hz dBC/Hz A B trise 3 tfall 20 20 30 30 ns ns B 6.1 6.2 3 CCLK_OUT 8 pF B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component values as in Table 2-2 on page 7 (RFIN). 36 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 14. Electrical Characteristic: 3V Application All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V and VVS5V = 5V. Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. 7 7.1 7.2 Parameters 3V Application Supply current in OFF mode Supported voltage range VVS3V_AVCC = VVS5V ≤ 3V CLK_OUT disabled 3V application 10, 11 10, 11 ISOFF VVS3V_AVCC, VVS5V 2.7 2 3.3 µA V A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 7.3 VVS3V_AVCC = VVS5V ≤3V external load C on pin CLK_OUT = 12 pF CLK enabled (division ratio 3) Current in Standby mode (XTO is running) CLK enabled (division ratio 6) CLK enabled (division ratio 12) CLK disabled Current during TStartup_PLL VVS3V_AVCC = VVS5V ≤3V CLK disabled 420 10, 11 IStandby 290 220 50 10, 11 IStartup_PLL IActive 4.5 mA µA C C C A C 7.4 7.5 VVS3V_AVCC = VVS5V ≤3V Current in Active mode CLK disabled ASK SENSE_CTRL = 0 VVS3V_AVCC = VVS5V ≤3V Current in Active mode CLK disabled FSK SENSE_CTRL = 0 10, 11 6.5 mA A 7.6 10, 11 IActive 6.7 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 37 4971C–INDCO–04/09 15. Electrical Characteristics: 5V Application All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V and VVS5V = 5V. Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”. No. 8 8.1 8.2 Parameters 5V Application Supply current in OFF mode Supported voltage range VVS5V = 5V CLK_OUT disabled 5V application VVS5V ≤5V external load C on pin CLK_OUT = 12 pF CLK enabled (division ratio 3) CLK enabled (division ratio 6) CLK enabled (division ratio 12) CLK disabled VVS5V = 5V CLK disabled VVS5V = 5V CLK disabled SENSE_CTRL = 0 VVS5V = 5V CLK disabled SENSE_CTRL = 0 10 10 ISOFF VVS5V 4.5 2 5.5 µA V A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 8.3 Current in Standby mode (XTO is running) 700 10 IStandby 490 370 50 10 IStartup_PLL IActive 4.7 mA µA C C C A C 8.4 Current during TStartup_PLL Current in Active mode ASK Current in Active mode FSK 8.5 10 6.7 mA A 8.6 10 IActive 6.9 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 38 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 16. Digital Timing Characteristics All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. 9 9.1 Parameters Basic clock cycle BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 Test Conditions Pin Symbol TDCLK Min. 16 / fXTO 8 4 2 1 × TDCLK Typ. Max. 16 / fXTO 8 4 2 1 × TDCLK 15 µs + 208 × TDCLK 929.5 545.5 353.5 257.5 × TDCLK 929.5 545.5 353.5 257.5 × TDCLK Unit µs Type* A Basic Clock Cycle of the Digital Circuitry 9.2 Extended basic clock cycle TXDCLK µs A 10 10.1 Active Mode Startup PLL BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 ASK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 FSK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 TStartup_PLL µs A 10.2 Startup signal processing TStartup_Sig_Proc A 10.3 Bit rate range BR_Range 1.0 2.0 4.0 8.0 2.5 5.0 10.0 10.0 Kbits/s A 1.0 2.0 4.0 8.0 10 × TXDCLK 200 100 50 25 2.5 5.0 10.0 20.0 10.4 Minimum time period between edges at pin DATA_OUT Edge-to-edge time period of the data signal for full sensitivity in Active mode 24 TDATA_OUT_min µs A 10.5 TDATA_OUT 500 250 125 62.5 µs B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 39 4971C–INDCO–04/09 17. Digital Port Characteristics All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. 11 Parameters Digital Ports VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V ENABLE input - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = V = 2.7V to 3.3V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V RX input - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = V = 2.7V to 3.3V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V BR0 input - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = V = 2.7V to 3.3V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V BR1 input - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = = 2.7V to 3.3V V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V ASK_NFSK input - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = = 2.7V to 3.3V V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V 0.2 × VS 6 VIl 0.12 × VS 0.8 × VS 0.2 × VS 19 VIl 0.12 × VS 0.8 × VS 0.2 × VS 20 VIl 0.12 × VS 0.8 × VS V A V A V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 11.1 6 VIh V A 11.2 19 VIh V A 11.3 20 VIh V A 21 VIl 0.2 × VS 0.12 × VS V A 11.4 21 VIh 0.8 × VS V A 22 VIl 0.2 × VS 0.12 × VS V A 11.5 22 VIh 0.8 × VS V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 40 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 17. Digital Port Characteristics (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pin Symbol Min. Typ. Max. 0.2 × VS 16 VIl 0.12 × VS 0.8 × VS 0.2 × VS 5 VIl 0.12 × VS 0.8 × VS 0.2 × VS 4 VIl 0.12 × VS 0.8 × VS V A V A V A Unit Type* VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V SENSE_CTRL input - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = V = 2.7V to 3.3V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = CLK_OUT_CTRL0 input VVS5V = 2.7V to 3.3V - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = = 2.7V to 3.3V V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = CLK_OUT_CTRL1 input VVS5V = 2.7V to 3.3V - Low level input voltage VS = VVS5V = 4.5V to 5.5V VS = VVS3V_AVCC = = 2.7V to 3.3V V - High level input voltage VS5V VS = VVS5V = 4.5V to 5.5V TEST1 input TEST1 input must always be connected directly to GND TEST2 output must always be connected directly to GND TEST3 input must always be connected directly to GND 11.6 16 VIh V A 11.7 5 VIh V A 11.8 4 VIh V A 11.9 2 0 0 V D 11.10 TEST2 output 1 0 0 V D 11.11 TEST3 input 18 0 0 V D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 41 4971C–INDCO–04/09 17. Digital Port Characteristics (Continued) All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics” No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V DATA_OUT output VS = VVS5V = - Saturation voltage low 4.5V to 5.5V IDATA_OUT = 250 µA VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V - Saturation voltage high VS = VVS5V = 4.5V to 5.5V IDATA_OUT = –250 µA VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V CLK_OUT output VS = VVS5V = - Saturation voltage low 4.5V to 5.5V IDATA_OUT = 100 µA VS = VVS3V_AVCC = VVS5V = 2.7V to 3.3V - Saturation voltage high VS = VVS5V = 4.5V to 5.5V IDATA_OUT = –100 µA 24 Vol 0.15 0.4 V B 11.12 24 Voh VVS – 0.4 VVS – 0.15 V B 3 Vol 0.15 0.4 V B 11.13 3 Voh VVS – 0.4 VVS – 0.15 V B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 42 ATA8201/ATA8202 4971C–INDCO–04/09 ATA8201/ATA8202 18. Ordering Information Extended Type Number ATA8202-PXQW ATA8201-PXQW Package QFN24 QFN24 MOQ 6000 pcs 6000 pcs Remarks 5 mm × 5 mm, Pb-free, 433.92 MHz 5 mm × 5 mm, Pb-free, 315 MHz 19. Package Information Package: QFN 24 - 5 x 5 Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances ±0.05 0.9±0.1 0.05-0.05 24 1 0.4 18 19 +0 5 3.6 24 1 technical drawings according to DIN specifications 6 0.3 13 12 7 6 0.65 nom. Drawing-No.: 6.543-5122.01-4 Issue: 1; 15.11.05 3.25 20. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4971C-INDCO-04/09 4971B-INDCO-10/07 History • Put datasheet in the newest template • Benefits changed (page 2) • Put datasheet in the newest template 43 4971C–INDCO–04/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support industrial@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. A tmel ®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4971C–INDCO–04/09

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