ATMEGA640V_11

Features • • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – 64K/128K/256KBytes of In-System Self-Programmable Flash – 4Kbytes EEPROM – 8Kbytes Internal SRAM – Write/Erase Cycles:10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security • Endurance: Up to 64Kbytes Optional External Memory Space Atmel® QTouch® library support – Capacitive touch buttons, sliders and wheels – QTouch and QMatrix® acquisition – Up to 64 sense channels JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – Real Time Counter with Separate Oscillator – Four 8-bit PWM Channels – Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits (ATmega1281/2561, ATmega640/1280/2560) – Output Compare Modulator – 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) – Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages – 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560) – 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561) – 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560) – RoHS/Fully Green Temperature Range: – -40°C to 85°C Industrial Ultra-Low Power Consumption – Active Mode: 1MHz, 1.8V: 500µA – Power-down Mode: 0.1µA at 1.8V Speed Grade: – ATmega640V/ATmega1280V/ATmega1281V: • 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V – ATmega2560V/ATmega2561V: • 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V – ATmega640/ATmega1280/ATmega1281: • 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V – ATmega2560/ATmega2561: • 0 - 16MHz @ 4.5V - 5.5V • • • • 8-bit Atmel Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash ATmega640/V ATmega1280/V ATmega1281/V ATmega2560/V ATmega2561/V Preliminary Summary • • • • • 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 1. Pin Configurations Figure 1-1. TQFP-pinout ATmega640/1280/2560 PK2 (ADC10/PCINT18) PK3 (ADC11/PCINT19) PK4 (ADC12/PCINT20) PK5 (ADC13/PCINT21) PK6 (ADC14/PCINT22) PK7 (ADC15/PCINT23) PK0 (ADC8/PCINT16) PK1 (ADC9/PCINT17) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF0 (ADC0) PF7 (ADC7/TDI) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PA0 (AD0) PA1 (AD1) 77 100 99 (OC0B) PG5 (RXD0/PCINT8) PE0 (TXD0) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (CLKO/ICP3/INT7) PE7 VCC GND (RXD2) PH0 (TXD2) PH1 (XCK2) PH2 (OC4A) PH3 (OC4B) PH4 (OC4C) PH5 (OC2B) PH6 (SS/PCINT0) PB0 (SCK/PCINT1) PB1 (MOSI/PCINT2) PB2 (MISO/PCINT3) PB3 (OC2A/PCINT4) PB4 (OC1A/PCINT5) PB5 (OC1B/PCINT6) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 PA2 (AD2) 76 75 74 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PJ6 (PCINT15) PJ5 (PCINT14) PJ4 (PCINT13) PJ3 (PCINT12) PJ2 (XCK3/PCINT11) PJ1 (TXD3/PCINT10) PJ0 (RXD3/PCINT9) GND VCC PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR) 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 AVCC AREF GND GND VCC 46 INDEX CORNER 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 PJ7 47 48 49 (OC0A/OC1C/PCINT7) PB7 VCC GND (ICP4) PL0 (RXD1/INT2) PD2 (SCL/INT0) PD0 (XCK1) PD5 (T4) PH7 (T1) PD6 (TXD1/INT3) PD3 (OC5A) PL3 (OC5B) PL4 (OC5C) PL5 (TOSC2) PG3 (TOSC1) PG4 (SDA/INT1) PD1 (ICP1) PD4 (ICP5) PL1 (T0) PD7 PL6 (T5) PL2 XTAL2 RESET XTAL1 PL7 2 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 10 9 8 Bottom view 7 6 5 4 3 2 1 A B C D E F G H J K Table 1-1. 1 A B C D E F G H J K Note: GND AVCC PE2 PE3 PE7 VCC GND PB3 PH7 PB7 CBGA-pinout ATmega640/1280/2560 2 AREF PG5 PE0 PE4 PH0 PH4 PB1 PB4 PG3 PG4 3 PF0 PF1 PE1 PE5 PH1 PH6 PB2 RESET PB6 VCC 4 PF2 PF3 PF4 PE6 PH3 PB0 PB5 PL1 PL0 GND 5 PF5 PF6 PF7 PH2 PH5 PL4 PL2 PL3 XTAL2 XTAL1 6 PK0 PK1 PK2 PA4 PJ6 PD1 PD0 PL7 PL6 PL5 7 PK3 PK4 PK5 PA5 PJ5 PJ1 PD5 PD4 PD3 PD2 8 PK6 PK7 PJ7 PA6 PJ4 PJ0 PC5 PC4 PC1 PD6 9 GND PA0 PA1 PA7 PJ3 PC7 PC6 PC3 PC0 PD7 10 VCC PA2 PA3 PG2 PJ2 GND VCC PC2 PG1 PG0 The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2. 3 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 1-3. Pinout ATmega1281/2561 PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PA0 (AD0) PA1 (AD1) 50 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (OC0B) PG5 (RXD0/PCINT8 /PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/CLKO/INT7) PE7 (SS/PCINT0) PB0 (SCK/ PCINT1) PB1 (MOSI/ PCINT2) PB2 (MISO/ PCINT3) PB3 (OC2A/ PCINT4) PB4 (OC1A/PCINT5) PB5 (OC1B/PCINT6) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INDEX CORNER 49 PA2 (AD2) AVCC GND AREF GND VCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (T1) PD6 (RXD1/INT2) PD2 (SCL/INT0) PD0 (TXD1/INT3) PD3 (OC0A/OC1C/PCINT7) PB7 (XCK1) PD5 (ICP1) PD4 VCC Note: The large center pad underneath the QFN/MLF package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. (SDA/INT1) PD1 (TOSC2) PG3 (TOSC1) PG4 (T0) PD7 GND XTAL2 RESET XTAL1 32 4 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 2. Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Block Diagram PF7..0 VCC Figure 2-1. PK7..0 P J7..0 PE7..0 RESET Power Supervision POR/ BOD & RESET PORT F (8) PORT K (8) PORT J (8) PORT E (8) GND Watchdog Timer Watchdog Oscillator JTAG A/D Converter Analog Comparator USART 0 XTAL1 Oscillator Circuits / Clock Generation EEPROM Internal Bandgap reference 16 bit T/C 3 XTAL2 CPU 16 bit T/C 5 USART 3 P A7..0 PORT A (8) 16 bit T/C 4 USART 1 PG5..0 PORT G (6) XRAM FLASH SRAM 16 bit T/C 1 PC7..0 PORT C (8) TWI SPI 8 bit T/C 0 8 bit T/C 2 USART 2 NOTE: Shaded parts only available in the 100-pin version. Complete functionality for the ADC, T/C4, and T/C5 only available in the 100-pin version. PORT D (8) PORT B (8) PORT H (8) PORT L (8) PD7..0 PB7..0 PH7..0 PL7..0 5 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read- W hile- W rite capabilities, 4Kbytes EEPROM, 8 Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE® std. 1149.1 compliant JTAG test interface, also used for accessing the Onchip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheelsfunctionality into AVR microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent KeySuppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 6 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1 summarizes the different configurations for the six devices. Table 2-1. Device ATmega640 ATmega1280 ATmega1281 ATmega2560 ATmega2561 Configuration Summary Flash 64KB 128KB 128KB 256KB 256KB EEPROM 4KB 4KB 4KB 4KB 4KB RAM 8KB 8KB 8KB 8KB 8KB General Purpose I/O pins 86 86 54 86 54 16 bits resolution PWM channels 12 12 6 12 6 Serial USARTs 4 4 2 4 2 ADC Channels 16 16 8 16 8 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 78. special features of the 2.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 79. special features of the 2.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up 7 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on page 82. 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 83. 2.3.7 special features of the Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 86. special features of the 2.3.8 Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.3.9 Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 90. special features of the 2.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up 8 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 92. 2.3.11 Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 94. 2.3.12 Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter. Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port K also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 96. 2.3.13 Port L (PL7..PL0) Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 98. 2.3.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 372. Shorter pulses are not guaranteed to generate a reset. 2.3.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.16 XTAL2 Output from the inverting Oscillator amplifier. 9 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 2.3.17 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter. 10 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 3. Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85°C or 100 years at 25°C. 6. Capacitive touch sensing The Atmel®QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR ® m icrocontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. 11 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 7. Register Summary Address (0x1FF) ... (0x13F) (0x13E) (0x13D) (0x13C) (0x13B) (0x13A) (0x139) (0x138) (0x137) (0x136) (0x135) (0x134) (0x133) (0x132) (0x131) (0x130) (0x12F) (0x12E) (0x12D) (0x12C) (0x12B) (0x12A) (0x129) (0x128) (0x127) (0x126) (0x125) (0x124) (0x123) (0x122) (0x121) (0x120) (0x11F) (0x11E) (0x11D) (0x11C) (0x11B) (0x11A) (0x119) (0x118) (0x117) (0x116) (0x115) (0x114) (0x113) (0x112) (0x111) (0x110) (0x10F) (0x10E) (0x10D) (0x10C) (0x10B) (0x10A) (0x109) (0x108) (0x107) (0x106) (0x105) (0x104) (0x103) (0x102) (0x101) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR3 UBRR3H UBRR3L Reserved UCSR3C UCSR3B UCSR3A Reserved Reserved OCR5CH OCR5CL OCR5BH OCR5BL OCR5AH OCR5AL ICR5H ICR5L TCNT5H TCNT5L Reserved TCCR5C TCCR5B TCCR5A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTL DDRL PINL PORTK DDRK PINK PORTJ DDRJ PINJ PORTH DDRH Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - Page USART3 I/O Data Register UMSEL31 RXCIE3 RXC3 UMSEL30 TXCIE3 TXC3 UPM31 UDRIE3 UDRE3 UPM30 RXEN3 FE3 USBS3 TXEN3 DOR3 USART3 Baud Rate Register High Byte UCSZ31 UCSZ32 UPE3 UCSZ30 RXB83 U2X3 UCPOL3 TXB83 MPCM3 USART3 Baud Rate Register Low Byte 222 227 227 239 238 238 Timer/Counter5 - Output Compare Register C High Byte Timer/Counter5 - Output Compare Register C Low Byte Timer/Counter5 - Output Compare Register B High Byte Timer/Counter5 - Output Compare Register B Low Byte Timer/Counter5 - Output Compare Register A High Byte Timer/Counter5 - Output Compare Register A Low Byte Timer/Counter5 - Input Capture Register High Byte Timer/Counter5 - Input Capture Register Low Byte Timer/Counter5 - Counter Register High Byte Timer/Counter5 - Counter Register Low Byte FOC5A ICNC5 COM5A1 PORTL7 DDL7 PINL7 PORTK7 DDK7 PINK7 PORTJ7 DDJ7 PINJ7 PORTH7 DDH7 FOC5B ICES5 COM5A0 PORTL6 DDL6 PINL6 PORTK6 DDK6 PINK6 PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 FOC5C COM5B1 PORTL5 DDL5 PINL5 PORTK5 DDK5 PINK5 PORTJ5 DDJ5 PINJ5 PORTH5 DDH5 WGM53 COM5B0 PORTL4 DDL4 PINL4 PORTK4 DDK4 PINK4 PORTJ4 DDJ4 PINJ4 PORTH4 DDH4 WGM52 COM5C1 PORTL3 DDL3 PINL3 PORTK3 DDK3 PINK3 PORTJ3 DDJ3 PINJ3 PORTH3 DDH3 CS52 COM5C0 PORTL2 DDL2 PINL2 PORTK2 DDK2 PINK2 PORTJ2 DDJ2 PINJ2 PORTH2 DDH2 CS51 WGM51 PORTL1 DDL1 PINL1 PORTK1 DDK1 PINK1 PORTJ1 DDJ1 PINJ1 PORTH1 DDH1 CS50 WGM50 PORTL0 DDL0 PINL0 PORTK0 DDK0 PINK0 PORTJ0 DDJ0 PINJ0 PORTH0 DDH0 165 165 165 165 164 164 165 165 163 163 162 160 158 104 104 104 103 103 103 103 103 103 102 103 12 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Address (0x100) (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR2 UBRR2H UBRR2L Reserved UCSR2C UCSR2B UCSR2A Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved Bit 7 PINH7 UMSEL21 RXCIE2 RXC2 UMSEL11 RXCIE1 RXC1 UMSEL01 RXCIE0 RXC0 - Bit 6 PINH6 UMSEL20 TXCIE2 TXC2 UMSEL10 TXCIE1 TXC1 UMSEL00 TXCIE0 TXC0 - Bit 5 PINH5 UPM21 UDRIE2 UDRE2 UPM11 UDRIE1 UDRE1 UPM01 UDRIE0 UDRE0 - Bit 4 PINH4 UPM20 RXEN2 FE2 UPM10 RXEN1 FE1 UPM00 RXEN0 FE0 - Bit 3 PINH3 - Bit 2 PINH2 - Bit 1 PINH1 - Bit 0 PINH0 - Page 103 - - USART2 I/O Data Register USART2 Baud Rate Register High Byte USBS2 TXEN2 DOR2 UCSZ21 UCSZ22 UPE2 UCSZ20 RXB82 U2X2 UCPOL2 TXB82 MPCM2 USART2 Baud Rate Register Low Byte 222 227 227 239 238 238 222 USART1 Baud Rate Register High Byte 227 227 UCSZ11 UCSZ12 UPE1 UCSZ10 RXB81 U2X1 UCPOL1 TXB81 MPCM1 222 USART0 Baud Rate Register High Byte 227 227 UCSZ01 UCSZ02 UPE0 UCSZ00 RXB80 U2X0 UCPOL0 TXB80 MPCM0 239 238 238 239 238 238 USART1 I/O Data Register USART1 Baud Rate Register Low Byte USBS1 TXEN1 DOR1 - USART0 I/O Data Register USART0 Baud Rate Register Low Byte USBS0 TXEN0 DOR0 - 13 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A Reserved Reserved OCR4CH OCR4CL OCR4BH OCR4BL OCR4AH OCR4AL ICR4H ICR4L TCNT4H TCNT4L Reserved TCCR4C TCCR4B TCCR4A Reserved Reserved OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 DIDR2 Bit 7 TWAM6 TWINT TWA6 TWS7 - Bit 6 TWAM5 TWEA TWA5 TWS6 EXCLK - Bit 5 TWAM4 TWSTA TWA4 TWS5 AS2 - Bit 4 TWAM3 TWSTO TWA3 TWS4 TCN2UB - Bit 3 TWAM2 TWWC TWA2 TWS3 OCR2AUB - Bit 2 TWAM1 TWEN TWA1 OCR2BUB - Bit 1 TWAM0 TWA0 TWPS1 TCR2AUB - Bit 0 TWIE TWGCE TWPS0 TCR2BUB - Page 269 266 268 269 268 266 184 191 191 191 2-wire Serial Interface Data Register 2-wire Serial Interface Bit Rate Register Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A Timer/Counter2 (8 Bit) FOC2A COM2A1 FOC2B COM2A0 COM2B1 COM2B0 WGM22 CS22 CS21 WGM21 CS20 WGM20 - 190 191 Timer/Counter4 - Output Compare Register C High Byte Timer/Counter4 - Output Compare Register C Low Byte Timer/Counter4 - Output Compare Register B High Byte Timer/Counter4 - Output Compare Register B Low Byte Timer/Counter4 - Output Compare Register A High Byte Timer/Counter4 - Output Compare Register A Low Byte Timer/Counter4 - Input Capture Register High Byte Timer/Counter4 - Input Capture Register Low Byte Timer/Counter4 - Counter Register High Byte Timer/Counter4 - Counter Register Low Byte FOC4A ICNC4 COM4A1 FOC4B ICES4 COM4A0 FOC4C COM4B1 WGM43 COM4B0 WGM42 COM4C1 CS42 COM4C0 CS41 WGM41 CS40 WGM40 - 164 164 164 164 164 164 165 165 163 163 162 160 158 Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte FOC3A ICNC3 COM3A1 FOC3B ICES3 COM3A0 FOC3C COM3B1 WGM33 COM3B0 WGM32 COM3C1 CS32 COM3C0 CS31 WGM31 CS30 WGM30 - 164 164 164 164 163 163 165 165 162 162 162 160 158 Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte FOC1A ICNC1 COM1A1 ADC7D ADC15D FOC1B ICES1 COM1A0 ADC6D ADC14D FOC1C COM1B1 ADC5D ADC13D WGM13 COM1B0 ADC4D ADC12D WGM12 COM1C1 ADC3D ADC11D CS12 COM1C0 ADC2D ADC10D CS11 WGM11 AIN1D ADC1D ADC9D CS10 WGM10 AIN0D ADC0D ADC8D 163 163 163 163 163 163 165 165 162 162 161 160 158 274 295 295 14 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) Name ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved XMCRB XMCRA TIMSK5 TIMSK4 TIMSK3 TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 EICRB EICRA PCICR Reserved OSCCAL PRR1 PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL EIND RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR Bit 7 REFS1 ADEN Bit 6 REFS0 ACME ADSC Bit 5 ADLAR ADATE Bit 4 MUX4 ADIF Bit 3 MUX3 MUX5 ADIE Bit 2 MUX2 ADTS2 ADPS2 Bit 1 MUX1 ADTS1 ADPS1 Bit 0 MUX0 ADTS0 ADPS0 Page 289 272, 290, 294 292 294 294 ADC Data Register High byte ADC Data Register Low byte XMBK SRE PCINT23 PCINT15 PCINT7 ISC71 ISC31 PRTWI CLKPCE WDIF I SP15 SP7 SPMIE JTD OCDR7 ACD SPIF SPIE SRL2 PCINT22 PCINT14 PCINT6 ISC70 ISC30 PRTIM2 WDIE T SP14 SP6 RWWSB OCDR6 ACBG WCOL SPE SRL1 ICIE5 ICIE4 ICIE3 ICIE1 PCINT21 PCINT13 PCINT5 ISC61 ISC21 PRTIM5 PRTIM0 WDP3 H SP13 SP5 SIGRD OCDR5 ACO DORD SRL0 PCINT20 PCINT12 PCINT4 ISC60 ISC20 PRTIM4 WDCE S SP12 SP4 RWWSRE PUD JTRF OCDR4 ACI MSTR SRW11 OCIE5C OCIE4C OCIE3C OCIE1C PCINT19 PCINT11 PCINT3 ISC51 ISC11 PRTIM3 PRTIM1 CLKPS3 WDE V SP11 SP3 BLBSET WDRF SM2 OCDR3 ACIE SPI Data Register CPOL CPHA SPR1 SPI2X SPR0 XMM2 SRW10 OCIE5B OCIE4B OCIE3B OCIE2B OCIE1B OCIE0B PCINT18 PCINT10 PCINT2 ISC50 ISC10 PCIE2 PRUSART3 PRSPI CLKPS2 WDP2 N SP10 SP2 PGWRT BORF SM1 OCDR2 ACIC XMM1 SRW01 OCIE5A OCIE4A OCIE3A OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 ISC41 ISC01 PCIE1 PRUSART2 PRUSART0 CLKPS1 WDP1 Z SP9 SP1 RAMPZ1 PGERS IVSEL EXTRF SM0 OCDR1 ACIS1 XMM0 SRW00 TOIE5 TOIE4 TOIE3 TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 ISC40 ISC00 PCIE0 - 38 37 166 166 166 193 166 134 116 116 117 114 113 115 50 Oscillator Calibration Register PRUSART1 PRADC CLKPS0 WDP0 C SP8 SP0 EIND0 RAMPZ0 SPMEN IVCE PORF SE OCDR0 ACIS0 - 57 56 50 67 14 16 16 17 17 332 67, 110, 100, 308 308 52 301 272 204 203 202 37 37 General Purpose I/O Register 2 General Purpose I/O Register 1 Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM FOC0B COM0A0 COM0B1 COM0B0 EEPROM Data Register INT7 INTF7 INT6 INTF6 EEPM1 INT5 INTF5 EEPM0 INT4 INTF4 EERIE INT3 INTF3 EEMPE INT2 INTF2 PCIF2 EEPE INT1 INTF1 PCIF1 EERE INT0 INTF0 PCIF0 General Purpose I/O Register 0 WGM02 CS02 CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC 133 133 133 132 129 170, 194 35 35 35 35 37 115 115 116 EEPROM Address Register High Byte EEPROM Address Register Low Byte 15 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Address 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name TIFR5 TIFR4 TIFR3 TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 Bit 6 PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 Bit 5 ICF5 ICF4 ICF3 ICF1 PORTG5 DDG5 PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 Bit 4 PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 Bit 3 OCF5C OCF4C OCF3C OCF1C PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 Bit 2 OCF5B OCF4B OCF3B OCF2B OCF1B OCF0B PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 Bit 1 OCF5A OCF4A OCF3A OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page 166 167 167 193 167 134 102 102 102 101 102 102 101 101 102 101 101 101 101 101 101 100 100 100 100 100 100 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 16 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 8. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP EIJMP JMP RCALL ICALL EICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, C, N, V Z, C, N, V, H Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V None Z, C Z, C Z, C Z, C Z, C Z, C None None None None None None None None None I None Z, N, V, C, H Z, N, V, C, H Z, N, V, C, H None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 4 4 4 5 5 5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Extended Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Extended Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr 1 R1:R0 ← (Rd x Rr)