MMKR-26C516E-31-E

29C516E 16–Bit Flow–Through EDAC Error Detection And Correction unit 1. Introduction The 29C516E Atmel EDAC is a very low power flow–through 16–bit Error Detection And Correction unit (EDAC) with two user data buses. The EDAC is used in a high integrity system for monitoring and correction of data values coming from the memory space. During a processor write cycle, at each memory location (16–bit width), EDAC calculated checkword (6 or 8–bit width) is added. When performing a read operation from memory, the 29C516E verifies the entire checkword and data combination. It detects and can correct 100% of all the single–bit errors and it detects all double–bit errors. When the 29C516E uses 6–checkbit, it can detect any error on any single 4–bit memory chip. The 8–check–bit option gives the additional capability to detect all errors on any single 8–bit memory chip. All the errors are signaled to the master system (via 2 error Flags) in order to allow the processor to make the required action. The 29C516E operates in two possible modes: corrected or detected mode. In the corrected mode, the single–bit in error is complemented (corrected). Then, the available entire data is placed on the output port and the Correctable Error Flag is set. In case of double–bit errors (or more), the corrupted data is placed on the output port and the Uncorrectable Error Flag is set. Note that when there is more than two errors, then some bit patterns may appear as possible correctable errors. Therefore, if the environment produces this type of error, the EDAC must be used in detect and provide no automatic correction. Data and syndrome analysis must be done. The 29C516E acts as a data buffer for µP–memory interfacing. A flow–through EDAC is placed in the data bus path, between the processor and the memory to be protected. This component is able to serve two different users of one memory space. So, it forms the interface between the 22/24–bit (16+6/16+8) memory data bus and the two 16–bit processor data busses with a high drive capability (–12.8 mA). The two data ports can be used to create a dual port bus in front of memory space. The User–1(2) can transfer data from/to the memory or from/to the User–2(1), by–passing the memory. During read or write memory cycles processed by the User–1(2), the User–2(1) have the possibility to listen the transferred data. 2. Features D D D D D D D D Very Low Power CMOS 16–Bit operation with 6 or 8 Check Bits Fast Error Detection : 31 ns (max.) Fast Error Correction : 32 ns (max.) Corrects all Single–Bit Errors Detects all Double–Bit Errors Detects some Multi–Bit Errors Detects Chip Errors (x1, x4 & x8 RAM Format) D D D D D D D Correctable and Uncorrectable Error Flags Two User Data Buses User to User Transfer and Listening operation High Drive Capability on Buses : –12.8 mA TTL Compatible Single 5V ±10% Power Supply 100 Pin Multilayer Quad Flat Pack (Flat leaded or L leaded). Atmel Corporation Rev. E (03 2007) 1 29C516E 3. Interface 3.1. Functional Diagram Figure 1.Functional Diagram 8 CORRECT SYNCHK MEM1 EN1 RD/WR1 CHECK BIT GENERATOR 16 I/O BUFFER 8 MC[0..7] 8 U1D[0..15] U2/U1 TRANS U2D[0..15] 16 16 I/O BUFFER 16 CONTROLLER 16 16 I/O BUFFER 16 29C516E RD/WR2 EN2 MEM2 16 16 16 I/O BUFFER 16 MD[0..15] CERR NCERR N22 SYNDROME DECODER 8 SYNDROME GENERATOR 3.2. Block Diagram Figure 2.Block Diagram VCC CORRECT SYNCHK N22 U1/U2 TRANS U1D[0..15] MC[0..7] EN1 MEM1 RD/WR1 MD[0..15] U2D[0..15] EN2 MEM2 RD/WR2 GND 29C516E CERR NCERR 2 Rev. E (03 2007) 29C516E 3.3. Pin Configuration for multilayer quad Flat–pack (flat or L leaded) Figure 3.Pin Configuration index corner nc nc MEM2 Gnd U2D[15] U2D[14] U2D[13] U2D[12] Vcc U2D[11] U2D[10] U2D[9] U2D[8] Gnd U2D[7] U2D[6] U2D[5] U2D[4] Vcc U2D[3] U2D[2] U2D[1] U2D[0] Gnd NCERR CERR N22 U1D[15] nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 Vcc RD/WR2 CORRECT SYNCHK TRANS U2/U1 EN2 Gnd Gnd MC[7] MC[6] MC[5] MC[4] Vcc MC[3] MC[2] MC[1] MC[0] nc nc MQFPF100 or MQFPL100 (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc nc Gnd MD[15] MD[14] MD[13] MD[12] Vcc MD[11] MD[10] MD[9] MD[8] Gnd MD[7] MD[6] MD[5] MD[4] Vcc MD[3] MD[2] MD[1] MD[0] Gnd MEM1 EN1 RD/WR1 Vcc U1D[0] nc nc nc Vcc U1D[14] U1D[13] U1D[12] Gnd U1D[11] U1D[10] U1D[9] U1D[8] Vcc U1D[7] U1D[6] U1D[5] U1D[4] Gnd U1D[3] U1D[2] U1D[1] nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev. E (03 2007) 3 29C516E 3.4. Pin Description Table 1: Name Pin Description I/O Active Description Buses U1D[0..15] U2D[0..15] ΜD[0..15] ΜC[0..7] Error Flags CERR NCERR 26 25 O O Low Low Correctable Error Uncorrectable Error 53,49..47,45..42,40..37,35..33,28 23..20,18..15,13..10,8..5 59..62,64..67,69..72,74..77 83..86,88..91 I/O* I/O* I/O* I/O* High High High High User 1 Data Bus User 2 Data Bus Memory Data Bus Memory Check–bit Bus General Control Signals CORRECT SYNCHK N22 TRANS 98 97 27 96 I* I* I* I* High Low High H/L When active, the EDAC is in CORRECT mode. If low, the EDAC is in DETECT mode. Selects the Syndrome bits (high byte) and the Check–bits (low byte) to be driven on the selected User Data Bus. When active, the EDAC uses 6 check–bits. If low, the EDAC uses 8 check–bits in memory read. Selects the Data path to be used. If high, the EDAC access the memory, if low, the EDAC access the transfer buffer. Selects who is the master of User 1 and User 2. The master is responsible for applying RD/WRx, MEMx, and ENx signals in a correct way. U2/U1 95 I* H/L User 1 Control Signals RD/WRT EN1 MEM1 55 56 57 I* I* I* H/L Low Low User 1 Read/Write signal User 1 Output Enable User 1 Memory Select User 1 Control Signals RD/WR2 EN2 MEM2 Power (Buffers) VCCB GNDB Power (Core) VCCC GNDC 100 93 I I – – Core supply (5 V nominal) Core 0 V reference 9,19,32,41,54,63,73,87 4,14,24,36,46,58,68,78,92 I I – – Buffers supply (5 V nominal) Buffers 0 V nominal reference 99 94 3 I* I* I* H/L Low Low User 2 Read/Write signal User 2 Output Enable User 2 Memory Select * Pull–up buffers 4 Rev. E (03 2007) 29C516E 4. Check–Bit Generation The Check–bit Generator produces 8 check–bits (whatever N22 value) from the incoming User Data Word UxD[0..15] according the Table 2. Example: to create check–bit 0, bit 13, 12, 8, 7, 6, 5, 4 and 0 of the Data Word are XORed together. If memory devices 8–bit wide are used, 24 bits (MD[0..15] & MC[0..7]) are stored to give error detection. But if memory devices 1–bit or 4–bit wide are used, 22 bits (MD[0..15] & MC[0..5]) are stored to give error detection. Table 2: Check Bit Generation (indicates a bit of UxD bus used in the XOR/NXOR) MC[..] PARITY 15 0 1 2 3 Even(XOR) Even(XOR) Odd(NXOR) Odd(NXOR) x x x x x x 14 13 x 12 x x x x x 11 10 9 UxD[..] 8 x x 7 x 6 x x x x 5 x 4 x x x x x x x x x x x 3 2 1 0 x 4 5 6 7 Even(XOR) Even(XOR) Even(XOR) Odd(NXOR) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 5. Syndrome Generation The syndrome Generator produces 8 syndrome–bits (whatever N22 value) from the incoming Memory Data Word MD[0..15] and the associated Check–bits MC[0..7] (or MC[0..5]) according the Table 3. Syndrome–bit SY[x] is the XOR of the generated Check–bit MC[x] with the generation of Chek–bit on MD[..]. Example: to create syndrome–bit 3, first the bit 14, 13, 10, 4, 3, 2, 1 and 0 of the Data Word (MD[14,13,10,4,3,2,1,0]) are NXORed. Then, the result is XORed with the associated Check–bit (MC[3]) of the Check–byte read in the same time as Data Word is checked. If the memory uses x8 devices, then the bits should be physically divided as follows: MC[0..7], MD[0..7] and MD[8..15] . For x4 organization, the bits should be divided MC[0..2]+MC[6], MC[3..5]+MC[7], MD[0..3], MD[4..7], MD[8..11] and MD[12..15]. Table 3: Syndrome Bit Generation (indicates a bit of MD and MC buses used in the XOR/NXOR) SY[..] PARITY 15 0 1 2 3 EVEN(XOR) EVEN(XOR) ODD(NXOR) ODD(NXOR) x x x x x x 14 13 x 12 x x x x x 11 10 9 MD[..] 8 x x 7 x 6 x x x x 5 x 4 x x x x x x x x x x x x x 3 2 1 0 x x 7 5 4 MC[..] 3 6 2 1 0 x 4 5 EVEN(XOR) EVEN(XOR) x x x x x x x x x x x x x x x x x x 6 7 EVEN(XOR) ODD(NXOR) x x x x x x x x x x x x x x x x x x Rev. E (03 2007) 5 29C516E 6. Syndrome Decoding The syndrome decoder generates the error flags CERR (Correctable ERRor) and NCERR (Non–Correctable ERRor). If a correctable error occurs, the 29C516E EDAC provides corrected data to the user. The inputs are the 8 syndrome bits from the syndrome generator, the 16 data bits from the memory and the control signal N22. N22 signal controls if 22 or 24 bits shall be decode from the entire memory word. Table 4: 6–Bit Syndrome Word to Bit–In–Error (N22=”1”) Hex Syndrome Bit SY[..] 5 4 Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 N.E.D MC0 MC1 D MC2 D D M MC3 D D MD4 D MD0 MD1 D MC4 D D MD8 D MD5 MD9 D D M MD10 D MD2 D D M MC5 D D MD6 D MD12 M D D MD13 MD14 D MD3 D D M D MD7 MD11 D MD15 D D M M D D M D M M D 0 0 0 1 0 1 2 1 0 3 1 1 Note : N.E.D = No Errors Detected MDx = Memory Data Bit–In–Error MCx = Memory Check Bit–In–Error D = Double–Bit–In–Error Detected M = Multi–Bit–In–Error Detected 6 Rev. E (03 2007) 29C516E Table 5: 8–Bit Syndrome Word to Bit–In–Error (N22 = ”0”) Hex 7 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 A 1 0 1 0 B 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1 Syndrome Bit SY [..] 6 5 4 Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 N.E.D MC0 MC1 D MC2 D D M MC3 D D D D MD0 M D MC4 D D D D M MD9 D D M MD10 D M D D M MC5 D D MD6 D D M D D M MD14 D D D D M D D M D D D D M M D D M D M M D MC6 D D D D D D M D D D MD4 D D D D D D D MD8 M D D D M M D D D D D M D D D D M M M D D D D D M M M M D MD7 D D M M M D D D D D M M M M MC7 D D D D D D M D M M M D D D D D M M M D D D D D M D M D D D M D D D D D MD12 M D D D D M MD3 D D M D M D D MD15 D D M M D D M D M M D D M M D M D D M M D D D D M MD1 D M D D D D MD5 M D D M M M MD2 D D M M D D M D D M D D MD13 M D D D D M D D MD11 D D D D M M D D M D M M D Note : N.E.D = No Errors Detected MDx = Memory Data Bit–In–Error MCx = Memory Check Bit–In–Error D = Double–Bit–In–Error Detected M = Multi–Bit–In–Error Detected 7. The 6–Bit Syndrome Word This feature is available when the N22 pin is driven at a high level. 7.1. No Errors If there are no errors in the read Data or Check–Bit, all the syndrome byte is ”00”. The EDAC flags are inactive. No Error : SY=00 7.2. Single Bit–Error A single bit–error in a Memory Data word read (MD[..]) causes three syndrome bits to be set to one. The code formed indicates which bit of the Memory Data word is incorrect. For example, if MD[2] were incorrect, the syndrome byte would have bits 2, 3 and 4 set to one. The syndrome decoder of 29C516E EDAC decodes the information in the syndrome byte and only sets low the error flag CERR. In correct mode (CORRECT pin active), it inverts (and hence corrects) the relevant bit in error of the Memory Rev. E (03 2007) Data word and provides the expected Data word for the EDAC controller. If there is an error in the Memory Check–bit (MC[..]), only one bit of the syndrome is set to one. In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR does not change. It does not correct the Check–bit because these bits are not used by the system. 7 29C516E Table 6: Single Bit–Error MD[..] SY(hexa) [15] 34h [14] 2Ah [13] 29h [12] 25h [11] 32h [10] 1Ah [9] 16h [8] 13h [7] 31h [6] 23h [5] 15h [4] 0Bh [3] 2Ch [2] 1Ch [1] 0Eh [0] 0Dh MC[..] SY(hexa) [– ] ––h [– ] ––h [5 ] 20h [4 ] 10h [3 ] 08h [2 ] 04h [1 ] 02h [0 ] 01h 7.3. Double–Bit Error If two errors occurs, there will be either 2, 4 or 6 bits set to one in the syndrome byte. The syndrome value generated by a double–bit error does not take place of a syndrome value generated by a single–bit error. Then, only the non correctable error flag NCERR will be activated to indicate that errors are present but cannot be corrected. Example: If MD[4] and MC[2] are incorrect, syndrome bits [0], [1], [2] and [3] are set to one (SY=0Fh ), NCERR is set low and CERR remains at high level. 7.4. Triple–Bit Error Triple–Bit Error When three errors are detected, an error flag is set low as warning to the system. But the generated syndrome can have the listed value of single–bit error. The device must be in detect mode to prevent false correction occurring. Example: If MD[0], MD[14] and MC[1] are corrupted, the syndrome value is ”25h ”. This is decoded by the 29C516E EDAC as being a correctable error on MD[12]. The CERR flag is set low and correction would take place if the device is in correct mode. This would cause more errors. 7.5. 4–bit Wide Memory Error The 6 check–bit code can be used to provide error detection for up to 4 errors occurring in the following groups: MD[15..12], MD[11..8], MD[7..4], MD[3..0], MC[5..3] and MC[2..0]. The 29C516E EDAC can flag any number of errors in 4–bit wide memory chip. A special attention must be taken, multi–bit error ( 3) located into the defined groups can provide the syndrome byte of a single–bit error. Example: If MD[3], MD[2], MD[1] and MD[0] are in error, the syndrome code is ”33 h ”; 8. The 8–Bit Syndrome Word This feature is available when the N22 pin is driven at a low level. 8.1. No Errors If there are no errors in the read Data or Check–Bit, all the syndrome byte is ”00”. The EDAC flags are inactive. No Error : SY=00 8.2. Single Bit–Error Single Bit–Error A single bit–error in a Memory Data word read (MD[..]) causes three syndrome bits to be set to one. The code formed indicates which bit of the Memory Data word is incorrect. For example, if MD[10] were incorrect, the syndrome byte would have bits 1, 3 and 4 set to one. The syndrome decoder of 29C516E EDAC decodes the information in the syndrome byte and only sets low the error flag CERR. In correct mode (CORRECT pin active), it inverts (and hence corrects) the relevant bit in error of the Memory 8 Data word and provides the expected Data word for the EDAC controller. If there is an error in the Memory Check–bit (MC[..]), only one bit of the syndrome is set to one. In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR does not change. It does not correct the Check–bit because these bits are not used by the system. Rev. E (03 2007) 29C516E Table 7: Single Bit Error MD[..] SY(hexa) [15] 34h [14] 2Ah [13] 29h [12] 25h [11] 32h [10] 1Ah [9] 16h [8] 13h [7] 31h [6] 23h [5] 15h [4] 0Bh [3] 2Ch [2] 1Ch [1] 0Eh [0] 0Dh MC[..] SY(hexa) [– ] ––h [– ] ––h [5 ] 20h [4 ] 10h [3 ] 08h [2 ] 04h [1 ] 02h [0 ] 01h 8.3. Double–Bit Error If two errors occur, there will be 2, 3, 4, 5, 6 or 8 bits set to one in the syndrome byte. The syndrome value generated by a double–bit error does not take place of a syndrome value generated by a single–bit error. Then, only the non correctable error flag NCERR will be activated to indicate that errors are present but cannot be corrected. Example: If MD[5] and MC[7] are incorrect, syndrome bits [0], [2], [4] and [6] are set to one (SY=55h ), NCERR is set low and CERR remains at high level. 8.4. Triple–Bit Error When three errors are detected, an error flag is set low as warning to the system. But the generated syndrome can have the listed value of single–bit error. The device must be in detect mode to prevent false correction occurrence. Example: If MD[0], MD[9] and MC[0] are corrupted, the syndrome value is ”1Ah ”. This is decoded by the 29C516E EDAC as being a correctable error on MD[10]. The CERR flag is set low and correction would take place if the device is in correct mode. This would cause more errors. 8.5. 4–bit Wide Memory Error The 8 check–bit code can be used to provide error detection for up to 4 errors occur in the following groups: MD[15..12], MD[11..8], MD[7..4], MD[3..0], MC[7..4] and MC[3..0]. The 29C516E EDAC can flag any number of errors in 4–bit wide memory chip. A special attention must be taken, multi–bit error ( 3) located into the defined groups can provide the syndrome byte of a single–bit error. Example: If MD[11], MD[10], MD[9] and MD[8] are in error, the syndrome code is ”AD h ”. 8.6. 8–bit Wide Memory Error The 8 check–bit code can be used to provide error detection for up to 8 errors occurring in the following groups: MD[15..8], MD[7..0] and MC[7..0]. The 29C516E EDAC can flag any number of errors in 8–bit wide memory chip. A special attention must be taken, multi–bit error ( 3) located into the defined groups can provide the syndrome byte of a single–bit error. Example: If MD[13], MD[12], MD[10] and MD[9] are in error, the syndrome code is ”40h ”. (In 6 check–bit coding, the syndrome code should have been ”00h ”, the ”No Error Detected” value.) Note that the syndrome code ”40 h ” is also the code for MC[6] in error. 9. Transactions Transactions Three types of transactions may be done: 9.1. Memory Read The TRANS pin is driven at a high level to select the access to the memory. The external arbiter drives the U2/U1 pin and dispatches the commands RD/WRx, MEMx and ENx. All transaction managed by the master user can be listened by the second user. 9 Rev. E (03 2007) 29C516E Table 8: CORRECT SYNCHK RD/WR1 RD/WR2 TRANS NCERR MEM1 MEM2 CERR U2/U1 EN1 EN2 Function UD1[0..15] = MD[0..15] UD1[0..15] = {corrected MD[0..15]} UD1[0..15] = {corrupted MD[0..15]} UD1[0..15] = MD[0..15] UD1[0..15] = {MC[0..7]  Syndrome} UD1[0..15] = H.Z UD2[0..15] = {expected UD1[0..15]} (User 2 listening) UD2[0..15] = MD[0..15] UD2[0..15] = {corrected MD[0..15]} UD2[0..15] = {corrupted MD[0..15]} UD2[0..15] = MD[0..15] UD2[0..15] = {MC[0..7] Syndrome} UD2[0..15] = H.Z UD1[0..15] = {expected UD2[0..15]} (User 1 listening) 1 1 1 1 0 0 x x x 0 x 0 1 0 x 1 0 1 0 1 1 x x 1 x x 0 x 1 x x 1 x 0 x 0 x x 1 1 1 x x x 1 0 0 0 x 0 1 1 x 1 0 x x x 1 0 1 x x x 1 0 0 1 x x 1 x x 0 x 1 x x x x x x x x 1 1 0 x x x 1 1 0 x x x x : don’t care 9.2. Memory Write The TRANS pin is driven at a high level to select the access to the memory. The external arbiter drives the U2/U1 pin and dispatches the commands RD/WRx, Table 9: RD/WR1 TRANS RD/WR2 MEM1 MEM2 MEMx and ENx. All transaction managed by the master user can be listened by the second user. U2/U1 EN1 EN2 Function MD[0..15] = UD1[0..15] MC[0..7] = {check–bits generated from UD1[0..15]} MD[0..15] = H.Z MC[0..7] = H.Z UD2[0..15] = UD1[0..15] (User 2 listening) MD[0..15] = UD2[0..15] MC[0..7] = {check–bits generated from UD2[0..15]} MD[0..15] = H.Z MC[0..7] = H.Z UD1[0..15] = UD2[0..15] (User 1 listening) 0 1 0 0 0 x 1 1 x 1 0 1 x x x x 0 0 x 1 x x x 0 x x 1 0 0 0 x x 0 0 1 x x x x 0 0 x 1 x x : don’t care CERR and NCERR are not valid CORRECT and SYNCHK are not active 10 Rev. E (03 2007) 29C516E 9.3. User to User Transfer The TRANS pin is driven at a low level to select this mode. The external arbiter drives the U2/U1 pin and Table 10: RD/WR1 TRANS RD/WR2 MEM2 MEM1 dispatches the unidirectional commands RD/WRx, MEMx and ENx. U2/U1 EN1 EN2 Function UD1[0..15] = UD2[0..15] UD1[0..15] = H.Z UD2[0..15] = UD1[0..15] UD2[0..15] = H.Z UD2[0..15] = UD1[0..15] UD2[0..15] = Η.Ζ UD1[0..15] = UD2[0..15] UD1[0..15] = H.Z 0 1 0 0 0 1 x 0 1 x 1 x 0 1 x 0 x x x x x x x x 0 x x x x 1 x 0 1 x 0 1 0 1 x x x 0 1 x 0 1 x x : don’t care CERR and NCERR are not valid CORRECT and SYNCHK are not active 11 Rev. E (03 2007) 29C516E 10. Signal Timing 10.1. Memory Write Figure 4.Memory Write Timing Diagram U2/U1 N22 t13 t20 t22 t22 t22 t20 MD[0..15] t14 t20 t22 t22 t22 t20 MC[0..7] UD2[0..15] 1.5TRANS 1.5 1.5 t2 Memory Data Word t19 t23 t23 t23 t3 2.5 Generated Check–bits t21 t23 t23 t23 RD/WR2 EN2 MEM2 Propagation Delays t2 * 13 ns Output Enable / Disable Times t19 * 23 ns t3 * 26 ns t20 * 22 ns t13 * 18 ns t21 * 22 ns t14 * 30 ns t22 * 19 ns ( * : Max Value ) ( * : Max Value ) Figure 5.Transfer Write Timing Diagram U2/U1 t13 t20 t12 t22 t22 t22 t18 UD2[0..15] UD1[0..15] TRANS RD/WR1 EN1 MEM1 Propagation Delays t1 * 14 ns Output Enable / Disable Times t18 * 23 ns t12 * 20 ns t19 * 23 ns t13 * 18 ns t20 * 22 ns t21 * 22 ns t22 * 19 ns t23 * 19 ns ( * : Max Value ) ( * : Max Value ) t21 t23 t23 t23 t19 t1 12 Rev. E (03 2007) 29C516E 10.2. Memory Read Figure 6.Memory Read Timing Diagram t8 t5 t16 CERR t9 t6 t17 NCERR N22 MD[0..15] MC[0..7] CORRECT t22 t22 t22 t18 Memory Data Word Memory Check–bits t15 t4 t7 t10 Corrected Data Valid Error Flag Valid Error Flag 2.5 2.5 UD1[0..15] TRANS RD/WR2 EN2 MEM2 Propagation Delays t4 * 34 ns t9 * 32 ns t5 * 33 ns t10 * 19 ns t22 * 19 ns t6 * 34 ns t15 * 24 ns t7 * 32 ns t16 * 24 ns t8 * 31 ns t17 * 24 ns ( * : Max Value ) ( * : Max Value ) Output Enable / Disable Times t18 * 23 ns ( * : Max Value ) 13 Rev. E (03 2007) 29C516E 10.3. Transfer Read Figure 7.Transfer Read Timing Diagram U2/U1 t13 t20 t12 t22 t22 t22 t18 t1 t21 t23 t23 t23 t19 UD2[0..15] UD1[0..15] TRANS RD/WR2 EN2 MEM2 Propagation Delays t1 * 14 ns t12 * 20 ns t19 * 23 ns t13 * 18 ns t20 * 22 ns ( * : Max Value ) Output Enable / Disable Times t18 * 23 ns t21 * 22 ns t22 * 19 ns t23 * 19 ns ( * : Max Value ) 11. Electrical Characteristics 11.1. Absolute Maximum Ratings Table 11: Parameter Value Supply voltage, Vcc Input voltage range Input current per power pin Input current per signal pin Continuous output current, one pin Soldering lead temperature 1.6 mm from case for max 10 s Storage temperature Maximum package power dissipation – 0.5 to 7V – 0.5 to Vcc + 0.5 V +/– 50 mA +/– 10 mA +/– 30 mA + 300 C – 65 C to + 150 C 1.0 W 14 Rev. E (03 2007) 29C516E 11.2. Operating Conditions Table 12: Parameter Min.. Typ Max Unit Supply voltage, Vcc Operating temperature range 4.5 – 55 5.0 5.5 125 Volt C 11.3. Static Electrical Characteristics Table 13: Parameter Condition Min. Typ Max Unit VIH VIL VOH1 VOL1 VOH2 VOL2 IIL IILP IIH IIHP IOZ IOZLP IOZHP CI CIO ICCSB High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Low level input current Low level input current, (Pull–up Input) High level input current High level input current, (Pull–down Input) Output leakage current Output leakage current, (Pull–up Input) Output leakage current, (Pull–down Input) Input pin capacitance I/O pin capacitance Standby supply current 2,2 0,8 V V V 0,1 V V 0,4 V µΑ µΑ + 10 + 100 + 10 – 40 +40 + 100 8 12 + 10 + 20 µΑ µΑ µΑ µΑ µΑ pF pF µΑ IOH = – 20 ,µΑ IOL = + 20 ,µΑ IOH = – 12.8 mΑ IOL = + 12.8 mΑ Vin = Gnd Vin = Gnd Vin = Vcc Vin = Vcc Outputs disable, (Gnd