T5760

T5760 / T5761 UHF ASK/FSK Receiver Description The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel Wireless & Microcontrollers’ PLL RF transmitter T5750. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. It can be used in the frequency receiving range of f0 = 868 to 870 MHz or f0 = 902 to 928 MHz for ASK or FSK data transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz applications. Features D Fully integrated LC-VCO and PLL loop filter D Very high sensitivity with power matched LNA D 30 dB image rejection D High system IIP3 (–16 dBm), system 1-dB compression point (–25 dBm) D High large-signal capability at GSM band (blocking –30 dBm @ + 20 MHz, IIP3 = –12 dBm @ + 20 MHz) D 5 V to 20 V automotive compatible data interface D Data clock available for Manchester- and Bi-phasecoded signals D Programmable digital noise suppresion D Receiving bandwidth BIF = 600 kHz for low cost 90-ppm crystals D Low power consumption due to configurable polling D Temperature range –40°C to 105°C D ESD protection 2 kV HBM, 200 V MM D Communication to mC possible via a single bi-directional data line D Low-cost solution due to high integration level with minimum external circuitry requirements System Block Diagram UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver T5750 XTO PLL T5760/ T5761 Demod. Control 1...5 mC IF Amp Antenna VCO Antenna PLL XTO Power amp. LNA VCO Figure 1. System block diagram Ordering Information Extended Type Number T5760-TG T5760-TGQ T5761-TG T5761-TGQ Package SO20 SO20 SO20 SO20 Remarks Tube, for 868 MHz ISM band Taped and reeled, for 868 MHz ISM band Tube, for 915 MHz ISM band Taped and reeled, for 915 MHz ISM band Rev. A2, 19-Oct-00 1 (32) Preliminary Information T5760 / T5761 Pin Description Pin 1 2 Symbol SENS IC_ ACTIVE CDEM AVCC TEST 1 AGND n.c. LNAREF LNA_IN TEST 2 TEST 3 n.c. XTAL DVCC TEST 4 DATA_ CLK DGND Function Sensitivity-control resistor IC condition indicator Low = sleep mode High = active mode Lower cut-off frequency data filter Analog power supply Test pin, during operation at GND Analog ground Not connected, connect to GND High-frequency reference node LNA and mixer RF input Do not connect during operating Test pin, during operation at GND Not connected, connect to GND Crystal oscillator XTAL connection Digital power supply Test pin, during operation at DVCC Bit clock of data stream Figure 2. Pinning SO20 LNAREF LNA_IN 8 9 13 n.c. TEST 3 TEST 2 AVCC 4 17 DATA_CLK CDEM 3 18 SENS 1 20 DATA 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IC_ACTIVE 2 19 POLLING /_ON DGND TEST 1 5 AGND 6 n.c. 7 16 TEST 4 LNAGND DC ground LNA and mixer T5760/ T5761 15 DVCC 14 XTAL 12 LNAGND 10 11 Digital ground POLLSelects polling or rceiving mode ING/_ON Low: receiving mode High: polling mode DATA Data output / configuration input 20 2 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Block Diagram CDEM FSK/ASK– demodulator and data filter Rssi Limiter out RSSI IF Dem_out Data – interface DATA SENS AVCC AGND DGND DVCC POLLING/_ON Sensitivity– reduction Polling circuit and control logic Amp. DATA_CLK 4. Order f0=950 kHz/ 1 MHz FE CLK IC_ACTIVE LPF fg=2.2MHz Standby logic IF Amp. Loop– filter Poly–LPF fg=7MHz LC–VCO XTO XTAL LNAREF f f :2 :256 LNA_IN LNAGND LNA Figure 3. Block diagram RF Front End The RF front end of the receiver is a low-IF heterodyne configuration that converts the input signal into a 950-kHz/ 1-MHz IF signal with an image rejection of typical 30dB. According to figure 3 the front end consists of an LNA (low noise amplifier), LO (local oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier. The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with integrated low noise LC-VCO (voltage controlled oscillator ) and PLL-loopfilter. The XTO ( crystal oscillator ) generates the reference frequency fXTO. The integrated LC-VCO generates two times the mixer drive frequency fVCO. The I/Q signals for the mixer are generated with a divide by two circuit ( fLO = fVCO/2 ). fVCO is divided by a factor of 256 and feed into a phase frequency detector and compared with fXTO. The output of the phase frequency detector is feed into an integrated loopfilter and thereby generates the control voltage for the VCO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO / 128 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at Pin XTAL. According to figure 4, the crystal should be connected to GND with a series capacitor CL. The value of that capacitor is recommended by the crystal supplier. Due to a somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower value of CL is normally necessary. Rev. A2, 19-Oct-00 3 (32) Preliminary Information T5760 / T5761 The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO (the best way is to use a crystal with known load resonance frequency to find the right value for this capacitor) and hereby of fLO. When designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered. If a crystal with $30 ppm adjustment tolerance at 25_C , $50ppm over Temperature –40_C to 105_C, $10 ppm of total aging and a CM ( motional capacitance ) of 7 fF is used, an additional XTO pulling of $30 ppm has to be added. The resulting total LO tolerance of $120ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of $120 ppm. V S DVCC CL XTAL n.c. TEST 3 TEST 2 Figure 33 shows a typical input matching network for fRF = 868.3 MHz to 50 W. Figure 34 illustrates an according input matching for 868.3 MHz to an SAW. The input matching network shown in Figure 33 is the reference network for the parameters given in the electrical characteristics. Analog Signal Processing IF Filter The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 950 kHz for applications where fRF = 868.3 MHz and fIF =1.0 MHz for fRF = 915 MHz. The nominal bandwidth is 600 kHz. Limiting RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier, because only the hard limited signal from a high gain limiting amplifier is used by the demodulator. The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSens. RSens is connected between Pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this means it is possible to operate the receiver at a lower sensitivity. If RSens is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the Pin SENS directly to GND to get the maximum sensitivity. If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSens, the maximum sensitivity by the signal-tonoise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in figure 33 Rev. A2, 19-Oct-00 Figure 4. XTO peripherals The nominal frequency fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula (low side injection): fLO = fRF – fIF To determine fLO , the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO. fIF = fLO / 915 The relation is designed to achieve the nominal IF frequency of fIF = 950 kHz for the 868.3 MHz version. For the 915 MHz version an IF frequency of fIF = 1.0 MHz results. The RF input either from an antenna or from a RF generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well as to 50 W or an antenna more easy. 4 (32) Preliminary Information T5760 / T5761 and exhibits the best possible sensitivity and at the same time power matching at RF_IN. RSens can be connected to VS or GND via a µC. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to figure 5 is issued at Pin DATA to indicate that the receiver is still active (see also figure 32). fcu_DF + 2 p 1 30 kW CDEM In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if selfpolling is used. On the other hand CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to chapter ‘Configuration of the Receiver ’). The BR_Range must be set in accordance to the used baud-rate. The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver. DATA t DATA_min t DATA_L_max Figure 5. Steady L state limited DATA output pattern FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data signal can be detected properly, but better values are found for many modulation schemes of the competing transmitter. The FSK demodulator is intended to be used for an FSK deviation of 10 kHz ≤ Df ≤ 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signals) exceeds about 2 dB. This value is valid for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order highpass and a 2nd-order lowpass filter The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: Receiving Characteristics The RF receiver T5760/T5761 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in figures 6 and 7. This example relates to ASK mode. FSK mode exhibit similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3 dB must be considered, but the over all selectivity is much better. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the T5760/T5761. Lowcost crystals are specified to be within ±90 ppm over tolerance, temperature and aging. The XTO deviation of the T5760/T5761 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm worst case for a crystal with CM = 7 fF. If a crystal of ±90 ppm is used, the total deviation is ±120 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Rev. A2, 19-Oct-00 5 (32) Preliminary Information T5760 / T5761 0 –10 –20 –30 –40 –50 –60 –4 –3 –2 –1 0 1 2 3 4 df ( MHz ) single bi-directional line to save ports to the connected mC or it can be operated by up to five uni-directional ports. Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divide by 14 circuit. According to chapter ‘RF Front End’, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). The basic clock cycle is TClk = 14/ fXTO giving TClk = 2.066 ms for fRF = 868.3 MHz and TClk = 1.961 ms for fRF = 915 MHz TClk controls the following application-relevant parameters: D Timing of the polling circuit including bit check D Timing of the analog and digital signal processing D Timing of the register programming D Frequency of the reset marker D IF filter center frequency (fIF0) Most applications are dominated by two transmission frequencies: fTransmit = 915 MHz is mainly used in USA, fTransmit = 868.3 MHz in Europe. In order to ease the usage of all TClk-dependent parameters on this electrical characteristics display three conditions for each parameter. –9 –6 –3 0 3 6 9 12 Figure 6. Narrow band receiving frequency response 0 –20 dP ( dB ) –40 –60 –80 –100 –12 dP ( dB ) df ( MHz ) D Application USA (fXTO = 7.14063 MHz, TClk = 1.961 µs) D Application Europe (fXTO = 6.77617 MHz, TClk = 2.066 µs) D Other applications The electrical characteristic is given as a function of TClk. The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: TXClk = 8 × TClk TXClk = 4 × TClk TXClk = 2 × TClk TXClk = 1 × TClk Figure 7. Wide band receiving frequency response Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected the receiver remains active and transfers the data to the connected µC. If there is no valid signal present the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected µC is disabled during that time. All relevant parameters of the polling logic can be configured by the connected µC. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. Regarding the number of connection wires to the mC, the receiver is very flexible. It can be either operated by a 6 (32) Polling Mode According to figure 11, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the followRev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 ing bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBit-check. This period varies check by check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During TStartup and TBit-check the current consumption is IS = ISon. The condition of the receiver is indicated on Pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: I Spoll + ISoff T Sleep ) ISon (T Startup ) T Bitcheck) T Sleep ) T Startup ) T Bitcheck The following formula indicates how to calculate the preburst length. TPreburst w TSleep + TStartup + TBit-check + TStart_mC Sleep Mode The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (according to table 9), and the basic clock cycle TClk. It is calculated to be: TSleep = Sleep XSleep 1024 TClk In US- and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to’1’. According to table 8, the highest register value of sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for µC polling – via Pin POLLING/_ON, the receiver can be switched on and off. During TSleep and TStartup the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters TSleep, TStartup, TBit-check and the start-up time of a connected µC (TStart,µC). Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. Rev. A2, 19-Oct-00 7 (32) Preliminary Information T5760 / T5761 Sleep mode: All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low IS = ISoff TSleep = Sleep × XSleep × 1024 × TClk Sleep: XSleep: TClk: TStartup: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register Extension factor defined by XSleepStd according to table 9 Basic clock cycle defined by fXTO and Pin MODE Is defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. Start-up mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in stable condition and ready to receive. Output level on Pin IC_ACTIVE => high IS = ISon TStartup Bit-check mode: The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE => high IS = ISon TBit-check NO Bit check OK ? TBit-check: Depends on the result of the bit check If the bit check is ok, TBit-check depends on the number of bits to be checked (NBit-check) and on the utilized data rate. If the bit check fails, the average time period for that check depends on the selected baud-rate range and on TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. YES Receiving mode: The receiver is turned on permanently and passes the data stream to the connected mC. It can be set to Sleep mode through an OFF command via Pin DATA or POLLING/_ON. Output level on Pin IC_ACTIVE => high IS = ISon OFF command Figure 8. Polling mode flow chart ( Number of checked Bits: 3 ) Bit check ok IC_ACTIVE Bit check Dem_out Data_out (DATA) 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit TStart–up Start–up mode TBit–check Bit–check mode Receiving mode Figure 9. Timing diagram for complete successful bit check 8 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Bit-Check Mode In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. Configuring the Bit Check Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in the OPMODE register. This implies 0, 6, 12 and 18 edge to edge checks respectively. If NBit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 12 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA. According to figure 13, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds TLim_max, the bit check will be terminated and the receiver switches to sleep mode. 1/fSig tee TLim_min TLim_max ing a fixed frequency at a 50% duty cycle for the transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ± 25% regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. The bit-check limits are determined by means of the formula below. TLim_min = Lim_min × TXClk TLim_max = (Lim_max –1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the chapter ‘Receiving Mode’. The lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (NBit-check) to prevent switching to receiving mode due to noise. Figures 14, 15 and 16 illustrate the bit check for the bitcheck limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the ASK/ FSK demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit-check counter is clocked with the cycle TXClk. Figure 14 shows how the bit check proceeds if the bitcheck counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In figure 15 the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in figure 16. Dem_out Figure 10. Valid time window for bit check For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved us- Rev. A2, 19-Oct-00 9 (32) Preliminary Information T5760 / T5761 ( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit–check– counter 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 Bit check ok Bit check ok 1/2 Bit 1/2 Bit TStart–up Start–up mode TXClk TBit–check Bit–check mode Figure 11. Timing diagram during bit check ( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit–check– counter 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 0 Bit check failed ( CV_Lim < Lim_min ) TStart–up Start–up mode TBit–check Bit–check mode TSleep Sleep mode Figure 12. Timing diagram for failed bit check (condition: CV_Lim < Lim_min) ( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit–check– counter 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 Bit check failed ( CV_Lim >= Lim_max ) TStart–up Start–up mode TBit–check Bit–check mode TSleep Sleep mode Figure 13. Timing diagram for failed bit check (condition: CV_Lim >= Lim_max) Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/ FSK demodulator delivers random signals. The bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a lower value for TBit-check resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the checked bits, NBit-check. A higher value for 10 (32) NBit-check thereby results in a longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst. Receiving Mode If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. According to figure 9, the internal data signal is switched to Pin DATA in that case and the data clock is available after the start bit has been detected (figure 20). A connected µC can be woken up by the negative edge at Pin DATA or by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly. Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Digital Signal Processing The data from the ASK/ FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 14 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data TXClk Clock bit–check counter Dem_out Data_out (DATA) signal is limited to tee ≥ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected µC. The maximum time period for DATA to stay Low is limited to TDATA_L_max. This function is employed to ensure a finite response time in programming or switching off the receiver via Pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 16 gives an example where Dem_out remains Low after the receiver has switched to receiving mode. tee Figure 14. Synchronization of the demodulator output Dem_out Data_out (DATA) tDATA_min tDATA_min tDATA_min tee tee tee Figure 15. Debouncing of the demodulator output IC_ACTIVE Bit check Dem_out Data_out (DATA) tDATA_min Start–up mode Bit–check mode Receiving mode tDATA_L_max Figure 16. Steady L state limited DATA output pattern after transmission Rev. A2, 19-Oct-00 11 (32) Preliminary Information T5760 / T5761 After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the output signal at Pin DATA is high or random noise pulses appear at Pin DATA (see chapter ’Digital Noise Supression’). The edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than TDATA_min. Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via Pin DATA or via Pin POLLING/_ON. When using Pin DATA, this pin must be pulled to Low for the period t1 by the connected µC. Figure 17 illustrates the timing of the OFF command (see also figure 32). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. Note also that an internal reset for the OPMODE and the LIMIT register will be generated if t1 exceeds the specified values. This item is explained in more detail in the chapter ‘Configuration of the Receiver ’. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to be ‘1’ during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command the sleep time TSleep elapses. Note that the capacitive load at Pin DATA is limited (see chapter ’Data Interface’). IC_ACTIVE t1 t2 t3 t4 t10 t7 t5 Out1 (µC) Data_out (DATA) X Serial bi–directional data line X Bit 1 (”1”) (Start bit) OFF–command Receiving mode TSleep Sleep mode TStart–up Start–up mode Figure 17. Timing diagram of the OFF-command via Pin DATA IC_ACTIVE ton2 ton3 Bit check ok POLLING/_ON X Data_out (DATA) X Serial bi–directional data line X Receiving mode Sleep mode Start–up mode Bit–check mode X Receiving mode Figure 18. Timing diagram of the OFF-command via Pin POLLING/_ON 12 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 IC_ACTIVE ton1 POLLING/_ON X Data_out (DATA) Serial bi–directional data line Sleep mode Start–up mode X Receiving mode Figure 19. Activating the receiving mode via Pin POLLING/_ON Figure 18 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON. The Pin POLLING/_ON must be held to low for the time period ton2. After the positive edge on Pin POLLING/_ON and the delay ton3, the polling mode is active and the sleep time TSleep elapses. This command is faster than using Pin DATA at the cost of an additional connection to the µC. Figure 19 illustrates how to set the receiver to receiving mode via the Pin POLLING/_ON. The Pin POLLING/_ON must be held to Low. After the delay ton1 , the receiver changes from sleep mode to start–up mode regardless the programmed values for TSleep and NBit–check. As long as POLLING/_ON is held to Low, the values for TSleep and NBit–check will be ignored, but not deleted (see also chapter ’Digital Noise Suppression’). If the receiver is polled exclusively by a µC, TSleep must be programmed to 31 (permanent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON is held to High. compared to a programmable time window. As illustrated in figure 20, only two distances between two edges in Manchester and Bi-phase coded signals are valid (T and 2T). The limits for T are the same as used for the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see tables 10 and 11). The limits for 2T are calculated as follows: Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min) / 2 Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min) / 2 (If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it will be round up) The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the delay tDelay after the edge on Pin DATA (see figure 20). If the data clock control logic detects a timing or logical error (Manchester code violation), like illustrated in figures 21 and 22, it stops the output of the data clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see figure 23). It is recommended to use the function of the data clock only in conjunction with the bit check 3, 6 or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the Pin POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit). Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit. Data Clock The Pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock, a µC can easily synchronize the data stream. This clock can only be used for Manchester and Biphase coded signals. Generation of the data clock: After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at Pin DATA. In receiving mode, the data clock control logic (Manchester/Bi-phase demodulator) is active and examines the incoming data stream. This is done, like in the bit check, by subsequent time frame checks where the distance between two edges is continuously Rev. A2, 19-Oct-00 13 (32) Preliminary Information T5760 / T5761 Preburst Bit check ok T ’1’ Dem_out ’1’ ’1’ ’1’ ’1’ 2T ’0’ ’1’ ’1’ ’0’ ’1’ ’0’ Data Data_out (DATA) DATA_CLK Start bit Bit–check mode tDelay tP_Data_Clk Receiving mode, data clock control logic active Figure 20. Timing diagram of the data clock Data Timing error (Tee < T Lim_min OR T Lim_max T Lim_max_2T) Tee ’1’ Dem_out ’1’ ’1’ ’1’ ’1’ ’0’ ’1’ ’1’ ’0’ ’1’ ’0’ Data_out (DATA) DATA_CLK Receiving mode, data clock control logic active Receiving mode, bit check active Figure 21. Data clock disappears because of a timing error Data Logical error (Manchester code violation) ’1’ Dem_out ’1’ ’1’ ’0’ ’1’ ’1’ ’?’ ’0’ ’0’ ’1’ ’0’ Data_out (DATA) DATA_CLK Receiving mode, data clock control logic active Receiving mode, bit check aktive Figure 22. Data clock disappears because of a logical error 14 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Data Bit check ok ’1’ Dem_out ’1’ ’1’ ’1’ ’1’ ’0’ ’1’ ’1’ ’0’ ’1’ ’0’ Data_out (DATA) DATA_CLK Receiving mode, bit check active Start bit Receiving mode, data clock control logic active Figure 23. Output of the data clock after a successful bit check The delay of the data clock is calculated as follows: tDelay = tDelay1 + tDelay2 tDelay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1 depends on the capacitive load CL at Pin DATA and the external pull–up resistor Rpup. For the falling edge, tDelay1 depends additionally on the external voltage VX (see figures 24, 25 and 32). When the level of Data_In is equal to the level of Data_Out, the data clock is issued after an additional delay tDelay2. Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive load at Pin DATA is exceeded, the data clock disappears (see chapter ’Data Interface’). Data_Out V X V Ih = 0,65 * V S VIl = 0,35 * V S Serial bi–directional data line Data_In DATA_CLK tDelay1 tDelay tDelay2 tP_Data_Clk Figure 24. Timing characteristic of the data clock (rising edge on Pin DATA) Data_Out VX VIh = 0,65 * VS VIl = 0,35 * VS Serial bi–directional data line Data_In DATA_CLK tDelay1 tDelay tDelay2 tP_Data_Clk Figure 25. Timing characteristic of the data clock (falling edge of the Pin DATA) Rev. A2, 19-Oct-00 15 (32) Preliminary Information T5760 / T5761 Digital Noise Suppression After a data transmission, digital noise appears on the data output (see figure 26). To prevent that digital noise keeps the connected µC busy, it can be suppressed in two different ways. 1. Automatic noise suppression: is suppressed and the level at Pin DATA is High in that case. The receiver changes back to receiving mode, if the bit check was successful. This way to suppress the noise is recommended if the data stream is Manchester or Bi-phase coded and is active after power on. Figure 28 illustrates the behavior of the data output at the end of a data stream. Note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on Pin DATA. The length of the pulse depends on the selected baud-rate range. Bit check ok Data Digital Noise Digital Noise Preburst Data Digital Noise If the bit Noise_Disable (table 9) in the OPMODE register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream. The digital noise Bit check ok Data_out (DATA) DATA_CLK Bit–check mode Receiving mode, data clock control logic active Preburst Receiving mode, bit check aktive Receiving mode, data clock control logic active Receiving mode, bit check aktive Figure 26. Output of digital noise at the end of the data stream Bit check ok Data_out (DATA) DATA_CLK Bit–check mode Receiving mode, data clock control logic active Bit–check mode Preburst Data Bit check ok Preburst Data Receiving mode, data clock control logic active Bit–check mode Figure 27. Automatic noise suppression Timing error (tee < TLim_min OR TLim_max < tee < TLim_min_2T OR tee > TLim_max_2T) Tee Digital noise Data stream ’1’ Dem_out ’1’ ’1’ Data_out (DATA) TPulse DATA_CLK Receiving mode, data clock control logic active Bit–check mode Figure 28. Occurence of a pulse at the end of the data stream 16 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 2. Controlled noise suppression by the µC: Bit check ok Serial bi–directional data line (DATA_CLK) POLLING/_ON Bit–check mode Receiving mode Start–up Bit–check mode mode Receiving mode Sleep mode Preburst Data OFF–command Digital Noise Bit check ok Preburst Data Digital Noise Figure 29. Controlled noise suppression If the bit Noise_Disable (see table 9) in the OPMODE register is set to 0, digital noise appears at the end of a valid data stream. To suppress the noise, the Pin POLLING/_ON must be set to Low. The receiver remains in receiving mode. Then, the OFF-command causes the change to the start-up mode. The programmed sleep time (see table 7) will not be executed because the level at Pin POLLING/_ON is low, but the bit check is active in that case. The OFF-command activates the bit check also if the Pin POLLING/_ON is held to Low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the Pin POLLING/_ON must be set to High. This way to suppress the noise is recommended if the data stream is not Manchester or Bi-phase coded. is operated in default mode, there is no need to program the registers. Table 3 shows the structure of the registers. According to table 2 bit 1 defines if the receiver is set back to polling mode via the OFF command (see chapter ’Receiving Mode’) or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. To get a high programming reliability, Bit15 (Stop bit), at the end of the programming operation, must be set to 0. Table 1 Effect of Bit 1 and Bit 2 on programming the registers Bit 1 1 0 0 Bit 2 x 1 0 Action The receiver is set back to polling mode (OFF command) The OPMODE register is programmed The LIMIT register is programmed Configuration of the Receiver The T5760/T5761 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver Table 2 Effect of Bit 15 on programming the register Bit 15 0 1 Action The values will be written into the register (OPMODE or LIMIT) The values will not be written into the register Rev. A2, 19-Oct-00 17 (32) Preliminary Information T5760 / T5761 Table 3 Effect of the configuration words within the registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF–command 1 OPMODE register BR_Range NBit–check Modulation ASK/_ FSK 0 Sleep4 0 Sleep3 0 Sleep X Sleep Sleep1 1 Sleep0 0 XSleep Std Noise Suppression Noise_D isable 1 0 0 1 Baud1 0 Baud0 0 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É ÉÉÉ ÉÉÉ É É É ÉÉÉ É É É É É É É É É ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ Default values of Bit 3...14 0 1 1 0 LIMIT register Lim_min Lim_max 0 0 BitChk 1 BitChk 0 Sleep2 ÉÉÉ É É ÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ É ÉÉ É ÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Default values of Bit 3...14 0 1 0 1 0 1 1 0 1 0 0 1 Lim_ min5 Lim_ min4 Lim_ min3 Lim_ min2 Lim_ min1 Lim_ min0 Lim_ max5 Lim_ max4 Lim_ max3 Lim_ max2 Lim_ max1 Lim_ max0 0 The following tables illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud–rate range and simultaneously defines XLim. XLim is used to define the bit– check limits TLim_min and TLim_max as shown in table 10 and table 11. Table 4 Effect of the configuration word BR_Range BR_Range Baud1 0 Baud0 0 Baud-Rate Range / Extension Factor for Bit-Check Limits (XLim) BR_Range0 (application USA / Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default) XLim = 4 BR_Range1 (application USA / Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) 0 1 1 0 BR_Range2 (application USA / Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 1 1 BR_Range3 (Application USA / Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5 Effect of the configuration word NBit-check NBit-check BitChk1 0 0 1 1 BitChk0 0 1 0 1 Number of Bits to be Checked 0 6 9 3 (Default) 18 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Table 6 Effect of the configuration bit Modulation Modulation Selected Modulation FSK ASK/_FSK ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ 0 1 ASK Table 7 Effect of the configuration word Sleep Sleep Sleep4 0 0 0 0 . . . 0 . . . Sleep3 0 0 0 0 . . . 0 . . . Sleep2 0 0 0 0 . . . 1 . . . Sleep1 0 0 1 1 . . . 1 . . . Sleep0 0 1 0 1 . . . 0 . . . 0 (Receiver is continuously polling until a valid signal occurs) 1 (TSleep ≈ 2.1 ms for XSleep =1 and fRF = 868.3 ms, 1.96 ms for fRF = 915 MHz) 2 3 . . . 6 (TSleep = 12.695 ms for fRF = 868.3 MHz, 11.76 ms for fRF = 915 MHz) . . . Start Value for Sleep Counter (TSleep = Sleep y Xsleep y 1024 y TClk) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É É É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 29 30 31 (Permanent sleep mode) Table 8 Effect of the configuration bit XSleep XSleep XSleepStd 0 1 Extension Factor for Sleep Time (TSleep = Sleep y Xsleep y 1024 y TClk) 1 (Default) 8 Table 9 Effect of the configuration bit Noise Suppression Noise Suppression Noise_Disable Suppression of the Digital Noise at Pin DATA Noise suppression is inactive 0 1 Noise suppression is active (default) Rev. A2, 19-Oct-00 19 (32) Preliminary Information T5760 / T5761 Table 10 Effect of the configuration word Lim_min Lim_min *) (Lim_min < 10 is not applicable) Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lower Limit Value for Bit Check (TLim_min = Lim_min y XLim y TClk) 0 0 0 . . 0 0 0 . . 1 1 1 . . 0 0 1 . . 1 1 0 . . 0 1 0 . . 10 11 12 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ 0 1 0 1 0 1 21 (Default) (TLim_min = 347 µs for fRF = 868.3 MHz and BR_Range0 TLim_min = 329 µs for fRF = 915 MHz and BR_Range0) . . . . . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 61 62 63 *) Lim_min is also be used to determine the margins of the data clock control logic (see chapter ’Data Clock’) Table 11 Effect of the configuration word Lim_max Lim_max *) (Lim_max < 12 is not applicable) Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 Upper Limit Value for Bit Check (TLim_max = (Lim_max – 1) y XLim y TClk) 0 0 0 . . 0 0 0 . . 1 1 1 . . 1 1 1 . . 0 0 1 . . 0 1 0 . . 12 13 14 ÉÉ É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ É É É É É ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 0 1 0 0 1 41 (Default) (TLim_max = 677 µs for fRF = 868.3 MHz and BR_Range0, TLim_max = 642 µs for fRF = 915 MHz and BR_Range0) . . . . . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 61 62 63 *) Lim_max is also be used to determine the margins of the data clock control logic (see chapter ’Data Clock’) Conservation of the Register Information The T5760/T5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to figure 30, a power–on reset (POR) is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once VS exceeds VThReset the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at Pin DATA after a reset. The RM is repre- sented by the fixed frequency fRM at a 50% duty-cycle. RM can be canceled via a Low pulse t1 at Pin DATA. The RM implies the following characteristics: D fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected µC. D If the receiver is set back to polling mode via Pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in the section ’Programming the Configuration Registers’. By means of that mechanism the receiver cannot lose its register information without communicating that condition via the reset marker RM. 20 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 VS POR tRst Data_out (DATA) X 1 / fRM VThReset Figure 30. Generation of the power-on reset Programming the Configuration Register IC_ACTIVE t1 t2 t3 t4 t5 t6 t7 t9 t8 Out1 ( Data_out (DATA) X Serial bi–directional data line X Bit 1 (”0”) (Start bit) Bit 2 (”1”) (Register– select) Programming frame Receiving mode Bit 14 (”0”) (Poll8) Bit 15 (”0”) (Stop bit) TSleep TStart–up Sleep Start–up mode mode Figure 31. Timing of the register programming VX = 5 V to 20 V VS = 4.5 V to 5.5 V T5760/ T5761 Rpup DATA I/O Serial bi–directional data line µC 0V/5V Data_In Input – Interface 0 ... 20 V ID CL Data_out Out1 µC Figure 32. Data interface The configuration registers are programmed serially via the bi-directional data line according to figure 31 and figure 32. Rev. A2, 19-Oct-00 21 (32) Preliminary Information T5760 / T5761 To start programming, the serial data line DATA is pulled to Low for the time period t1 by the µC. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the µC pulls down Pin DATA for the time period t7 during t5, the according bit is set to ’0’. If no programming pulse t7 is issued, this bit is set to ’1’. All 15 bits are subsequently programmed this way. The time frame to program a bit is defined by t6. Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both in sleep– and in active–mode of the receiver. During programming, the LNA, LO, lowpass filter IFamplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to ’1’, it represents the OFF–command to set the receiver back to polling mode at the same time. For the length of the proTable 12 Applicable Rpup gramming start pulse t1, the following convention should be considered: D t1(min) < t1 < 5632 TClk: t1(min) is the minimum specified value for the relevant BR_Range Programming respectively OFF-command is initiated if the receiver is not in reset mode.If the receiver is in reset mode, programming respectively Off-command is not initiated and the reset marker RM is still present at Pin DATA. This period is generally used to switch the receiver to polling mode or to start the programming of a register. In reset condition, RM is not cancelled by accident. D t1 > 7936 TClk Programming respectively OFF–command is initiated in any case. The registers OPMODE and LIMIT are set to the default values. RM is cancelled if present. This period is used if the connected µC detected RM.If the receiver operates in default mode, this time period for t1 can generally be used. Note that the capacitive load at Pin DATA is limited. Data Interface The data interface (see figure 32) is designed for automotive requirements. It can be connected via the pull–up resistor Rpup up to 20V and is short–circuit–protected. The applicable pull-up resistor Rpup depends on the load capacity CL at Pin DATA and the selected BR_range (see table 12). More detailed information about the calculation of the maximum load capacity at Pin DATA is given in the ’Application Hints T5743N’. BR_range CL ≤ 1nF B0 B1 B2 B3 CL ≤ 100pF B0 B1 B2 B3 Applicable Rpup 1.6 kΩ to 47 kΩ 1.6 kΩ to 22 kΩ 1.6 kΩ to 12 kΩ 1.6 kΩ to 5.6 kΩ 1.6 kΩ to 470 kΩ 1.6 kΩ to 220 kΩ 1.6 kΩ to 120 kΩ 1.6 kΩ to 56 kΩ 22 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 VS C7 4.7u 10% GND R3 >= 1.6k C14 33n 5% C13 10n 10% 1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST1 6 AGND 7 n.c. DATA POLLING/_ON DGND DATA_CLK TEST4 DVCC XTAL 20 19 18 17 16 15 IC_ACTIVE R2 Sensitivity reduction 56k to 150k VX = 5 V to 20 V DATA POLLING/_ON DATA_CLK C12 10n 10% C11 12p 2% np0 T5760/ T5761 Q1 14 8 LNAREF 9 LNA_IN 10 LNAGND n.c. 13 12 TEST3 11 TEST2 6.77617 MHz RF_IN C17 2.2p 5% np0 C16 150p 10% np0 Toko LL2012 F5N6J 5.6 nH, 5% Figure 33. Application circuit: fRF = 868.3 MHz without SAW filter VS C7 4.7u 10% GND 1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST1 6 AGND 7 n.c. DATA POLLING/_ON DGND DATA_CLK TEST4 DVCC XTAL 20 19 18 17 16 15 IC_ACTIVE R2 Sensitivity reduction 56k to 150k VX = 5 V to 20 V R3 >= 1.6k C14 33n 5% C13 10n 10% DATA POLLING/_ON DATA_CLK C12 10n 10% C11 12p 2% np0 T5760/ T5761 Q1 14 8 LNAREF 9 LNA_IN 10 LNAGND n.c. 13 12 TEST3 11 TEST2 6.77617 MHz C16 18p 5% np0 C17 5.6p 5% np0 Toko LL2012 F5N6J 5.6 nH, 5% 5 6 7 8 RF_IN Toko LL2012 EPCOS B3570 F15NJ 15n, 5% 1 IN OUT 2 IN_GND OUT_GND C2 3 CASE_GND CASE_GND 3.3p 4 CASE_GND CASE_GND 5% np0 Figure 34. Application circuit: fRF = 868.3 MHz with SAW filter Rev. A2, 19-Oct-00 23 (32) Preliminary Information T5760 / T5761 Absolute Maximum Ratings Parameter Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50 W Symbol VS Ptot Tj Tstg Tamb Pin_max –55 –40 Min. Max. 6 1000 150 +125 +105 10 Unit V mW °C °C °C dBm Thermal Resistance Parameter Junction ambient Symbol RthJA Value 100 Unit K/W Electrical Characteristics All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) Parameter Test Conditions Symbol fRF = 868.3 MHz 6.77617 MHz Osc. Min. Basic clock cycle of the digital circuitry Basic clock cycle Extended basic clock cycle Polling mode Sleep time see figures 11, 20 and 33 Start-up time see figures 11 and 12 Time for bit check see figure 11 Sleep and XSleep are defined in the OPMODE register TSleep Sleep × XSleep × 1024 × 2.0662 1852 1059 1059 662 Sleep × XSleep × 1024 × 2.0662 1852 1059 1059 662 Sleep × XSleep × 1024 × 1.9607 1758 1049 1049 628 Sleep × XSleep × 1024 × 1.9607 1758 1049 1049 628 Sleep × XSleep × 1024 × TClk 896.5 512.5 512.5 320.5 × TClk Sleep × XSleep × 1024 × TClk 896.5 512.5 512.5 320.5 × TClk ms BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk TXClk 2.0662 16.53 8.26 4.13 2.07 2.0662 16.53 8.26 4.13 2.07 1.9607 15.69 7.84 3.92 1.96 1.9607 15.69 7.84 3.92 1.96 1/fXTO/14 8 × TClk 4 × TClk 2 × TClk 1 × TClk 1/fXTO/14 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs µs Typ. Max. fRF = 915 MHz 7.14063 MHz Osc. Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit BR_Range0 BR_Range1 BR_Range2 BR_Range3 Average bit-check time while polling, no RF applied, see figures 15 and 16 BR_Range0 BR_Range1 BR_Range2 BR_Range3 Bit-check time for a valid input signal fSig , see figure 12 NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 TStartup µs µs µs µs µs TBit-check 0.45 0.24 0.14 0.08 TBit-check 0.45 0.24 0.14 0.08 ms ms ms ms 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 1 TXClk 3/fSig 6/fSig 9/fSig 1 × TClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms 24 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Electrical Characteristics (continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) Parameter Test Conditions Symbol fRF = 868.3 MHz 6.77617 MHz Osc. Min. Receiving mode Intermediate frequency Baud-rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 165.3 82.6 41.3 20.7 165.3 82.6 41.3 20.7 156.8 78.4 39.2 19.6 156.8 78.4 39.2 19.6 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk µs µs µs µs fIF BR_Range 1.0 1.8 3.2 5.6 1.000 1.8 3.2 5.6 10.0 1.054 1.89 3.38 5.9 1.054 1.89 3.38 5.9 10.5 fXTO × 128 / 867.3 BR_Range0 × 2 µs / TClk BR_Range1 × 2 µs / TClk BR_Range2 × 2 µs / TClk BR_Range3 × 2 µs / TClk MHz kBaud kBaud kBaud kBaud fRF = 915 MHz 7.14063 MHz Osc. Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit Typ. Max. Minimum time period between edges at Pin DATA See figures 18 and 19 (With the exception of parameter TPulse) Maximum Low period at Pin DATA See figure 16 Delay to activate the start-up mode See figure 22 OFF– command at Pin POLLING/_ON See figure 21 Delay to activate the sleep mode See figure 21 Pulse on Pin DATA at the end of a data stream See figure 30 tDATA_min BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDATA_L_m ax 2149 1074 537 269 19.6 2149 1074 537 269 21.7 2139 1020 510 255 18.6 2139 1020 510 255 20.6 130 130 130 130 × TXClk × TXClk × TXClk × TXClk 130 130 130 130 × TXClk × TXClk × TXClk × TXClk µs µs µs µs µs Ton1 9.5 TClk 10.5 TClk Ton2 16.5 15.6 8 TClk µs Ton3 17.6 19.6 16.6 18.6 8.5 TClk 9.5 TClk µs BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 TPulse 16.5 8.3 4.1 2.1 16.5 8.3 4.1 2.1 15.69 7.84 3.92 1.96 15.69 7.84 3.92 1.96 8 4 2 1 TClk TClk TClk TClk 8 4 2 1 TClk TClk TClk TClk µs µs µs µs Rev. A2, 19-Oct-00 25 (32) Preliminary Information T5760 / T5761 Electrical Characteristics (continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) Parameter Test Conditions Symbol fRF = 868.3 MHz 6.77617 MHz Osc. Min. Configuration of the receiver (see figures 17 and 33) Freque ncy of the reset marker Programming start pulse Frequency is stable within 50 ms after POR BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR Programming delay period Synchroni– zation pulse Delay until of the program window starts Programming window Time frame of a bit Programming pulse Equivalent acknowledge pulse: E_Ack Equivalent time window OFF-bit programming window Data clock (see figures 27 and 28) Minimum delay time between edge @ DATA and DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDelay2 0 0 0 0 16.5 8.3 4.1 2.1 0 0 0 0 16.7 7.8 3.9 1.96 0 0 0 0 1 × TXClk 1 × TXClk 1 × TXClk 1 × TXClk µs µs µs µs t2 t3 t4 t1 3355 2273 1731 1461 16397 fRF = 915 MHz 7.14063 MHz Osc. Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit Typ. Max. 1 fRM 118.2 118.2 124.5 124.5 4096 T Clk 4096 1 T Clk Hz 11637 11637 11637 11637 3184 2168 1643 1386 15560 11043 11043 11043 11043 1624 TClk 1100 TClk 838 TClk 707 TClk 7936 TClk TClk 5632 5632 5632 5632 TClk TClk TClk TClk µs µs µs µs µs µs µs µs 795 264 131 797 264 131 754 251 125 756 251 125 384.5 385.5 TClk 128 TClk 128 TClk 63.5 TClk 63.5 TClk t5 t6 529 1058 529 1058 502 1004 502 1004 256 512 TClk TClk 256 512 TClk TClk µs µs t7 132 529 125 502 64 TClk 256 TClk µs t8 264 264 251 251 128 TClk 128 TClk µs t9 t10 533 929 533 929 506 881 506 881 258 TClk 258 TClk µs µs 449.5 TClk 449.5 TClk Pulswidth of negative pulse @ Pin DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tP_DATA_ CLK 66.1 33.0 16.5 8.3 66.1 33.0 16.5 8.3 63 31 15.7 7.8 63 31 15.7 7.8 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk µs µs µs µs 26 (32) Rev. A2, 19-Oct-00 Preliminary Information ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á ÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á Á ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ ÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁ Á Á Á Á ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) Rev. A2, 19-Oct-00 Electrical Characteristics (continued) Static capacitance at Pin XTAL to GND Series resonance resistor of the crystal XTO pulling Spurious of the VCO Phase noise local oscillator Operating frequency range VCO Local oscillator Maximum input level Image rejection 1 dB compression point LNA_IN input impedance System noise figure LO spurious emission Third-order intercept point LNA, mixer, polyphase lowpass and IF amplifier (input matched according to figure 33 referred to RFIN) Current consumption Parameters fosc = 867.3 MHz @ 10 MHz Parameter of the supplied crystal and board parasitics Parameter of the supplied crystal fXTAL = 7.14063 MHz (US) XTO pulling, appropriate load capacitance must be connected to XTAL, crystal CM = 7 fF fXTAL = 6.77617 MHz (EU) @ ± fXTO T5760 T5761 BER ≤ FSK mode ASK mode Within the complete image band @ 868.3 MHz @ 915 MHz With power matching |S11| < –10 dB Required according to I–ETS 300220 LNA/ mixer/ IF amplifier IC active (start-up-, bit check-, receiving mode) Pin DATA = H FSK ASK Sleep mode (XTO and polling logic active) Test Conditions / Pins 10–3, Preliminary Information ZiLNA_IN Symbol Pin_max ISLORF L (fm) IP1db fVCO fVCO fXTO ISoff IIP3 ISon NF RS C0 –30 ppm Min. 866 900 T5760 / T5761 200 || 3.2 200 || 3.2 fXTAL –140 Typ. –55 –25 –70 –16 170 7.8 7.4 30 5 +30 ppm Max. –130 120 –45 871 929 –10 –10 –57 276 6.5 9.9 9.6 20 dBC/Hz Ω || pF Ω || pF 27 (32) MHz MHz MHz dBm dBm dBm dBm dBm Unit dBC mA mA µA dB dB pF W T5760 / T5761 Electrical Characteristics (continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) ÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog signal processing (input matched according to figure 33 referred to RFIN) Input sensitivity ASK ASK (level of carrier) BERv10–3, 100% Mod fin = 868.3 MHz / 915 MHz Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit VS = 5 V, Tamb = 25°C fIF = 950 kHz/ 1 MHz BR_Range0 BR_Range1 BR_Range2 BR_Range3 PRef_ASK –110 –112 –110 –114 dBm dBm dBm dBm dB –108.5 –108 –106 +2.5 –100.5 –108 –112.5 –108 –110 –1.0 Sensitivity variation ASK for the full operating range compared to Tamb = 25°C, VS = 5 V Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25°C, VS = 5 V, Input sensitivity FSK fin = 868.3 MHz / 915 MHz fIF = 950 kHz/ 1 MHz PASK = PRef_ASK + DPRef fin = 868.3 MHz / 915 MHz fIF = 950 kHz/ 1 MHz DPRef fIF – 210 kHz to + 210 kHz fIF – 270 kHz to + 270 kHz PASK = PRef_ASK + DPRef, BERv10–3 fin = 868.3 MHz / 915 MHz DPRef +5.5 +7.5 –1.5 –1.5 dB dB VS = 5 V, Tamb = 25°C fIF = 950 kHz/ 1 MHz BR_Range0 df = +/– 16 kHz to 28 kHz df = +/– 10 kHz to +/– 100 kHz BR_Range1 df = +/– 16 kHz to 28 kHz df = +/– 10 kHz to +/– 100 kHz BR_Range2 df = +/– 18 kHz to 31 kHz df = +/– 13 kHz to +/– 100 kHz BR_Range3 df = +/– 25 kHz to 44 kHz df = +/– 20 kHz to +/– 100 kHz fin = 868.3 MHz / 915 MHz fIF = 950 kHz/ 1 MHz PFSK = PRef_FSK + DPRef fin = 868.3 MHz / 915 MHz fIF = 950 kHz/ 1 MHz PRef_FSK –103 –101 –101 –99 –106 –107.5 –107.5 –105.5 –105.5 –104 dBm dBm dBm dBm dBm dBm dBm dBm dB PRef_FSK –104 PRef_FSK –99.5 –97.5 –97.5 –95.5 +3 –102.5 PRef_FSK –100.5 –102 Sensitivity variation FSK for the full operating range compared to Tamb = 25°C, DPRef –1.5 VS = 5 V Sensitivity variation FSK for the full operating range including IF filter compared to Tamb = 25°C, VS = 5 V fIF – 150 kHz to + 150 kHz fIF – 200 kHz to + 200 kHz fIF – 260 kHz to + 260 kHz PFSK = PRef_FSK + DPRef DPRef +6 +8 +11 –2 –2 –2 dB dB dB 28 (32) Rev. A2, 19-Oct-00 Preliminary Information ÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ Á Á ÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á ÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁ Á Á Á ÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) Rev. A2, 19-Oct-00 Electrical Characteristics (continued) Threshold voltage for reset Reduced sensitivity variation for different values of RSense Reduced sensitivity variation over full operating range Reduced sensitivity Upper cut-off frequency data filter Edge-to-edge time period of the input data signal for full sensitivity Recommended CDEM for best performance Lower cut-off frequency of the data filter Dynamic range RSSI ampl. S/N ratio to suppress inband noise signals. Noise signals may have any modulation scheme Parameters fcu_DF + RSense connected from Pin Sens to VS, input matched according to figure 33, fIN = 868.3 MHz/ 915 MHz Values relative to RSense = 56 kW RSense = 56 kW RSense = 100 kW PRed = PRef_Red + DPRed RSense = 100 kW RSense = 56 kW Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 CDEM = 33 nF BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 FSK mode ASK mode RSense = 56 kW RSense = 68 kW RSense = 82 kW RSense = 100 kW RSense = 120 kW RSense = 150 kW PRed = PRef_Red + DPRed Test Conditions / Pins Preliminary Information 2 p 1 30kW CDEM VThRESET SNRASK SNRFSK PRef_Red PRef_Red Symbol DRRSSI CDEM DPRed DPRed DPRed DPRed DPRed DPRed DPRed fcu_DF tee_sig fu Min. 2.8 4.8 8.0 15.0 1.95 0.11 –72 –63 270 156 89 50 5 5 T5760 / T5761 0 –3.5 –6.0 –9.0 –11.0 –13.5 Typ. 3.4 6.0 10.0 19.0 0.16 –77 –68 39 22 12 8.2 2.8 60 10 0 0 2 Max. 1000 560 320 180 4.0 7.2 12.0 23.0 3.75 0.20 –82 –73 12 0 0 3 29 (32) dBm (peak level) dBm dBm Unit kHz kHz kHz kHz kHz dB dB dB dB dB dB dB dB dB dB dB nF nF nF nF ms ms ms ms V T5760 / T5761 Electrical Characteristics (continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 868.3 MHz and f0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25°C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital ports Data output – Saturation voltage Low – max voltage @ Pin DATA – quiescent current – short–circuit current – ambient temp. in case of permanent short–circuit Data input – Input voltage Low – Input voltage High DATA_CLK output – Saturation voltage Low – Saturation voltage High IC_ACTIVE output – Saturation voltage Low – Saturation voltage High POLLING/_ON input – Low level input voltage – High level input voltage MODE input – Low level input voltage – High level input voltage TEST input – Low level input voltage IDATA_CLK = 1mA IDATA_CLK = –1mA IIC_ACTIVE = 1mA IIC_ACTIVE = –1mA Receiving mode Polling mode Division factor = 10 Division factor = 14 Test input must always be set to Low Voh = 20 V Vol = 0.8 to 20 V Voh = 0V to 20 V Iol ≤ 12 mA Iol = 2 mA Vol Vol 0.35 0.08 0.8 0.3 20 20 13 30 45 85 0.35 × VS Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit V V V Voh Iqu Iol_lim tamb_sc VIl Vich Vol Voh Vol Voh VIl VIh VIl VIh VIl µA mA °C V V V V V V V V V V V 0.65 × VS VS–0.4 V 0.1 VS–0.15 V 0.1 VS–0.15 V 0.4 VS–0.4 V 0.4 0.8 × VS 0.2 × VS 0.8 × VS 0.2 × VS 0.2 × VS 30 (32) Rev. A2, 19-Oct-00 Preliminary Information T5760 / T5761 Package Information Package SO20 Dimensions in mm 12.95 12.70 9.15 8.65 7.5 7.3 2.35 0.25 0.10 11.43 20 11 10.50 10.20 0.25 0.4 1.27 technical drawings according to DIN specifications 13038 1 10 Rev. A2, 19-Oct-00 31 (32) Preliminary Information T5760 / T5761 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 12. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 32 (32) Rev. A2, 19-Oct-00 Preliminary Information