Main Features
• • • • • • • • • • • •
8-bit Resolution 500 Msps (min) Sampling Rate Power Consumption: 3.8W Typ 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50Ω ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility ADC Gain Adjust Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Enhanced CBGA Package with Ceramic Lid Evaluation Board: TSEV8308500GL (Detailed Specification on Request) Demultiplexer TS81102G0: Companion Device Available
ADC 8-bit 500 Msps TS8308500
Performance
• 1.3 GHz Full Power Input Bandwidth • Band Flatness: 0.5 dB up to 500 MHz • SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at FS = 500 Msps, FIN = 20 MHz
• SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
at FS = 500 Msps, FIN = 250 MHz
• SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
at FS = 500 Msps, FIN = 500 MHz (-3 dB FS)
• 2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps • DNL = ±0.3 LSB INL = ±0.7 LSB • Low Bit Error Rate (10-13) at 500 Msps, Tj = 90°C
Applications
• • • • Digital Sampling Oscilloscopes Satellite Receiver Electronic Countermeasures/Electronic Warfare Direct RF Down-conversion
Screening
• • Atmel Standard Screening Level Temperature Range: – – 0°C < Tc; Tj < +90°C -40°C < Tc ; Tj < + 110°C
Description
The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 500 Msps. The TS8308500 is using an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an advanced high-speed bipolar process. The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing).
Rev. 2193A–BDC–06/03 2193A–BDC–04/03
1
Functional Description
Block Diagram
Figure 1. Simplified Block Diagram
GAIN
VIN, VINB
Master/Slave Track & Hold Amplifier
Resistor Chain
Analog Encoding Block
4
Interpolation Stages 4 5
Regeneration Latches 4 Error Correction & Decode Logic Clock Buffer 8 Output Latches & Buffers 8 DRRB DR, DRB GORB DATA, DATAB OR, ORB 5
CLK, CLKB
Functional Description
The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75Ω differential output buffers. The TS8308500 works in fully differential mode from analog inputs up to digital outputs. The TS8308500 features a full-power input bandwidth of 1.3 GHz. Control pin GORB is provided to select either the Gray or Binary data output format. The gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8308500. The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose).
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Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VIN and VINB Digital input voltage Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK and VCLKB Maximum junction temperature Storage temperature Lead temperature (soldering 10s) Note: Symbol VCC DVEE VPLUSD VEE DVEE to VEE VIN or VINB VIN - VINB VD VD VO VCLK or VCLKB VCLK - VCLKB Tj Tstg Tleads GORB DRRB Comments Value GND to 6 GND to -5.7 GND -0.3 to 2.8 GND to -6 0.3 -1 to 1 -2 to 2 -0.3 to VCC 0.3 VEE -0.3 to 0.9 VPLUSD -3 to VPLUSD -0.5 -3 to 1.5 -2 to 2 135 -65 to 150 300 Unit V V V V V V V V V V V V °C °C °C
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a thermal heat sink is mandatory (see Thermal characteristics).
Recommended Conditions of Use
Table 2. Recommended Conditions of Use
Recommended Value Parameter Positive supply voltage Positive digital supply voltage Positive digital supply voltage Negative supply voltages Differential analog input voltage (full-scale) Clock input power level Operating temperature range Symbol VCC VPLUSD VPLUSD VEE, DVEE VIN, VINB VIN - VINB PCLK, PCLKB TJ 50Ω differential or single-ended 50Ω single-ended clock input Commercial grade: “C” Industrial grade “V“ ECL output compatibility LVDS output compatibility Comments Min 4.75 – 1.4 -5.25 ±113 450 3 Typ 5 GND 2.4 -5 ±125 500 4 0 < Tc; Tj < 90 -40 < Tc; Tj < 110 Max 5.25 – 2.6 -4.75 ±137 550 10 Unit V V V V mV mVpp dBm °C
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Electrical Operating Characteristics
VEE = DVEE = -5V; VCC = +5V; VIN -VINB = 500 mVpp Full Scale differential input 50Ω differentially terminated digital outputs Tj (typical) = 70°C
Table 3. Electrical Specifications
Test Level Value Min Typ Max Unit Note
Parameter Power Requirements Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Analog Digital Negative supply voltage Negative supply current Analog Digital Nominal power dissipation Power supply rejection ratio Resolution Analog Inputs Full-scale input voltage range (differential mode) (0V common mode voltage) Full-scale input voltage range (single-ended input option) (14) Analog input capacitance Input bias current Input Resistance Full Power input Bandwidth (-3 dB) Small signal input Bandwidth (10% full-scale) Clock Inputs Logic compatibility for clock inputs (14) ECL Clock inputs voltages (VCLK or VCLKB): Logic 0 voltage Logic 1 voltage Logic 0 current Logic 1 current Clock input power level into 50Ω termination
Symbol
VCC VPLUSD VPLUSD ICC IPLUSD VEE AIEE DIEE PD PSRR –
1 4 4 1 1 1 1 1 1 4 –
4.5 – 1.4 – – -5.5 – – – – –
5 0 2.4 420 130 -5 185 160 3.9 0.5 –
5.5 – 2.6 445 145 -4.5 200 180 4.1 2 8
V V V mA mA V mA mA W mW bits
(2)
VIN VINB VIN VINB CIN IIN RIN FPBW SSBW
4 – 4 – 4 4 4 4 4
-125 -125 -250 – – – 0.5 – –
– – – 0 3 10 1 1.8 1.7
125 125 250 – 3.5 20 – – –
mV mV mV mV pF µA MΩ GHz GHz
– – VIL VIH IIL IIH –
– 4 – – – – –
ECL or specified clock input power level in dBm – – -1.1 – – – – – 5 5 dBm into 50Ω – -1.5 – 50 50
– – V V µA µA –
(8)
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Table 3. Electrical Specifications (Continued)
Test Level 4 4 Value Min -2 – Typ 4 3 Max 10 3.5 Unit dBm pF
(1)(6)
Parameter Clock input power level Clock input capacitance
Symbol – CCLK
Note
Digital Outputs Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format, Tj (typical) = 70°C. Full temperature range: 0°C < Tc; Tj < +90°C or -40°C < Tc ; Tj < 110°C Logic compatibility for digital outputs (Depending on the value of VPLUSD) (14) Differential output voltage swings (assuming VPLUSD = 0V): 75Ω open transmission lines (ECL levels) 75Ω differentially terminated 50Ω differentially terminated Output levels (assuming VPLUSD = 0V) 75Ω open transmission lines: Logic 0 voltage Logic 1 voltage Output levels (assuming VPLUSD = 0V) 75Ω differentially terminated: Logic 0 voltage Logic 1 voltage Output levels (assuming VPLUSD = 0V) 50Ω differentially terminated: Logic 0 voltage Logic 1 voltage Differential Output Swing Output level drift with temperature – – – – – – VOL VOH – VOL VOH – VOL VOH DOS – – 4 – – – 4 – – 4 – – – 1, 2 1, 2 4 4 – 1.5 0.70 0.54 – – -0.88 – – -1.07 – – -1.16 270 – ECL or LVDS – 1.620 0.825 0.660 – -1.62 -0.8 – -1.41 -1 – -1.40 -1.10 300 – – – – – – -1.54 – – -1.34 – – -1.32 – – 1.6 – – V V V – V V – V V – V V mV mV/°C
(6)
(6)
(6)
DC Accuracy Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format Tj (typical) = 70°C Differential non linearity Differential non linearity Integral non linearity Integral non linearity No missing codes Gain Input offset voltage DNLDNL+ INLINL+ – – – 1 1 1 1 -0.6 – -1.2 – -0.4 0.4 -0.7 0.7 – 0.6 – 1.2 lsb/V lsb/V lsb/V lsb/V
(3) (2)(3) (2)(3)
Guaranteed over specified temperature range 1, 2 1, 2 90 -26 98 -5 110 26 %/V mV/V
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Table 3. Electrical Specifications (Continued)
Test Level 4 4 Value Min 100 40 Typ 125 50 Max 150 60 Unit ppm/°C ppm/°C Note
Parameter Gain error drift Offset error drift Transient Performance Bit error rate FS = 500 Msps, FIN = 62.5 MHz ADC settling time VIN -VINB = 400 mVpp Overvoltage recovery time
Symbol – –
BER TS TOR
4 4 4
– – –
– 0.5 0.5
1E-13 1 1
Error/ sample ns ns
(2)(4)
(2)
(2)
AC Performance Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), binary output data format, Tj = 70°C, unless otherwise specified Signal to noise and distortion ratio FS = 500 Msps, FIN = 20 MHz FS = 500 Msps, FIN = 500 MHz FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) FS = 50 Msps, FIN = 25 MHz Effective number of bits FS = 500 Msps, FIN = 20 MHz FS = 500 Msps, FIN = 500 MHz FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) FS = 50 Msps, FIN = 25 MHz Signal to noise ratio FS = 500 Msps, FIN = 20 MHz FS = 500 Msps, FIN = 500 MHz FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) FS = 50 Msps, FIN = 25 MHz Total harmonic distortion FS = 500 Msps, FIN = 20 MHz FS = 500 Msps, FIN = 500 MHz FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) FS = 50 Msps, FIN = 25 MHz SINAD – – – – ENOB – – – – SNR – – – – |THD| – – – – – 4 4 4 1 – 4 4 4 1 – 4 4 4 1 – 4 4 4 1 – 43 42 38 43 – 7.0 6.8 6.0 7.0 – 44 44 40 44 – 50 48 38 44 – 45 44 40 46 – 7.2 7.0 6.3 7.4 – 46 45 43 45 – 53 50 40 54 – – – – – – – – – – – – – – – – – – – – – dB dB dB dB – Bits Bits Bits Bits – dB dB dB dB – dB dB dB dB
(2) (2) (2)
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Table 3. Electrical Specifications (Continued)
Test Level – 4 4 4 1 4 – Value Min – 50 50 38 50 – -47 Typ – 56 53 40 55 – -52 Max – – – – – – – Unit – dBc dBc dBc dBc – dBc
(2)
Parameter Spurious free dynamic range FS = 500 Msps, FIN = 20 MHz FS = 500 Msps, FIN = 500 MHz FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) FS = 50 Msps, FIN = 25 MHz Two-tone inter-modulation distortion FIN1 = 199.5 MHz at FS = 500 Msps, FIN2 = 200.5 MHz at FS = 500 Msps
Symbol SFDR – – – – IMD –
Note
(2)
Switching Performance and Characteristics – See Figure 2 and Figure 3 on page 9 Maximum clock frequency Minimum clock frequency Minimum clock pulse width (high) Minimum clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output rise/fall time for data (20%-80%) Output rise/fall time for data ready (20%-80%) Data ready output delay Data ready reset delay Data to data ready – Clock low pulse width (See “Timing Diagrams” on page 9) Data to data ready output delay (50% duty cycle) at 1 Gsps (See “Timing Diagrams” on page 9) Data pipeline delay Notes: 1. 2. 3. 4. 5. 6. 7. 8. FS FS TC1 TC2 Ta Jitter TDO TR/TF TR/TF TDR TRDR TOD-TDR TD1 TPD – 4 4 4 4 4 4 4 4 4 4 4 4 4 500 10 1.71 1.71 100 – 1150 250 250 1110 – 0 920 – – 2 2 +250 0.4 1360 350 350 1320 720 40 960 4 700 50 50 50 400 0.6 1660 550 550 1620 1000 80 1000 Msps Msps ns ns ps ps (rms) ps ps ps ps ps
(7)(11) (2) (2)(5) (2)(8) (9)(10) (9) (9) (2)(8) (9)(10) (12) (13)
ps ps clock cycles
(12)
(2)(13)
Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA See “Definition of Terms” on page 46 Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps Output error amplitude < ±4 lsb around worst code Maximum jitter value obtained for single-ended clock input on the die (chip on board): 200 fs Digital output back termination options depicted in Application Notes At 500 Msps, 50/50 clock duty cycle, TC2 = 2 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate Specified loading conditions for digital outputs: - 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces - Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input parasitic capacitance of 1.5 pF including package and ESD protections.) 9. Termination load parasitic capacitance derating values: - 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load
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- Unterminated (source terminated) 75Ω controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termination load 10. Apply proper 50/75Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8308500GL Evaluation Board 11. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100°C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about “TOD-TDR Variation Over Temperature” on page 22). 12. Min value guarantees performance. Max value guarantees functionality 13. Min value guarantees functionality. Max value guarantees performance 14. Refer to product Application Notes
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Timing Diagrams
Figure 2. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at LOW Level
TA = 250 ps
X (VIN, VINB) X N-1
N
X N+1
TC = 1000 ps TC1 TC2
X N+2
X N+3
X N+4
X N+5
(CLK, CLKB)
1360 ps TPD: 4.0 Clock periods TOD = 1360 ps
DIGITAL OUTPUTS
1000 ps
DATA N-5
DATA N-4
TDR = 1320 ps
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
TDR = 1320 ps
TD1 = TC1+TDR-TOD = TC1-40 ps = 460 ps
Data Ready (DR, DRB)
TD2 = TC2+TOD-TDR = TC2+40 ps = 540 ps
TRDR = 720 ps
DRRB
1 ns (min)
Figure 3. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at HIGH Level
TA = 250 ps
X
(VIN, VINB)
X
X
N+2
X
N+3
N+4
X
X
N+5
XN-1
N
N+1
TC = 1000 ps TC1 TC2
(CLK, CLKB)
1360 ps TPD: 4.0 Clock periods TOD = 1360 ps
DIGITAL OUTPUTS
1000 ps
DATA N-5
DATA N-4
TDR = 1320 ps
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
TDR = 1320 ps
TD1 = TC1+TDR-TOD = TC1-40 ps = 460 ps
Data Ready (DR, DRB)
TD2 = TC2+TOD-TD = TC2+40 ps = 540
TRDR = 720 ps
DRRB
1 ns (min)
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Explanation of Test Levels
Table 4. Explanation of Test Levels(3)
Num 1 2 3 4 5 Note: Characteristics 100% production tested at +25°C(1) (for “C” Temperature range(2)) 100% production tested at +25°C(1), and sample tested at specified temperatures (for “V” Temperature range(2)) Sample tested only at specified temperatures Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature) Parameter is a typical value only 1. Unless otherwise specified, all tests are pulsed tests : therefore TC = TA where TC and TA are case and ambient temperature. 2. Refer to “Ordering Information” on page 48. 3. Only min and max values are guaranteed (typical values are issued from characterization results).
Functions Description
Table 5. Functions Description
Name VCC VEE VPLUSD GND VIN, VINB CLK, CLKB DR, DRB OR, ORB GAIN GORB DIOD/DRRB Function Positive power supply Analog negative power supply Digital positive power supply Ground Differential analog inputs Differential clock inputs Differential output data port Differential data ready outputs
GORG VIN VINB CLK CLKB GAIN OR ORB VCC = +5V VPLUSD = +0V (ECL) VPLUSD = +2.4V (LVDS)
TS8308500
D0 16 D0B DR DRB
D7 D7B
Out of range outputs ADC gain adjust Gray or binary digital output select Die junction temperature measurement/ asynchronous data ready reset
DIOD/ DRRB
DVEE = -5V VEE = -5V
GND
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Digital Output Coding
NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity voltage errors.
Table 6. Digital Output Coding
Digital Output Differential Analog Input > +251 mV +251 mV +249 mV +126 mV +124 mV +1 mV -1 mV -124 mV -126 mV -249 mV -251 mV < -251 mV Voltage Level > Positive full-scale + 1/2 LSB Positive full-scale + 1/2 LSB Positive full-scale - 1/2 LSB Positive 1/2 scale + 1/2 LSB Positive 1/2 scale - 1/2 LSB Bipolar zero + 1/2 LSB Bipolar zero - 1/2 LSB Negative 1/2 scale + 1/2 LSB Negative 1/2 scale - 1/2 LSB Negative full-scale + 1/2 LSB Negative full-scale - 1/2 LSB < Negative full-scale - 1/2 LSB Binary GORB = VCC or Floating 11111111 11111111 11111110 11000000 10111111 10000000 01111111 01000000 00111111 00000001 00000000 00000000 Gray GORB = GND 10000000 10000000 10000001 10100000 11100000 11000000 01000000 01100000 00100000 00000001 00000000 00000000 Out of Range 1 0 0 0 0 0 0 0 0 0 0 1
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Typical Characterization Results Static Linearity
50/50 clock duty cycle, Binary output coding, Tj = 70°C, single-ended analog and clock inputs, unless otherwise specified.
FS = 50 Msps/FIN = 10 MHz Figure 4. Integral Non-linearity
Note:
Clock frequency = 50 Msps; signal frequency = 10 MHz Positive peak: -0.68 LSB; Negative peak: -0.69 LSB
Figure 5. Differential Non-linearity
Note:
Clock frequency = 50 Msps; signal frequency = 10 MHz; Positive peak: 0.3 LSB; negative peak: -0.29 LSB
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Effective Number of Bits Versus Power Supply Variation
Figure 6. Effective Number of Bits = f (VEEA); FS = 500 Msps; FIN = 100 MHz
8 7 6 ENOB (bits) 5 4 3 2 1 0 -7 -6.5 -6 -5.5 VEEA (V) -5 -4.5 -4
Figure 7. Effective Number of Bits = f (VCC); FS = 500 Msps; FIN = 100 MHz
8 7 6 ENOB (bits) 5 4 3 2 1 0 3 3.5 4 4.5 5 VCC (V) 5.5 6 6.5 7
Figure 8. Effective Number of Bits = f (VEED); FS = 500 Msps; FIN = 100 MHz
8 7 6 ENOB (bits) 5 4 3 2 1 0 -6 -5.5 -5 -4.5 VEED (V) -4 -3.5 -3
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Typical FFT Results
Figure 9. Spectrum for FS = 500 Msps, FIN = 498 MHz (Full Scale Input)
Note:
Acquisition of 4096 points; THD = -49.67 dBc; Fs = 500 Msps; SINAD = 44.01 dB; FIN = 498 MHz; SFDR = -54.31 dBc; SFSR = -0.94 dB; ENOB = 7.13 bits; SNR = 45.39 dB
Figure 10. Reconstructed Signal for FS = 500 Msps, FIN = 498 MHz (Full Scale Input)
LSB 250 200 150 100 50 0 0 1 ns
Note:
Acquisition of 4096 samples; FS = 500 Msps; Amplitude: 0.221V (114.5 LSB); FIN = 498 MHz; Offset: 0V (122.5 LSB)
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Figure 11. Spectrum for FS = 500 Msps, FIN = 250 MHz (Full Scale Input)
Figure 12. Reconstructed Signal for FS = 500 Msps, FIN = 250 MHz (Full Scale Input)
Lsb 250 200 150 100 50 0 0 1 2 3 ns
Note:
Acquisition of 4096 samples; FS = 500 Msps ; Amplitude: 0.189V (113.5 LSB); FIN = 250 MHz ; Offset: 0V (122.5 LSB)
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Dynamic Performance Versus Analog Input Frequency
Figure 13. SFDR: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
SFDR 60 55 dBc 50 45 40 2 100 200 300 400 500 Fin (MHz) 600 700 800 900 1000
Figure 14. THD: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
THD -60 -50 dBc -40 -30 -20 -10 0 2 100 200 300 400 500 Fin (MHz) 600 700 800 900 1000
Figure 15. SINAD and SNR: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
SINAD 48 46 44 42 dB 40 38 36 2 100 200 300 400 500 Fin (MHz) 600 700 800 900 1000 SNR
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Figure 16. Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
ENOB
7,5 7
Bits
6,5 6 5,5 2 100 200 300 400 500
Fin (MHz)
600
700
800
900
1000
SFDR and THD Versus Sampling Frequency
Figure 17. Analog Input Frequency: FIN = 250 MHz and Fs = 200 Msps to 1400 Msps
THD -60 -50 dBc -40 -30 -20 -10 200 400 600 800 Fs (Msps) 1000 1200 1400 SFDR
Effective Number of Bits (ENOB) Versus Sampling Frequency
Figure 18. Analog Input Frequency: FIN = 250 MHz and Fs = 200 Msps to 1400 Msps
ENOB 8 7 6 Bits 5 4 3 2 1
200
400
600
800
Fs Msps
1000
1200
1400
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Sinad and SNR Versus Sampling Frequency
Figure 19. Analog Input Frequency: FIN = 250 MHz and FS = 200 Msps to 1400 Msps
SINAD 50 45 40 35 dB 30 25 20 15 10 200 400 600 800 Fs (Msps) 1000 1200 1400 SNR
TS8308500 ADC Performances Versus Junction Temperature
Figure 20. SFDR: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
SFDR 53.0 52.5 52.0 51.5 51.0 50.5 50.0 0 25 50 Tj(°C) 75 100 125
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dBc
TS8308500
Figure 21. THD: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
THD -60 -50 -40
dBc
-30 -20 -10 0 0 25 50 Tj (°C) 75 100 125
Figure 22. SINAD and SNR: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
SINAD 46.5 46.0 45.5 dB 45.0 44.5 44.0 43.5 0 25 50 Tj (°C) 75 100 125 SNR
Figure 23. ENOB: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
ENOB
7.30 7.25 7.20
Bits
7.15 7.10 7.05 7.00
0 25 50
Tj (°C)
75
100
125
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Figure 24. Power Consumption Versus Junction Temperature: FS = 500 Msps; FIN = 250 MHz; Duty cycle = 50%
5
Power Consumption (W)
4
3
2
1
0 -40
-20
0
20
40
60
80
100
120
140
160
Temperature (°C)
Typical Full Power Input Bandwidth
Figure 25. Band Flatness at 1.3 GHz ; -3 dB (-2 dBm Full Power Input)
0
-1
-2 SFSR (dB FS)
-3
-4
-5
-6 0 200 400 600 800 Frequency (MHz) 1000 1200 1400 1600
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ADC Step Response
Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps.
Note: This step response was obtained with the TSEV8308500 chip on-board (device in die form).
Figure 26. Test Pulse Digitized with 20 GHz DSO
250 200 150
mV
100
Vpp ~ 260 mV Tr ~ 270 ps 50 mV/div 600 ps/div
50
0
0
0.5
1.0
1.5
2.0
2.5 Time (ns)
3.0
3.5
4.0
4.5
Figure 27. Same Test Pulse Digitized with TS8308500 ADC
200
150
ADC
Tr ~ 330 ps 100 50 codes/div (Vpp ~ 260 mV) 600 ps/div
50
0 0 0.6 1.2 1.8 2.4 3.0 Time (ns) 3.6 4.2 4.8 5.4 6.0
Note:
Ripples are due to the test setup (they are present on both measurements).
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TS8308500 Main Features
Timing Information
Timing Value for TS8308500 Timing values as defined in Table 3 on page 4 are advanced data, issuing from electric simulations and are the first characterization results fitted with measurements. Timing values are given for CBGA68 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, and specified termination loads. Propagation delays in 50/75Ω impedance traces are NOT taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions: – Specified termination load (differential output Data and Data Ready): 50Ω resistor in parallel with 1 standard ECLinPS register from Motorola, (i.e.: 10E452). (Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections). If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value given below Output Termination Load derating values for TOD and TDR: ~ 35 ps/pF or 50 ps per additional ECLinPS load Propagation time delay derating values have also to be applied for TOD and TDR: ~ 6 ps/mm (155 ps/inch) for TSEV8308500 Evaluation Board Apply proper time delay derating value if a different dielectric layer is used.
– –
Propagation Time Considerations
TOD and TDR timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and input/output termination loads. For the TSEV8308500 Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corresponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board. If a different dielectric layer is used (for instance Teflon), use appropriate propagation time values. TD does NOT depend on propagation times because it is a differential data. (TD is the time difference between Data Ready output delay and digital Data output delay) TD is also the most straightforward data to measure, again because it is differential: TD can be measured directly onto termination loads, with matched oscilloscopes probes.
TOD-TDR Variation Over Temperature
Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per 100°C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR affect can be considered as negligible.
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Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other words: – – If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR). If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR). However, external TOD-TDR values may be dictated by total digital data skews between every TODs (each digital data) and TDR: MCM board , bonding wires and output lines lengths differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR.
Principle of Operation
The Analog input is sampled on the rising edge of the external clock input (CLK, CLKB) after TA (aperture delay) of typically 250 ps . The digitized data is available after 4 clock periods latency (pipeline delay (TPD), on clock rising edge, after 1360 ps typical propagation delay TOD.) The Data Ready differential output signal frequency (DR, DRB) is half the external clock frequency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR, DRB) switches on the external clock falling edge after a propagation delay TDR of typically 1320 ps. A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the output digital data in a defined order.
Principle of Data Ready Signal Control by DRRB Input Command
Data Ready Output Signal Reset The Data Ready signal is reset on the falling edge of the DRRB input command, on the ECL logical low level (-1.8V). DRRB may also be tied to VEE = -5V for Data Ready output signal Master Reset. So long as DRRB remains at a logical low level, (or tied to VEE = -5V), the Data Ready output remains at logical zero and is independent of the external free running encoding clock. The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps typical. TRDR is measured between the -1.3V point of the falling edge of the DRRB input command and the zero crossing point of the differential Data Ready output signal (DR, DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width.
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Data Ready Output Signal Restart
The Data Ready output signal restarts on the DRRB command’s rising edge, ECL logical high levels (-0.8V). DRRB may also be grounded, or is allowed to float, for a normal free running Data Ready output signal. The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant: • The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is LOW: The Data Ready output’s first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already defined hereabove. The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH: The Data Ready output’s first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320 ps.
•
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data corresponding to the first acquisition (N) after a Data Ready signal restart (rising edge) is always strobed by the third rising edge of the Data Ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,DRB) (zero crossing point).
Note: 1. For normal initialization of the Data Ready output signal, the external encoding clock signal frequency and level must be controlled. The minimum encoding clock sampling rate for the ADC is 10 Msps and consequently the clock cannot be stopped. 2. One single pin is used for both the DRRB input command and die junction temperature monitoring. Pin denomination will be DRRB/DIOD. (On former versions the denomination was DIOD.). Temperature monitoring and Data Ready control by DRRB is not possible simultaneously.
Analog Inputs (VIN, VINB)
The analog input Full Scale range is 0.5V, or -2 dBm into the 50Ω termination resistor. In differential mode input configuration, that means 0.25V on each input, or ±125 mV around 0V. The input common mode is ground. The typical input capacitance is 3 pF for TS8308500 in a CBGA package.
Differential Input Voltage Span
Figure 28. Differential Input Voltage Span
[mV] 125 500 mV Full Scale analog input 250 mV VIN VINB
-250 mV
0V
-125 (VIN, VINB) = ±250 mV = 500 mV diff
t
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Differential Versus Single-ended Analog Input Operation The TS8308500 can operate at full speed in either the differential or single-ended configuration. This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceeding the sample and hold stage), which has been designed in order to be entered either in differential mode or single-ended mode. This is true so long as the out-of-phase analog input pin VINB is 50Ω terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the in-phase analog input pin (VIN). Thus the differential analog input preamplifier will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. In a typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50Ω termination resistor. In a single-ended input configuration, the in-phase input amplitude is 0.5V, centered on 0V (or -2 dBm into 50Ω). The inverted phase input is at ground potential through the 50Ω termination resistor. However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode.
Typical Single-ended Analog Input Configuration Figure 29. Typical Single-ended Analog Input Configuration
[mV] 250 500 mV Full Scale analog input 500 mV VINB t VIN = ±250 mV = 500 mV diff 50Ω reverse termination VIN VIN or VINB double pad (pins 54, 55 or 56, 57) VIN or VINB
VINB = 0V
50Ω (on package)
1 MΩ
3 pF
-250
Clock Inputs (CLK, CLKB)
The TS8308500 can be clocked at full speed without noticeable performance degradation in either the differential or single-ended configuration. This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered either in differential or single-ended mode. The recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.
Single-ended Clock Input (Ground Common Mode)
Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V ECL levels, the TS8308500 clock buffer can manage a single-ended sinewave clock signal centered around 0V. This is the most convenient clock input configuration as it does not require the use of a power splitter.
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No performance degradation (i.e.: due to timing jitter) is observed in this particular singleended configuration up to 500 Msps Nyquist Conditions (FIN = 250 MHz). This is all the more so since the inverted phase clock input pin is 50Ω terminated on the package (that is very close to one of the neighboring shield ground pins, which constitutes the local ground reference for the inphase clock input). Thus the TS8308500 differential clock input buffer will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. The typical in-phase clock input amplitude is 1V, centered on 0V (ground) common mode. This corresponds to a typical clock input power level of 4 dBm into the 50Ω termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors. Figure 30. Single-ended Clock Input (Ground Common Mode): VCLK common mode = 0V; VCLKB = 0V; 4 dBm typical clock input power level (into 50Ω termination resistor)
[V] +0.5V VCLK CLK or CLKB double pad (pins 37, 38 or 39, 40) CLK or CLKB 1 MΩ
VCLK = 0V VCLK -0.5V t
50Ω (on package)
0.4 pF
50Ω reverse termination
Note:
Do not exceed 10 dBm into the 50Ω termination resistor for the single clock input power level.
Differential ECL Clock Input
The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels. In this mode, a low-phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 ° o ut of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels. Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals are 180° out of phase, especially at fast clock rates in the 500 Msps range.
Figure 31. Differential Clock Inputs (ECL Levels)
[mV] -0.8V VCLK VCLKB CLK or CLKB double pad (pins 37, 38 or 39, 40) CLK or CLKB 1 MΩ
Common mode = -1.3V
50Ω (on package) -2V
0.4 pF
-1.8V
t
50Ω reverse termination
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Single-ended ECL Clock Input In a single-ended configuration, enter at CLK (resp. CLKB) pin, with the inverted phase clock input pin CLKB (respectively CLK) connected to -1.3V through the 50Ω termination resistor. The in-phase input amplitude is 1V, centered on -1.3V common mode. Figure 32. Single-ended Clock Input (ECL): VCLK common mode = -1.3V; VCLKB = -1.3V
[V] -0.8V VCLK
VCLKB = -1.3V
-1.8V
t
Noise Immunity Information
Circuit noise immunity performance begins at design level. Efforts have been made to the design to make it as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry. (Cascode stage isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors.) Furthermore, the fully differential operation from the analog input up to the digital outputs provides enhanced noise immunity with common mode noise rejection. Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers. Moreover, proper active signal shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs. The analog inputs and clock inputs of the TS8308500 device have been surrounded by ground pins, which must be directly connected to the external ground plane.
Digital Outputs
The TS8308500 differential output buffers are internally loaded with 75Ω. The 75Ω resistors are connected to the digital ground pins through a -0.8V level shift diode (see Figure 33, Figure 34, Figure 35 on page 29). The TS8308500 output buffers are designed for driving 75Ω (default) or 50Ω properly terminated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75Ω resistors when switching ensures a 0.825V voltage drop across the resistor (unterminated outputs). The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output compatibility). Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V, (outputs unterminated), around -1.2V common mode voltage.
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Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD = 0V): 1. 75Ω impedance transmission lines, 75Ω differentially terminated (Figure 33): Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to ±0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V) 2. 50Ω impedance transmission lines, 50Ω differentially terminated (Figure 34): Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to ±0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V) 3. 75Ω impedance open transmission lines (Figure 35): Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V), which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V (respectively +1.2V) common mode for VPLUSD = 0V (respectively 2.4V) Therefore, it is possible to directly drive high input impedance storing registers, without terminating the 75Ω transmission lines. In the time domain, that means that the incident wave will reflect at the 75Ω transmission line output and travel back to the generator (i.e.: the 75Ω data output buffer). As the buffer output impedance is 75Ω, no back reflection will occur.
Note: This is no longer true if a 50Ω transmission line is used, as the latter is not matching the buffer 75Ω output impedance.
Each differential output termination length must be kept identical. It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor leading to switching ground noise. The differential output voltage levels (75Ω or 50Ω termination) are not ECL standard voltage levels, however, it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from Motorola®.
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Differential Output Loading Configurations (Levels for ECL Compatibility) Figure 33. Differential Output: 75Ω Terminated
VPLUSD = 0V -0.8V Out 75Ω 75Ω 75Ω 75Ω impedance 75Ω -1V/-1.41V
Differential output: +0.41V = 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level)
-
+
10 nF
75Ω
OutB 11 mA DVEE
-1.41V/-1V
Figure 34. Differential Output: 50Ω Terminated
VPLUSD = 0V -0.8V Out 75Ω 75Ω 50Ω 50Ω impedance 50Ω -1.02V/-1.35V
Differential output: +0.33V = 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level)
-
+
10 nF
50Ω
OutB 11 mA DVEE
-1.35V/-1.02V
Figure 35. Differential Output: Open Loaded
VPLUSD = 0V -0.8V Out 75Ω 75Ω 75Ω 75Ω impedance -0.8V/-1.6V
Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level)
-
+
OutB 11 mA DVEE
-1.6V/-0.8V
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Differential Output Loading Configurations (Levels for LVDS Compatibility) Figure 36. Differential Output: 75Ω Terminated
VPLUSD = 2.4V 1.6V Out 75Ω 75Ω 75Ω 75Ω impedance 75Ω 1.4V/0.99V
Differential output: +0.41V = 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level)
-
+
10 nF
75Ω
OutB 11 mA DVEE
0.99V/1.4V
Figure 37. Differential Output: 50Ω Terminated
VPLUSD = 2.4V 1.6V Out 75Ω 75Ω 50Ω 50Ω impedance 50Ω 1.38V/1.05V
Differential output: +0.33V = 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level)
-
+
10 nF
50Ω
OutB 11 mA DVEE
1.05V/1.38V
Figure 38. Differential Output: Open Loaded
VPLUSD = 2.4V 1.6V Out 75Ω 75Ω 75Ω 75Ω impedance 1.6V/0.8V
Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level)
-
+
OutB 11 mA DVEE
0.8V/1.6V
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Out of Range Bit
An Out of Range (OR, ORB) bit that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale is available. When the analog input exceeds the positive full-scale, the digital output datas remain at a high logical state, with (OR, ORB) at logical one. When the analog input falls below the negative full-scale, the digital outputs remain at a logical low state, with (OR, ORB) at logical one again.
Gray or Binary Output Data Format Select
The TS8308500 internal regeneration latches indecisions (for inputs very close to a latch threshold) that can produce errors in the logic encoding circuitry and lead to large amplitude output errors. This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t): Av = exp(∆(t)/τ), where τ is the positive feedback regeneration time constant. The TS8308500 has been designed to reduce the probability of occurrence of such errors to approximately 10-13 (targeted for the TS8308500 at 500 Msps). A standard technique for reducing the amplitude of such errors down to ±1 LSB consists in outputing the digital data in Gray code format. Though the TS8308500 has been designed to feature a bit error rate of 10-13 with a binary output format, it is possible for the user to select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when they occur, by storing Gray output codes. Digital Data format selection: • • BINARY output format if GORB is floating or VCC. GRAY output format if GORB is connected to ground (0V).
Diode Pin K1
A single pin is used for both the DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. (See “Principle of Data Ready Signal Control by DRRB Input Command” on page 23 for Data Ready Reset input command). The operating die junction temperature must be kept below 145°C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus junction temperature is given below.
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Figure 39. Diode Pin K1
1000 960 920 880 VBE (mV) 840 800 760 720 680 640 600 -55 -35 -15 5 25 45 65 Junction temperature (°C) 85 105 125
ADC Gain Control Pin K6
The ADC gain is adjustable by means of the pin K6 (input impedance is 1 MΩ in parallel with 2 pF). The gain adjust transfer function is given below: Figure 40. ADC Gain Control Pin K6
1.20 1.15 1.10 ADC Gain 1.05 1.00 0.95 0.90 0.85 0.80 -500
-400
-300
-200
-100
0
100
200
300
400
500
Vgain (command voltage) (mV)
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Equivalent Input/Output Schematics
Figure 41. Equivalent Analog Input Circuit and ESD Protections
VCC = +5V VCLAMP = +2.4V
-0.8V -0.8V
VCC GND
-5.8V -5.8V
GND = 0V
50Ω E21V
+1.65V
E21V 200Ω 200Ω
50Ω
VEE VIN
Pad capacitance 340 fF 5.8V
VEE VINB
Pad capacitance 340 fF
-1.55V
5.8V
0.8V
0.8V
E21G
VEE = -5V
E21G
Note:
The ESD protection equivalent capacitance is 150 fF.
Figure 42. Equivalent Analog Clock Input Circuit and ESD Protections
VCC = +5V +0.8V
-5.8V -0.8V
VCC
-5.8V
-5.8V
GND = 0V
-5.8V -5.8V E31V 150Ω 150Ω
VEE CLK
Pad capacitance 340 fF
E31V
VEE CLKB
Pad capacitance 340 fF
5.8V
5.8V
380 µA 0.8V 0.8V
E21G
VEE = -5V
E21G
Note:
The ESD protection equivalent capacitance is 150 fF.
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Figure 43. Equivalent Data Output Buffer Circuit and ESD Protections
VPLUSD = 0V to 2.4V
-5.8V
-5.8V
VEE OUT
E01V
E01V
VEE OUTB
5.8V Pad capacitance 180 fF 0.8V
5.8V Pad capacitance 180 fF 0.8V
0.8V
0.8V
DVEE = -5V VEE = -5V VEE = -5V
Note:
The ESD protection equivalent capacitance is 150 fF.
Figure 44. ADC Gain Adjust Equivalent Input Circuits and ESD Protections
VCC = +5V
-0.8V
GND +0.8V
NP1032C2
-5.8V
E22V
GA
Pad capacitance 180 fF
1 kΩ
0.8V
2 pF
0.8V
GND
5.8V 500 µA 500 µA
VEE
E22GA
VEE = -5V
Note:
The ESD protection equivalent capacitance is 150 fF.
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Figure 45. GORB Equivalent Input Schematic and ESD Protections GORB: gray or binary select input; floating or tied to VCC -> binary
VCC = +5V
-0.8V 1 kΩ -0.8V 1 kΩ -5.8V 1 kΩ
VEE
E21VA
5 kΩ
GORB
Pad capacitance 180 fF
5.8V
5.8V 250 µA 5.8V 250 µA
VEE = -5V
E31G
GND = 0V
Note:
The ESD protection equivalent capacitance is 150 fF.
Figure 46. DRRB Equivalent Input Schematic and ESD Protections Actual protection range: 6.6V above VEE, in fact stress above GND are clipped by the CB diode used for Tj monitoring
VCC = +5V
GND = 0V
NP1032C2 10 kΩ 200Ω -1.3V Pad capacitance 180 fF
DRRB
-2.6V 5.8V
0.8V
VEE
E21G
VEE = -5V
Note:
The ESD protection equivalent capacitance is 150 fF.
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TSEV8308500: Device Evaluation Board
For complete specification, see the separate “TSEV8308500” document.
General Description
The TSEV8308500 Evaluation Board (EB) is a board which has been designed in order to facilitate the evaluation and the characterization of the TS8308500 device up to its 1.3 GHz full power bandwidth at up to 500 Msps in the commercial temperature range. The high speed of the TS8308500 requires careful attention to circuit design and layout to achieve optimal performance. This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the TS8308500 ADC performances over the temperature range. The TSEV8308500 Evaluation Board is very straightforward as it only implements the TS8308500 ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes. The board also implements a de-embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature measurement setting. The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. The board dimensions are 130 mm x 130 mm. The board set comes fully assembled and tested, with the TS8308500 and its heatsink installed.
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Package Description
Table 7. TS8308500 Pad Description
Pad number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Chip Pad Name VPLUSD D5 D5B D4 D4B DVEE DR DRB D3 D3B VPLUSD D2 D2B D1 D1B D0 D0B GORG VCC GND VCC VEE VCC GND CLK GND CLKB GND VEE VCC VEE DIOD/DRRB GND Chip Pad Function Positive digital supply (double pad)(2) In-phase (+) digital output, bit 5 (D7 is the MSB; Bit 7, D0 is the LSB; Bit 0) Inverted phase (-) digital output, bit 5 In-phase (+) digital output, bit 4 Inverted phase (-) digital output, bit 4 -5V digital supply (double pad) In-phase (+) Data Ready Inverted phase (-) Data Ready In-phase (+) digital output, bit 3 Inverted phase (-) digital output, bit 3 Positive digital supply (double pad)(2) In-phase (+) digital output, bit 2 Inverted phase (-) digital output, bit 2 In-phase (+) digital output, bit 1 Inverted phase (-) digital output, bit 1 In-phase (+) digital output, bit 0, Least Significant Bit Inverted phase (-) digital output, bit 0, Least Significant Bit Gray or Binary data output format select(1) +5V supply (double pad) Analog ground (double pad) +5V supply (double pad) -5V analog supply (double pad) +5V supply (double pad) Analog ground (double pad) In-phase (+) clock input (double pad) Analog ground Inverted phase (-) clock input (double pad) Analog ground (double pad) -5V analog supply (double pad) +5V supply (double pad) -5V analog supply (double pad) Diode input for Tj monitoring/Input for asynchronous Data Ready Reset Analog ground
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Table 7. TS8308500 Pad Description (Continued)
Pad number 34 35 36 37 38 39 40 41 42 43 44 45 46 Notes: Chip Pad Name VIN GND VINB GND GAIN VCC VCC OR ORB D7 D7B D6 D6B Chip Pad Function In-phase (+) analog input (double pad) Analog ground Inverted phase (-) analog input (double pad) Analog ground (double pad) ADC gain adjust input +5V supply (double pad) +5V supply In-phase (+) Out of Range digital output Inverted phase (-) Out of Range digital output In-phase (+) digital output, bit 7, Most Significant Bit Inverted phase (-) digital output bit 7 In-phase (+) digital output, bit 6 Inverted phase (-) digital output, bit 6
1. GORB tied to VCC or floating: Binary output data format. GORB tied to GND: Gray output data format. 2. The common mode level of the output buffers is 1.2V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0V (ground). For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is remmended to lower the positive digital supply level in the name proportion in order to spare power dissipation.
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TS8308500 Pin Description (CBGA68 package) Table 8. TS8308500 Pin Description
Symbol GND VCC VEE DVEE VIN VINB CLK CLKB B0, B1, B2, B3, B4, B5, B6, B7 B0B, B1B, B2B, B3B, B4B, B5B, B6B, B7B OR ORB DR DRB GORB A7 GAIN DIOD/DRRB K1 VPLUSD NC Note: B11, C10, J10, K11 A1, A11, L1, L11 Pin number A2, A5, B1, B5, B10, C2, D2, E1, E2, E11, F1, F2, G11, K2, K3, K4, K5, K10, L2, L5 A4, A6, B2, B4, B6, H1, H2, L6, L7 A3, B3, G1, G2, J1, J2 F10, F11 L3 L4 C1 D1 A8, A9, A10, D10, H11, J11, K9, K8 B7, B8, B9, C11, G10, H10, L10, L9 K7 L8 E10 D11 Function Ground pins, to be connected to external ground plane +5V positive supply 5V analog negative supply -5V digital negative supply In-phase (+) analog input signal of the Sample and Hold differential preamplifier Inverted phase (-) of ECL clock input signal (CLK) In-phase (+) ECL clock input signal. The analog input is sampled and held on the rising edge of the CLK signal Inverted phase (-) of ECL clock input signal (CLK) In-phase (+) digital outputs. B0 is the LSB, B7 is the MSB Inverted phase (-) Digital outputs. B0B is the inverted LSB B7B is the inverted MSB In-phase (+) Out of Range bit. Out of Range is high on the leading edge of code 0 and code 256 Inverted phase (+) of Out of Range bit (OR) In-phase (+) output of Data Ready signal Inverted phase (-) output of Data Ready signal (DR) Gray or Binary select output format control pin – Binary output format if GORB is floating or VCC – Gray output format if GORB is connected at ground (0V) ADC gain adjust pin. The gain pin is grounded by default, the ADC gain transfer fuction is nominally close to one Die function temperature measurement pin and asynchronous data ready reset active low, single ended ECL input + 2.4V for LVDS output levels otherwise to GND(1) Not connected
K6
1. The common mode level of the output buffers is 1.2V below the positive digital supply For ECL compatibility the positive digital supply must be set at 0V (ground ) For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V If the subsequent LVDS circuitry can withstand a lower level for the input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation
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2193A–BDC–04/03
TS8308500GL Pinout of CBGA68 Package
Figure 47. TS8308500 Pinout of CBGA68 Package
11
NC
VPLUSD
B3b
DRb
GND
DVEE
GND
B4
B5
VPLUSD
NC
10
B2
GND
VPLUSD
B3
DR
DVEE
B4b
B5b
VPLUSD
GND
B6b
9
B1
B2b
B6
B7b
8
B0
B1b
B7
ORb
7
Gorb
B0b
OR
VCC
6
VCC
VCC
GAIN
VCC
5
GND
GND
GND
GND
4
VCC
VCC
GND
VINB
3
VEE
VEE
GND
VIN
2
GND
VCC
GND
GND
GND
GND
VEE
VCC
VEE
GND
GND
1 Ball A1 Index other side
NC
GND
CLK
CLKB
GND
GND
VEE
VCC
VEE
Diode
NC
A
B
C
D
E
F
G
H
J
K
L
BOTTOM VIEW
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TS8308500
2193A–BDC–04/03
TS8308500
TS8308500 Capacitors and Resistors Implant Figure 48. TS8308500 Capacitors and Resistors Implant
GND
0.9 mm
100 pF
∅ 7.0 mm
DVEE
0.9 mm
GND
VCC
100 pF
GAIN
GND
100 pF
VINB
GND
50Ω
GND
VIN
50Ω
0.9 mm
VEE
VCC
VEE
CLKB
CLK
100 pF
100 pF
100 pF
50Ω
50Ω
GND
GND
GND
GND
GND
0.9 mm
Only on-package marking electrically isolated
Note:
R and C discrete components are 0603 size (1.6 x 0.8mm)
GND
VCC
100 pF
GND
VEE
100 pF
GND
VCC
100 pF
GND
VCC
100 pF
GORB
GND
100 pF
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2193A–BDC–04/03
Outline Dimensions Figure 49. Outline Dimensions - 68 Pins CBGA
CBGA 68 package. AL203 substrate. Package design. Corner balls (x4) are not connected (mechanical ball). Balls : 1.27 mm pitch on 11x11 grid. View balls side
1.27
Top side with soldered R, C devices (using solder Sn/Pb 63/37)
0.20
T
-T0.95 max Balls side Balls Sn/Pb 63/37 AI203 substrate
11 10 9 8 7 6 5 4 3
50 Ω
100 pF
15.00 ± 0.15 mm
7.84
7.84
AI203 Ceramic Cap. Glued and embedded in substrate
2 1
Ball A1 Index other side
A
B
C
D
E
F
G
H
J
K
L
-B-
15.00 ± 0.15 mm
-A-
D
68 x ∅ D = 0.80 ± 0.10 mm
0.40 T A B (Position of array of balls/edges A and B) 0.15 T (Position of balls within array)
1.27 ref
Detail of ball x2
0.63 ± 0.10
1.00
1.45 ± 0.12
All units in mm
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TS8308500
2193A–BDC–04/03
0.15
TS8308500
Cross Section Figure 50. Cross Section
0.20 T
-TTop side with soldered R, C devices (using solder Sn/Pb 63/37) 0.95 max Balls side
Balls Sn/Pb 63/37 100 pF
AI203 substrate
AI203 Ceramic Cap. Glued on substrate
50 Ω
(0.20) (2 x 0.20) (0.25) (0.20)
1.45 ± 0.12 All units in mm
0.15
(0.400)
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2193A–BDC–04/03
Thermal And Moisture Characteristics
Thermal Resistance from Junction to Ambient: RTHJA The following table lists the convection thermal performances parameters of the device itself, with no external heatsink added. Table 9. Thermal Resistance
Air Flow (m/s) 0 0.5 1 1.5 2 2.5 3 4 5 45 35.8
Rthja (deg.C/W) 50 40 30 20 10 0 0 1 2 3 Air Flow (m/s) 4 5
Estimated ja Thermal Resistance (°C/W)
30.8 27.4 24.9 23 21.5 19.3 17.7
Thermal Resistance from Junction to Case: RTHJC
The typical value for Rthjc is given as 6.7°C/W (8°C/W max). This value does not include thermal contact resistance between package and external component (heatsink or PC Board). As an example, 2.0°C/W can be taken for 50 µm of thermal grease.
CBGA68 Board Assembly with External Heatsink
It is recommended that an external heatsink or specifically designed PCB be used. Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device. Figure 51. CBGA68 Board Assembly
50.5
24.2
20.2 32.5
6.8 31 Board
Note:
Units = mm
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TS8308500
2193A–BDC–04/03
TS8308500
Moisture Characteristics This device is sensitive to moisture (MSL3 according to JEDEC standard): Shelf life in sealed bag: 12 months at
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