TSS463-AAR

Features • • • • • • • • • • • • • • • • Fully Compliant to VAN Specification ISO/11519-3 Handles All Specified Module Types Handles All Specified Message Types Handles Retransmission of Frames on Contention and Errors 3 Separate Line Inputs with Automatic Diagnosis and Selection Normal or Pulsed (Optical and Radio Mode) Coding VAN Transfer Rate: 1 Mbit/s Maximum SPI/SCI Interface – SPI Transfer Rate: 4 Mbit/s Maximum – SCI Transfer Rate: 125 Kbit/s Maximum Idle and Sleep Modes 128 Bytes of General-purpose RAM 14 Identifier Registers with All Bits Individually Maskable 6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the Reset Pin Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output Single +5V Power Supply 0.8 µm CMOS Technology SO16 Package VAN Data Link Controller with Serial Interface TSS463-AA Description The TSS463AA is a circuit that allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, that minimizes electrical wire usage. It can be used to interconnect powerful functions to control and interface car body electronics (lights, wipers, power window, etc.). The TSS463AA is fully compliant with the VAN ISO Standard 11519-3. This standard supports a wide range of applications such as low-cost remote-controlled switches. Typically it is used for lamp control, complex, highly-autonomous, distributed systems, which require fast and secure data transfers. The TSS463AA is a microprocessor-interfaced line controller for mid- to high-complexity bus-masters and listeners like dashboard controllers, car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-byte RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor, including SPI/SCI interface, to be connected easily to the TSS463AA. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS463AA analyzes the messages received or transmitted according to 6 different criteria including some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagnosis and selection. The interface allows for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. 4205B–AUTO–12/04 1 Block Diagram 2 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Pin Configuration TOP VIEW 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MISO SS INT VDD XTAL1 XTAL2 TEST/VSS CKOUT MOSI SCLK RESET GND TXD RXD0 RXD2 RXD1 Pin Description I/O Type O 3-state I trigger CMOS Open-drain Power I CMOS O Ground O I CMOS Pull-down I CMOS Pull-down I CMOS Pull-down O 3-state Ground I trigger CMOS pull-up I trigger CMOS I trigger CMOS Pin Name MISO SS INT VDD XTAL1 XTAL2 TEST/VSS CKOUT RXD1 RXD2 RXD0 TXD GND RESET SCLK MOSI Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Hardware Reset (active low) SPI/SCI Clock Input SPI/SCI Data Input Pin Function SPI/SCI Data Output SPI/SCI Slave Select (active low) Interrupt (active low) + 5V power supply Crystal oscillator or clock input pin from 1 to 16 MHz Crystal oscillator output pin Test mode input Buffered clock output VAN bus input 1 VAN bus input 2 VAN bus input 0 VAN bus output 3 4205B–AUTO–12/04 Application The TSS463AA is a microprocessor controlled line controller for the VAN bus. It can interface to virtually any microprocessor which includes SPI or SCI interface. • • • The TSS463AA provides one full Motorola compatible SPI interface. It includes one full compatible Intel UART (mode 0 only). And finally, one 9-bits SCI interface is also integrated. In addition, the circuit features a single interrupt pin. This pin can be treated as level sensitive. For example, if there is a pending interrupt inside the circuit when another interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the internal write strobe (typically 20 ns). Figure 1. Typical Application With Motorola SPI Mode Remaining pins SCLK MOSI MISO(2) PORT X.Y IRQ General I/O (if needed) 100K MISO 1 SS INT 2 16 15 SCLK RESET (1) mC Microcontroller MOSI TSS463 3 VDD 4 5 6 14 13 12 11 10 9 RxD0 RxD2 RxD1 VAN Bus GND TxD CKOUT XTAL1 XTAL2 RESET (1) TEST/VSS 7 CKOUT 8 Notes: 1. The TSS463AA RESET pin can either be connected to GND through a 1 µF capacitor, or the µC RESET pin or unconnected (inactive with internal pull-up). 2. Leaving MISO output pin floating in high impedance mode slightly increases standby consumption. A 100 KΩ pull-up/pull-down resistor is recommended. 4 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Microprocessor Interface Interface Modes Motorola SPI Mode The processor controls the TSS463AA by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. The TSS463AA must be connected with an SPI or SCI serial interface. The following section provides information on switching from one mode to another. The first two bytes to be sent by the master (CPU) are called “Initialization Sequence”: This sequence provides a proper asynchronous RESET in the TSS463AA and it selects the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown on Figure 4. Two 0x00 will cause an internal RESET and assert the Motorola SPI mode, Two “0xFF” will provide an internal RESET and assert the Intel® SPI mode and “9 bits to 0 followed by 0xFF or 0xFE” will generate an internal RESET and assert the 9-bits SCI mode. Figure 2. Mode Configuration Byte SPI 8 Pulses SCLK MOSI 0x00 or 0xFF 0x00 0xFF Motorola Intel SS Internal RESET Internal RESET and SPI Mode (Intel or Motorola) SCI 9 Pulses SCLK MOSI 0 . 0000 . 0000 1 . 1 . 1111 111 SS Internal RESET Internal RESET and SCI Mode The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola protocol. The interface is implemented for slave-mode only (the TSS463AA can not generate SPI frames by itself). The SPI interface allows the interconnection of several CPUs and peripherals on the same printed circuit board. The SPI mode interface consists of 4 pins: separate wires are required for data and clock, so the clock is not included in the data stream as shown in Figure 5. One pin is needed for the serial clock (SCLK), two pins for data communication MOSI and MISO and one pin for Slave Select (SS). 5 4205B–AUTO–12/04 Figure 3. SPI Data Stream SPI 8 Pulses SCLK MOSI 0x55 MISO 0x66 SS SCLK: Serial Clock The master device provides the serial clock for the slave devices. Data is transferred synchronously with this clock in both directions. The master and the slave devices send/receive a data byte during an eight-clock pulse sequence. The MOSI pin is the master device data output (CPU) and the slave device data input (TSS463AA). Data is transferred serially from the master to the slave on this line; most significant bit (MSB) first, least significant bit (LSB) last. The MISO pin is configured as the slave device data output (TSS463AA) and as master device data input (CPU). When the slave device is not selected (SS = 1), this pin is in high impedance state. The SS pin is the slave chip select. It is low active. A low state on the Slave Select input allows the TSS463AA to accept data on the MOSI pin and send data on the MISO pin. The Slave Select signal must not toggle between each transmitted byte and should be left at a low level during the whole SPI frame. SS must be asserted to inactive high level at the end of the SPI frame. As mentioned before, if SS is not asserted, MISO pin is in a high impedance state and incoming data is not driven to the serial data register. MOSI: Master Out Slave In MISO: Master In Slave Out SS: Slave Select SPI Protocol The general format of the data communication in the SPI frame between the TSS463AA and the host is a bit-for-bit exchange on each SCLK clock pulse. Data is arranged in the TSS463AA such that the significance of a bit is determined by its position from the start for output and from the end for input, most significant bit (MSB) is sent first. Bit exchanges in multiples of 8 bits are allowed. The Idle Clock Polarity (CPOL) and the Clock Phase (CPHA) are not programmable: the CPOL and CPHA values to be programmed in the master (CPU) are CPOL = CPHA = 1. This is available for all modes. Waveforms with transmit and sample points are shown in Figure 6. 6 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 4. CPOL and CPHA in the TSS463AA CPOL = CPHA = 1 Data Sample Points SPI 8 Pulses SCLK MOSI MISO SS 0x55 0x66 Data Transmit Points At the beginning of a transmission over the serial interface, the first byte is the address of the TSS463AA register to be accessed. The next byte transmitted is the control byte which determines the direction of the communication. The following bytes are data bytes (consecutive bytes are written in or read from Address, Address + 1, Address + 2,..., Address + n with n = 0 to 28). To make sure the TSS463AA is not out of synchronization, the SPI interface will transmit data “0xAA" and "0x55” on the MISO pin during address and control byte time. This way, the master always ensures the TSS463AA is well-synchronized. If the TSS463AA is out of synchronization, the master can assert the SS pin inactive to re synchronize the SPI interface or can assert the RESET pin active or can send an initialization sequence. When the SS pin is inactive, the SCLK is allowed to toggle. This will have no effect on the TSS463AA SPI module. SPI Control Byte The SPI control byte is transmitted by the master (CPU) to the TSS463AA. It specifies whether it is a TSS463AA Write or Read. Table 1. SPI Control Byte 7 DIR 6 1 5 1 4 0 3 0 2 0 1 0 0 0 DIR: Serial Transfer Direction Zero : Read Operation. The data bytes will be read by the master (CPU) from the TSS463AA. One : Write Operation. The data bytes will be written by the master (CPU) to the TSS463AA. In both cases, address auto-increment mechanism will take place when more than one data byte is read or written. This mechanism is inhibited when address value reaches 0xFF. The seven following bits are reserved and must be equal to: 1100000. When the master (CPU) conducts a write, it sends an address byte, a control byte and data bytes on its MOSI line. The slave device (TSS463AA) will send, if well-synchronized, “0xAA” during the address byte and “0x55” during the control byte on its MISO line. 7 4205B–AUTO–12/04 When the master (CPU) conducts a read, it sends an address byte, a control byte and dummy characters ("0xFF" for instance) on its MOSI line. In the case of a VAN messages RAM read (VAN frame received), the first data byte sent back by the TSS463AA on its MISO pin is the data length so the master knows how many dummy characters it must send to read the VAN frame properly. When the TSS463AA responds back with data, it will not take care of the MOSI line. The master must activate and de-activate SS between each data frame. Synchronization bytes must be monitored carefully. For instance, if “0xAA” and “0x55” are not monitored correctly, then the previous transmission may be incorrect too. A control byte containing "0x00" or "0xFF" is forbidden except during an "Initialization Sequence". Intel SPI Mode The Intel SPI mode is the second type of interface. As mentioned before, the TSS463AA enters this mode if the Initialization Sequence contains (first two bytes received) "0xFF, 0xFF". This mode is fully compatible to the Intel UART serial interface programmed in mode 0 only. It is the same as Motorola SPI mode (same CPOL and CPHA) but with inverted communication sense (LSB first and MSB last). The protocol is also the same. However, from the master point of view (host microcontroller), the hardware is different. Figure 5 shows how to connect the TSS463AA and Intel type microcontroller. Figure 5. Typical Application With the 8051 UART in Mode 0 General I/O Remaining pins optional TXD RXD 100k (if needed) PORT X.y PORT X.z IRQ INT 3 VDD C1 4 XTAL1 5 XTAL2 6 C2 TEST/VSS 7 XTAL1 CKOUT 8 10 RxD1 9 11 RxD2 VAN Bus 14 SS MISO 1 2 16 15 SCLK RESET (1) MOSI TSS463 Microcontroller RESET (1) GND 13 TXD 12 RxD0 Notes: 1. The RESET pin can either be connected to GND through a 1 µF capacitor, or the microcontroller RESET pin or unconnected (inactive with internal pull-up). 8 TSS463-AA 4205B–AUTO–12/04 TSS463-AA The master device provides the serial clock on the TxD pin and is still connected to SCLK pin of the slave device. Then, the RxD replaces the MOSI and MISO pins and is a bi-directional pin. To achieve a correct communication, the user should add a few gates to connect the master RxD pin to the MOSI-MISO slave pins. Figure 5 proposes two 3-state buffers controlled by the master through a general purpose I/O pin. It is obvious that, in this Intel SPI mode, the master cannot monitor the "0xAA and 0x55" synchronization bytes while sending the address and control bytes. It is the only exception in this mode compared with the Motorola SPI mode. SCI Mode The SCI mode is the third type of interface. The TSS463AA enters this mode if the Initialization Sequence contains (first two bytes received) "0x00, 0xFF". The SCI is compatible with a 9-bits SCI protocol. The interface is implemented for slavemode only (the TSS463AA cannot generate SCI frames by itself). The SCI interface allows an interconnection of several CPUs and peripherals on the same printed circuit board. The SCI mode interface consists of 4 pins: separate wires are required for data and clock, so the clock is not included in the data stream as shown in Figure 6. One pin is needed for the serial clock (SCLK), two pins for data exchange MOSI and MISO and one pin for Slave Select SS. Figure 6. SCI Data Stream SCI 9 Pulses SCLK MOSI 0x55 MISO 0x66 SS SCLK: Serial Clock The master device provides the serial clock for the slave devices. Data is transferred synchronously with this clock in both directions. The master and the slave devices exchange a data byte during a nine clock pulses sequence. However, the TSS463AA will only monitor 8 bits on its MOSI line and send 9 bits on its MISO line. The MOSI pin is the master device data output (CPU) and the slave device data input (TSS463AA). Data is transferred serially from the master to the slave on this line; least significant bit (LSB) first, most significant bit (MSB) last. The TSS463AA will only monitor 8 bits starting from the LSB to MSB-1. The MISO pin is configured as the slave device data output (TSS463AA) and as master device data input (CPU). When the slave device is not selected (SS = 1), this pin is in high impedance state. The value of the MSB (9th bit) sent on the MISO pin will always be "1" and should not be used by the master. The SS pin is the slave chip select. It is low active. A low state on the Slave Select input allows the TSS463AA to accept data on the MOSI pin and send data on the MISO pin. MOSI: Master Out Slave In MISO: Master In Slave Out SS: Slave Select 9 4205B–AUTO–12/04 The Slave Select signal must not toggle between each transmitted byte and therefore, should be left at a low level during the whole SCI frame. SS must be asserted to inactive high level at the end of the SCI frame. If SS is not asserted, MISO pin is in high impedance state and incoming data is not driven to the serial data register. SCI Protocol Same as the SPI protocol described earlier except for data arranging (LSB first and MSB last). Only 8 bits are monitored by the TSS463AA and master must monitor the 8 first bits too (9th bit always equal to 1). SCI Control Byte Same as the SPI control byte. Clocks and Speed Considerations SCLK and XTAL Clocks The SPI/SCI speed rate is given by the CPU producing SCLK. XTAL clock controls the speed rate on the VAN bus. The two clocks are asynchronous, but a minimum SPI/SCI interframe spacing must be apply according to XTAL clock. Within an SPI byte, the maximum speed allowed on the MOSI line is 4 Mbits/s. For example, when using a 1 MHz oscillator (sufficient to provide 62.5 kTS/s on the VAN bus) the minimum inter-character delay is 12 µs (12 oscillator periods). Speed considerations are detailed in Figure 7. Figure 7. SPI Speed Considerations Intel and Motorola SPI Modes 4 Mbits/s Max for SCLK SCLK MOSI SS 4 Xtal Min (4 s at 1 MHz) Address Control Data 8 Xtal Min (8 s at 1 MHz) 15 Xtal Min (15 s at 1 MHz) 12 Xtal Min (12 s at 1 MHz) SCI Mode Within an SCI 9-bits data, the maximum speed allowed on the MOSI line is 125 Kbits/s. When using a 1 MHz oscillator, the data transfer speed and the minimum delay time between SCI bytes are shown on Figure 8. 10 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 8. SCI Speed Considerations 125 Kbits/s Max for SCLK SCLK Start Bit MOSI Stop Bit Address Control Data SS 4 Xtal Min (4 s at 1 MHz) (8 s at 1 MHz) 8 Xtal Min 15 Xtal Min (15 s at 1 MHz) 12 Xtal Min (12 s at 1 MHz) Interrupts If an event occurs in the TSS463AA that needs the attention of the processor, this will be signalled on the active low, open-drain interrupt request pin. The event that creates this request is controlled by the internal registers. Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B), the INT pin will be released momentarily. This enables the TSS463AA to work with processors that have either edge or level sensitive interrupt inputs. Reset Asynchronous Reset The reset is applied asynchronously or synchronously to the XTAL clock. It can be done either by the RESET pin (hardware asynchronous reset) or by software (software asynchronous reset). The RESET pin is a CMOS trigger input with a pull-up resistor (~ 70 kΩ). An external 1 µF capacitor to GND provides to RESET pin an efficient behavior. The asynchronous software reset is made by the "Initialization Sequence" described in “Motorola SPI Mode” on page 5. Two "0x00" bytes provide an asynchronous software reset and configure the TSS463AA in the Motorola SPI mode while two "0xFF" bytes provide a reset and configure the component in the Intel SPI mode and "0x00 followed by 0xFF " provide a reset and configure the component in the SCI mode. The SS pin must be asserted as shown on Figure 9. T he SPI/SCI logic will monitor these two bytes and provide an internal reset pulse asserting the TSS463AA in the right mode. Synchronous Reset A synchronous reset (regarding XTAL clock) is available on the TSS463AA during current operation. It is made through the GRES command bit of the Command Register (address 0x03). The two kinds of reset are ordered and filtered. Then the internal reset, always asserted asynchronously, enables the internal oscillator. Then it waits for 12 clock periods and the oscillator stability. The different blocks of the TSS463AA need to be turned on synchronously. The release of the internal reset is synchronous and a loose of clock can let the TSS463AA in permanent reset after applying Reset. It is important to note that even after a reset on the RESET pin, the user should wait for 12 clock periods before sending the "Initialization Sequence" in order to select the SPI or SCI mode (because the default mode after a hardware reset is the Motorola SPI mode). 11 4205B–AUTO–12/04 Figure 9. Asynchronous Software Reset with UART Intel Mode 4 XTAL Min SCLK 15 XTAL Min MOSI 0xFF 0xFF SS Detection of Forbidden Control Reset Internal Pulse End of Chip Select Oscillator An oscillator is integrated in the TSS463AA, and consists of an inverting amplifier of which the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As shown in Figure 5, two capacitors have to be connected from the crystal pins to ground. The values of C2 depend on the frequency chosen and can be selected using the schematic given in Figure 39. If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1 input. Note that this pin will behave as a CMOS level compatible Schmitt trigger input. In this case the XTAL2 output should be left unconnected. The oscillator also features a buffered clock output pin CKOUT. The signal on this pin is directly buffered from the XTAL1 input, without inversion. There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground, and unless this pin is firmly connected to ground, with decoupling capacitors, the oscillator will not operate correctly. The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for factory use, and the functionality of this mode is not specified in any way. The TEST/VSS pin is subject to change without notice, the only exception is for incoming inspection tests using the test program. The clock signal is then fed to the clock generator that generates all the necessary timing signals for the operation of the circuit. The clock generator is controlled by a 4-bit code called the clock divider. f ( XTAL 1 ) f ( TSCLK ) = -----------------------n × 16 12 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Table 2. Clock Divider 8 MHz Clock Divider 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Divide by 1 2 4 8 16 32 64 128 1.5 3 6 12 24 48 96 192 KTS/s 500 250 125 62.5 31.25 15.625 7.813 3.906 333.333 166.666 83.333 41.666 20.833 10.416 5.208 2.604 Kbits/s 400 200 100 50 25 12.5 6.25 3.125 266.666 133.333 66.666 33.333 16.666 8.333 4.166 2.083 KTS/s 375 187.50 93.75 46.875+ 23.438 11.718 5.859 500 250 125 62.50 31.25 15.625 7.813 3.906 1.953 6 MHz Kbits/s 300 150 75 37.5 18.75 9.375 4.688 400 200 100 50 25 12.50 6.25 3.125 1.5625 KTS/s 250 125 62.50 31.25 15.625 7.813 3.906 1.953 166.666 83.333 41.666 20.833 10.416 5.208 2.604 1.302 4 MHz Kbits/s 200 100 50 25 12.5 6.25 3.125 1.562 133.333 66.666 33.333 16.666 8.333 4.166 2.083 1.042 KTS/s 125 62.50 31.25 15.625 7.813 3.906 1.953 166.666 83.333 41.666 20.833 10.416 5.208 2.604 1.302 0.651 2 MHz Kbits/s 100 50 25 12.5 6.25 3.125 1.562 133.333 66.666 33.333 16.666 8.333 4.166 2.083 1.042 0.521 13 4205B–AUTO–12/04 VAN Protocol Line Interface There are three line inputs and one line output available on the TSS463AA. Which of the three inputs to use is either programmable by software or automatically selected by a diagnosis system. The diagnosis system continuously monitors the data received through the three inputs, and compares it with each other and the selected bitrate. It then chooses the most reliable input according to the results. The data on the line is encoded according to the VAN standard ISO/11519-3. This means that the TSS463AA is using a two level signal having a recessive (1) and a dominant (0) state. Furthermore, due to the simple medium used, all data transmitted on the bus is also received simultaneously. The VAN protocol is hence a CSMA/CD (Carrier Sense Multiple Access Collision Detection) protocol, allowing for continuous bitwise arbitration of the bus, and non-destructive (for the higher priority messa ge) collision detection. Figure 10. CSMA/CD Arbritration Arbitration field R D R D R D 1 Node a loses the arbitration Node a releases the bus 3 Node b wins the arbitration Node a: TxD 2 Node b: TxD Node c: TxD Node c loses the arbitration Node c releases the bus On Bus: DATA R D R: Recessive Level D: Dominant Level In addition to the VAN specification there is also a pulsed coding of the dominant and recessive states. This mode is intended to be used with an optical or radio link. In this mode, the dominant state for the transmitter is a low pulse, (2x prescaled clocks at the beginning of the bit) and the recessive state is just a high level. When receiving in this mode, it is not the state of the signal itself which is decoded, but the edges. Also, reception is imposed on the RxD0 input, and the diagnosis system does not operate correctly. In addition, in this mode there is an internal loopback in the circuit since optical transceivers are not able to receive the signal that they transmit. 14 TSS463-AA 4205B–AUTO–12/04 TSS463-AA In Figure 11 the pulsed waveforms are shown. In Figure 14 through Figure 20 the low " timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominant waveform showed in Figure 11 if the correct representations for pulsed coding are to be seen. Figure 11. State Encoding VAN Frame Figure 12. VAN Bus Frame SOF Identifier Field Command EXT RAK R/W RTR Data Field Frame Check Sum EOD ACK EOF The VAN bus supports three different module (unit) types: 1. The Autonomous module, which is a bus master. It can transmit Start Of Frame (SOF) sequences, it can initiate data transfers and can receive messages. 2. The Synchronous access module. It cannot transmit SOF sequences, but it can initiate data transfers and can receive messages. 3. The Slave module, which can only transmit using an in-frame mechanism and can receive messages. Figure 13. Hierarchical Access Methods Autonomous Rank 0 SOF ID Synchronous Rank 1 ID COM Slave RTR COM DATA FCS EOD ACK EOF DATA FCS EOD ACK EOF Rank 16 DATA FCS EOD ACK EOF Figure 12 shows a normal VAN bus frame. It is initiated with a Start of Frame (SOF) sequence shown in Figure 14. The SOF can only be transmitted by an autonomous module. During the preamble, the TSS463AA will synchronize its bit rate clock to the data received. 15 4205B–AUTO–12/04 Figure 14. Framing Sequences VAN BUS START SYNC PREAMBLE SEQUENCE START OF FRAME VAN BUS SEQUENCE END OF DATA ACK END OF FRAME NUMBER OF PRESCALED CLOCKS 0 16 32 48 64 80 96 112 128 144 160 176 192 When the complete SOF sequence has been transmitted or received, the circuit will start the transmission or reception of the identifier field. All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are transmitted using enhanced Manchester code. In enhanced Manchester code, three NRZ bits are transmitted first followed by one Manchester bit, then three more NRZ bits followed by one Manchester bit and so on. Since the high state is recessive and the low state is dominant, the bus arbitration can be done. If a module wants access to the bus, it must first listen to the bus during one full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period to determine whether the bus is free or not (i.e. no dominant states received). Figure 15. Data Encoding VAN BUS SEQUENCE NRZ 0 NRZ 1 VAN BUS SEQUENCE MANCHESTER 0 VAN BUS SEQUENCE MANCHESTER 1 NUMBER OF PRESCALED CLOCKS 0 8 16 24 32 The IFS is defined to be a minimum of 64 prescaled clock periods. The TSS463AA, accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence. Once the bus has been determined as being free, the module must, if it is an autonomous module, emit an SOF sequence or, if it is a synchronous access module, wait until it detects a preamble sequence. At this point there could be several modules transmitting on the bus, and there is no possibility of knowing if this is the case or not. Therefore, the first field in which arbitra16 TSS463-AA 4205B–AUTO–12/04 TSS463-AA tion can be performed is the identifier field. Since the logical zeroes on the bus are dominant, and all data is transmitted with the most significant bit (MSB) first, the first module to transmit a logical zero on the bus will be the prioritized module, i.e. the message that is tagged with the lowest identifier will have priority over the other messages. It is possible that two messages transmitted on the bus will have the same identifier. The TSS463AA, therefore, continues the arbitration of the bus throughout the whole frame. Moreover, if the identifier in transmission has been programmed for reception as well, it transmits and receives messages simultaneously, right up until the Frame Check Sequence (FCS). Only then, if the TSS463AA has transmitted the whole message, it discard the message received. Arbitration loss in the FCS field is considered as a CRC error during transmission. This feature is called full data field arbitration, and it enables the user to extend the identifier. For instance it can be used to transmit the emitting modules address in the first bytes of the data field, thus enabling the identifier to specify the contents of the frame and the data field to specify the source of the information. The identifier field of the VAN bus frame is always 12 bits long, and it is always followed by the 4-bit command field: • The first bit of the command is the extension bit (EXT). This bit is defined by the user on transmission and is received and retained by the TSS463AA. To conform with the standard it should be set to 1 (recessive) by the user, else the frame is ignored without any IT generation. The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the receiving module must acknowledge the transfer with an in-frame acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must contain an acknowledge absent sequence. The third bit is the Read/Write (R/W). This bit indicates the direction of the data in a frame. – – If set to zero, it is a "write" message, i.e., data transmitted by one module to be received by another module. If it is set to one, it implies a "read" message, i.e. a request that another module should transmit data to be received by the one that requested the data (reply request message). • • • Last in the command field is the Remote Transmission Request bit (RTR). This bit is a logical zero if the frame contains data and a logical one if the frame does not contain data. In order to conform with the standard, a received frame includes the combination R/W. RTR = 01 is ignored without any IT generation. All the bits in the command field are automatically handled by the TSS463AA, so the user need not to be concerned for encoding and decoding of these bits. The command bits transmitted on the VAN bus are calculated from the current status of the active message. The data field comes after the command field. This is just a sequence of bytes transmitted MSB first. In the VAN standard the maximum message length is set to 28 bytes, but the TSS463AA handles messages up to 30 bytes. The next field is the FCS field. This field is a 15 bit CRC checksum defined by the following generator polynomial g(x) of order 15: g(x)= x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1 The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is performed before transmission. 17 4205B–AUTO–12/04 However, since the CRC is calculated automatically from the identifier, command and data fields by the TSS463AA, therefore, the user should not be concerned with the circuit. When the frame check sequence has been transmitted, the transmitting module must transmit an End of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to terminate the transfer. Figure 16. Acknowledge Sequences VAN BUS SEQUENCE POSITIVE ACKNOWLEDGE VAN BUS SEQUENCE ABSENT ACKNOWLEDGE NUMBER OF PRESCALED CLOCKS 0 8 16 24 32 Frame Examples The frames transmitted on the VAN bus are generated by several modules, each supplying different parts of the message. Figure 17 through Figure 20 show the four frame types specified in the VAN standard, and the module that is generating the different fields. • The most straightforward frame is the normal data frame in Figure 17. Like all other frames, it is initiated with a SOF sequence. This sequence is generated by a bus master (not shown in the figure). During this frame, there is basically only one module transmitting with the exception of the acknowledgement, generated by the receiving module if requested in the RAK bit. • The reply request frame with immediate reply in Figure 18 is the only frame in which a slave module can transmit data by filling it into the appropriate field. The only difference for the frame on the bus is that the R/W bit has changed state compared to the normal frame. This is a highly interactive frame where a bus master generates the SOF and the initiator generates the identifier, the three first bits of the command, and the acknowledge. The RTR bit, the data field, the frame check, the EOD and the EOF are all generated by the replying module. • The reply request frame with deferred reply in Figure 19 is basically the same frame as the reply request frame with immediate reply, but since the requested module does not generate the RTR bit the requesting module will continue with the frame check, the EOD and the EOF. During this frame, the requested module will only generate the acknowledge, and only if this was requested by the initiator through the RAK bit. • Finally, the deferred reply frame in Figure 20 which is sent when a module has prepared a reply for a reply request that has been received earlier. This frame very closely mimics the normal data frame with the exception is the R/W bit that has changed state. 18 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 17. Normal Data Frame With acknowledgment EOD EXT RAK R/W RTR (*) ACK TRANSMITTING module SOF IDENTIFIER DATA CRC EOF RECEIVING module EXT RAK R/W RTR (*) EOD FRAME on bus SOF IDENTIFIER DATA CRC ACK ACK EOF EXT RAK R/W RTR ACK : : : : : Recessive from Transmitter Recessive for acknowledge from Transmitter Dominant from Transmitter Dominant from Transmitter(*) Manchester bit Positive from Receiver because RAK is Recessive Without acknowledgment EOD EXT RAK R/W RTR (*) ACK TRANSMITTING module SOF IDENTIFIER DATA CRC EOF RECEIVING module EXT RAK R/W RTR (*) EOD FRAME on bus SOF IDENTIFIER DATA CRC ACK EOF EXT RAK R/W RTR ACK : Recessive from Transmitter : Dominant for no acknowledge from Transmitter : Dominant from Transmitter : Dominant from Transmitter(*) Manchester bit : Absent from Transmitter and from Receiver because RAK is Dominant 19 4205B–AUTO–12/04 Figure 18. Reply Request Frame with Immediate Reply EXT RAK R/W RTR (*) SOF IDENTIFIER ACK EOD DATA CRC ACK REQUESTING module RTR (*) REQUESTED module EOF EXT RAK R/W RTR (*) EOD FRAME on bus SOF IDENTIFIER DATA CRC ACK EOF EXT RAK R/W RTR ACK : : : : : Recessive from Requestor Recessive for acknowledge from Requestor Recessive from Requestor Recessive from Requestor and Dominant from Requestee (*) Manchester bit Absent from Requestee and Positive from Requestor because RAK is Recessive Figure 19. Reply Request Frame with Deferred Reply EXT RAK R/W RTR (*) EOD REQUESTING Module SOF IDENTIFIER CRC ACK ACK ACK EOF REQUESTED Module EXT RAK R/W RTR (*) FRAME on Bus SOF IDENTIFIER CRC EOD EOF EXT : Recessive from Requestor RAK : Recessive for acknowledge from Requestor R/W : Recessive from Requestor RTR : Recessive from Requestor - (*) Manchester bit ACK : Absent from Requestor and Positive from Requestee because RAK is Recessive 20 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 20. Deferred Reply Frame EXT RAK R/W RTR (*) EOD ACK REPLYING module SOF IDENTIFIER DATA CRC EOF RECEIVING module EXT RAK R/W RTR (*) EOD FRAME on bus SOF IDENTIFIER DATA CRC ACK ACK EOF EXT RAK R/W RTR ACK : : : : : Recessive from Replyer Recessive for acknowledge from Replyer Recessive from Replyer - (*) Manchester bit Dominant from Replyer Absent from Replyer and Positive from Receiver because RAK is Recessive 21 4205B–AUTO–12/04 Diagnosis System The purpose of the diagnosis system is to detect any short or open circuits on either the DATA or DATA lines and to permit, if it is possible, to carry the communications on the non-defective line. The diagnosis system is based on the assumption that three separate line receivers are connected to the VAN bus see Figure 1: • • One of the line receivers is connected in differential mode, sensing both DATA and DATA signals, and is connected to the RxD0 input. The other two line receivers are operating in single wire mode and are sensing only one of the two VAN bus signals: – – The line receiver sensing DATA is connected to RxD1 The line receiver sensing DATA is connected to RxD2 The diagnosis system analyzes and compares the data sent over both VAN lines. So, the diagnosis system executes a digital filtering and transition analyses. In order to perform its investigation, three internal signals are generated, RI (Return to Idle), SDC (Synchronous Diagnosis Clock) and TIP (Transmission In Progress). One of four operating modes can be chosen to manage the results of the diagnosis system. Diagnosis States If the diagnosis system finds a failure on any of the VAN bus signals, it changes from nominal to degraded mode, and connects the line receiver not coupled to the failing signal to the reception logic. When the diagnosis system finds that the failing signal is working again, it returns to nominal mode and re-connects the differential line receiver to the reception logic. A major error occurs when both the VAN bus signals failed. Figure 21. Diagnosis States Nominal Major Error Degraded Data Degraded Data - Failure during the frame - Default of transitions on the valid input between 2 consecutive SDC rising edges. - Protocol fault -In specified selection mode, every RI pulse when an EOF is detected or through an active SDC. -In automatic selection mode and SDC active, no failuresampled by 2 consecutive SDC rising edges. -General Reset 22 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Status bits give permanent information on the diagnosis performed, whatever the programmed operating mode. This is encoded over three bits: Sa, Sb and Sc. • Sa and Sb bits indicate the four possible states of the VAN bus. Table 3. Status Bits: Sa and Sb Sa Sb Communication Mode 0 0 Fault Status Mode 0 1 Fault Status Mode 1 0 Fault Status Mode 1 1 Fault Status Nominal No fault on VAN bus Differential communication on DATA and DATA Degraded on DATA Fault on DATA Communication on DATA Degraded on DATA Fault on DATA Communication on DATA Major error Fault on DATA and DATA No communication on DATA and DATA (attempt to communicate alternatively on DATA then DATA every SDC period) • Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others in the input comparison analysis performed by the diagnosis system, Sc is set. The only way to reset this status bit is through the RI signal or a general reset. Internal Operations Digital Filtering If several spurious pulses occur during one bit, the diagnosis for defective conductor may occur. To avoid such errors, digital filters are implemented. Filtering operation is based on sampling of the comparator output signals. A transition is taken into account only if it is observed over five samples (1/16th of timeslot). Transition Analyses These analyses are continuously done on the effective edges on comparators after digital filtering. • Asynchronous diagnosis The asynchronous diagnosis is done by comparing the number of edges on DATA and DATA. If four edges are detected on one input and no edges on the other during the same period, the second input is considered faulty and the diagnosis mode will change to one of the degraded modes. • Synchronous diagnosis The synchronous diagnosis counts the number of edges on the data input connected to the reception logic during one SDC period. If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode. 23 4205B–AUTO–12/04 • Transmission diagnosis The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output. At a time when the transmission logic generates a dominant - recessive transition, the inputs can give different values. Taking into account the filtering delay, the bus line seen as dominant is assumed to be correct, the other one, recessive, is considered faulty. The diagnosis mode is changed to reflect that. • Protocol fault The protocol fault is detected by counting the number of consecutive dominant timeslots. If eight consecutive timeslots are dominant, the diagnosis mode will change to the major error mode. Generation of Internal Signals RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see “Diagnosis States” on page 22 and “Programming Modes” on page 25). The RI signal is disabled in automatic selection mode. The RI signal is a pulse generated when an EOF is detected. Thus, at the end of each frame, regarding the diagnosis status bit Sa, Sb and Sc, the user can make its own choice. SDC Signal (Synchronous Diagnosis Clock) This time base is used by diagnosis system in automatic selection mode (see Section “Programming Modes”, page 25) when no event is recorded on the bus. The SDC is generated either by a special SDC divider connected to the timeslot clock, or can be performed manually. The SDC clock period must be long compared to the timeslot duration. A typical SDC period should be greater than the maximum frame length appearing on the VAN network. TIP Signal (Transmission in Progress) This signal must be enabled to allow the transmission diagnosis (see Section “Transition Analyses”, page 23). The TIP turns on synchronously with the beginning of the transmission: • • • • • • for asynchronous bus access, the beginning of SOF; for synchronous bus access, the beginning of the identifier field; and for a request of in frame reply, the RTR bit of the command field. after EOF; after a losing of arbitration or a code violation detection; and for a requestor of in frame reply, when the arbitration is lost on RTR the bit. The TIP turns off synchronously with the end of the transmission: This signal is not generated when the transmission logic only sends an ACK. 24 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Programming Modes Four programming modes determine how to use the three different inputs and the diagnosis system. • • 3 specified selection modes 1 automatic selection mode Table 4. Programming Modes Ma Mb Operating Mode 0 0 1 1 0 1 0 1 Differential communication Degraded communication on RxD2 (DATA) Degraded communication on RxD1 (DATA) Automatic selection according the diagnosis status 25 4205B–AUTO–12/04 Registers The TSS463AA memory map consists of three different areas, the Control and Status registers, the Channel registers and the Message data (or Mailbox). Mapping Figure 22. Memory Map 0x78 to 0x7F (r/w) 0x70 to 0x77 (r/w) 0x68 to 0x6F (r/w) 0x60 to 0x67 (r/w) 0x58 to 0x5F (r/w) 0x50 to 0x57 (r/w) 0x48 to 0x4F (r/w) 0x40 to 0x47 (r/w) 0x38 to 0x3F (r/w) 0x30 to 0x37 (r/w) 0x28 to 0x2F (r/w) 0x20 to 0x27 (r/w) 0x18 to 0x1F (r/w) 0x10 to 0x17 (r/w) 0x0C to 0x0F 0x0B (w) 0x0A (r/w) 0x09 (r) 0x08 0x07 (r) 0x06 (r) 0x05 (r) 0x04 (r) 0x03 (w) 0x02 (r/w) 0x01 (r/w) 0x00 (r/w) Channel13 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 8 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 0x7F (r/w) 0x7E (r/w) 0xFF ID_Mask [3..0] ID_Mask [11..4] Data Byte 127 0x7C and 0x7D Reserved Reserved 0x7B (r/w) Message Length + Status 0x7A (r/w) DRAK + Message Address 0x79 (r/w) ID_TAG (lsb) + COM 0x78 (r/w) ID_TAG (msb) Channel 13 Registers ID_Mask [3..0] 0x16 (r/w) ID_Mask[11..4] ID_Mask [11..4] 0x14 and 0x15 Reserved 0x13 (r/w) Message Length + Status 0x12 (r/w) DRAK + Message Address 0x11 (r/w) ID_TAG [3..0] + COM 0x10 (r/w) ID_TAG [11..4] 0x17 (r/w) 0x17 (r/w) Channel 0 Registers Channel 0 Reserved Interrupt Reset Interrupt Enable (0x80) Interrupt Status (0x80) Reserved Last Error Status (0x00) Last Message Status (0x00) Transmit Status (0x00) Line Status (0bx01xxx00) Command (0x00) Diagnosis Control (0x00) Transmit Control (0x02) Line Control (0x00) 0x8C 0x8B 0x8A 0x89 0x88 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80 Data Byte 12 Data Byte 11 Data Byte 10 Data Byte 9 Data Byte 8 Data Byte 7 Data Byte 6 Data Byte 5 Data Byte 4 Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Register Notes: Message 1. All the non-specified addresses between 0x00 and 0x7F are considered as absent. 2. (r) means read-only register. (w) means write-only register. (r/w) means read/write register. 3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET. 26 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Control and Status Registers Line Control Register (0x00) 7 CD3 6 CD2 5 CD1 4 CD0 3 PC 2 0 1 IVTX 0 IVRX • • • Read/write register. Default value after reset: 0×00 Reserved: Bit 2, this bit must not be set by the user; a 0 must always be written to this bit. CD[3:0]:Clock Divider They control the VAN Bus rate through a Baud Rate generator according to the formula below: f ( XTAL 1 ) f ( TSCLK ) = -----------------------n × 16 PC: Pulsed Code One: The TSS463AA will transmit and receive data using the pulsed coding mode (i.e optical or radio link mode). The use of this mode implies communication via the RxD0 input and the non-functionality of the diagnosis system. Zero : (Default at reset). The TSS463AA will transmit and receive data using the Enhanced Manchester code. (RxD0, RxD1, RxD2 used). IVTX: Invert TxD output IVRX: Invert RxD inputs The user can invert the logical levels used on either the TxD output or the RxD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (Default at reset). The TSS463AA will set TxD to recessive state in Idle mode and consider the bus free (recessive states on RxD inputs). Transmit Control Register (0x01) 7 MR3 6 MR2 5 MR1 4 MR0 3 VER2 2 VER1 1 VER0 0 MT Read/Write register. Default value after reset: 0x02 MR[3:0]: Maximum Retries These bits allow the user to control the amount of retries the circuit will perform if any errors occurred during transmission. 27 4205B–AUTO–12/04 Table 5. Retries MR [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Max. # of retries 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Max. # of transmissions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: Bus contention is not regarded as an error and an infinite number of transmission attempts will be performed if bus contention occurs continuously. VER[2:0] = 001 DLC Version after reset. These bits must not be set by user. 001 must always be written to these bits. MT: Module type The three different module types are supported (see “VAN Frame” on page 15): One : The TSS463AA is at once an autonomous module (Rank 0), a synchronous access module (Rank 1) or a slave module (Rank 16). Zero: The TSS463AA is at once an synchronous access module (Rank 1) or a slave module (Rank 16). 28 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Diagnosis Control Register (0x02) 7 SDC3 6 SDC2 5 SDC1 4 SDC0 3 Ma 2 Mb 1 ETIP 0 ESDC • • Read/Write register Default value after reset: 0×00. The diagnosis is discussed in greater detail in the section “Diagnosis System” on page 22. • • • In its four high order bits, the user can program the SDC rate SDC [3:0] In its two medium order bits, the diagnosis system mode is controlled: M1, M0. In the two low order bits, the user controls if the SDC and TIP are to be generated automatically ETIP, ESDC. SDC [3:0]: SDC divider The input clock is the timeslot clock. Table 6. System Diagnosis Clock Divider SDC DIVIDER SDC [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Divide by 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 131072 262144 524288 1048576 2097152 SDC calculation: (see “SDC Signal (Synchronous Diagnosis Clock)” on page 24). Notes: 1. For each module, determine the largest interframe spacing, LIFS (*). 2. For the whole network, get the maximum LIFS, MAX-LIFS. 3. SDC period > MAX-LIFS. (*) IFS min. = 4 TS Example: For VAN frame speed rate = 62,5 KTS/s (1 TS = 16 µs), SDC >100 ms => 100 ms / 16 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111. 29 4205B–AUTO–12/04 Ma, Mb: Operating Mode Command Bits Table 7. Diagnosis System Command Bits Ma 0 0 1 1 Mb 0 1 0 1 Forces the Communication on RxD0 (differential) Forces the Communication on RxD2 (DATA) Forces the Communication on RxD1 (DATA) Automatic selection ETIP: Enable Transmission In Progress The Transmission In Progress (TIP) tells the diagnosis system to enable transmission diagnosis. One: Enable TIP generation Zero: Disable TIP generation. ESDC: Enable System Diagnosis Clock The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous diagnosis. One: Enable SDC divider. Zero: Disable SDC divider. Command Register (0x03) 7 GRES 6 SLEEP 5 IDLE 4 ACTI 3 REAR 2 0 1 0 0 MSDC • • • Write only register. Reserved: Bit 1, 2 these bits must not be set by the user; a zero must always be written to these bit. If the circuit is operating at low bitrates there might be a considerable delay between the writing of this register and the performing of the actual command (worst case 6 timeslots). The user is therefore recommended to verify, by reading the Line Status Register (0x04), that the commands have been performed. GRES: General Reset The Reset circuit command bit performs, if set, exactly as if the external reset pin was asserted. This command bit has its own auto-reset circuitry. One: Reset active Zero: Reset inactive SLEEP: Sleep Command (See Section “Sleep Command”, page 52).If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode, all non-user registers are setup to minimize power consumption. Read/write accesses to the TSS463AA via the SPI/SCI interface are impossible, the oscillator is stopped. To exit from this mode the user must apply either an hardware reset (external RESET pin) or an asynchronous software reset (via the SPI/SCI interface). One: Sleep active Zero: Sleep inactive 30 TSS463-AA 4205B–AUTO–12/04 TSS463-AA IDLE: Idle Command (See Section “Idle and Activate Commands”, page 52). If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will operate, but the TSS463AA will not transmit or receive anything on the bus, and the TxD output will be in three state. One: Idle active Zero: Idle inactive ACTI: Activate Command (See Section “Idle and Activate Commands”, page 52). The Activate command will put the circuit in the active mode, i.e it will transmit and receive normally on the bus. When the circuit is in activate mode the TxD three-state output is enabled. One: Activate active Zero: Activate inactive REAR: Re-Arbitrate Command This command will, after the current attempt, reset the retry counter and re-arbitrate the messages to be transmitted in order to find the highest priority message to transmit. One: Re-arbitrate active Zero: Re-arbitrate inactive MSDC: Manual System Diagnosis Clock Rather than using the SDC divider described in Section “Message Data (string pointed by: Message Pointer Register + 1)”, page 44, the user can use the manual SDC command to generate a SDC pulse for the diagnosis system. This MSDC pulse should be high at least 2 timeslot clocks. Line Status Register (0x04) 7 X 6 SPG 5 IDG 4 Sc 3 Sb 2 Sa 1 TXG 0 RXG • • • Read only register Default value after reset: 0bx01xxx00. This register reports the operation mode of the TSS463AA in the Sleep an Idle bits (Command Register located at address 0×03) as well as the diagnosis system status bits Sa to Sc discussed in the section “Diagnosis System” on page 22. SPG: Sleeping IDG: Idling Default mode at reset Sa, Sb and Sc: Diagnosis System Status Bits • Sa and Sb Diagnosis System Status Bits Sb 0 0 1 1 Sa 0 1 0 1 Communication Indication Nominal mode, differential communication Degraded over DATA, fault on DATA Degraded over DATA, fault on DATA Major error, fault on DATA and DATA 31 4205B–AUTO–12/04 • Sc: As soon as one of the three inputs (RxD2, RxD1, RxD0) differs from the others in the input comparison analysis performed by the diagnosis system, Sc is set. The only ways to reset this status bits through the RI signal or a general reset. TXG: Transmitting If this status bit is active, it indicates that the TSS463AA has chosen an identifier to transmit, and it will continue to make transmission attempt for this message until it succeeds or the retry count is exceeded. RXG: Receiving The receiving indicates that there is activity on the bus. Note : For safe modification of active channel registers both bits should be inactive (except “abort” command). Transmission Status Register (0x05) 7 NRT3 6 NRT2 5 NRT1 4 NRT0 3 IDT3 2 IDT2 1 IDT1 0 IDT0 • • • Read only register. Default value after reset: 0x00. The transmission Status register contains the number of retries made up-to-date, according tothe table above, and the channel currently in transmission. NRT [3:0]: IDT [3:0]: Last Message Status Register (0x06) Number of retries done in transmission. Channel number currently in transmission. 7 NRTR3 6 NRTR2 5 NRTR1 4 NRTR0 3 IDTR3 2 IDTR2 1 IDTR1 0 IDTR0 • • • Read only register. Default value after reset: 0x00. This register is basically the same as the transmission status register. It contains the last identifier number that was successfully transmitted, received or exceeded its retry count. If it was a successful transmission, the number of retries performed can be seen in this register as well. NRTR [3:0]: Number of retries done successfully in transmission. In case of reception NRTR[3:0] is undefined. Channel number that was successfully transmitted, received or exceeded its retry count. IDTR [3:0]: 32 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Last Error Status Register (0x07) 7 X 6 BOC 5 BOV 4 X 3 FCSE 2 ACKE 1 CV 0 FV • • • Read only register. Default value after reset: 0×00. The Last Error Status Register contains the error code for the last transmission or reception attempt. It is updated after each attempt, i.e., several error codes can be reported during one single transmission (with several retries). BOC: Buffer Occupied • • when one channel configured in “Reply request” mode has its “received” bit set when it attempts to transmit its request. BOC with the link capability between two channels sharing the same received buffer, is set when one channel has already set its “received” bit in its “Message length and status Channel register” and a receive is attempt on the other one. One: BOC active Zero: BOC inactive BOV: Buffer Overflow BOV indicates that the buffer length setup in the Channel Status Register was shorter than the number of bytes received plus 1, and thus, some data was lost. One: BOV active Zero: BOV inactive FCSE: Framing Check Sequence Error FCSE indicates a mismatch between the FCS received and the FCS calculated One: FCSE active Zero: FCSE inactive ACKE: Acknowledge Error ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463AA is a producer. One: ACKE active Zero: ACKE inactive 33 4205B–AUTO–12/04 Figure 23. ACKE Status bit RAK = 0 EOD field Expected DLC: Producer ACK field ACKE = 0 ACKE = 1 ACKE = 1 ACKE = 1 Received Received Received RAK* = 1 *RAK: Bit of the Frame COMMAND Field EOD field Expected Received Received Received ACK field ACKE = 0 ACKE = 1 ACKE = 1 ACKE = 1 CV: Code Violation CV indicates: • either a Manchester code violation (2 identical TS on Manchester bit), or a physical violation (transmitted bit “dominant”, received bit “recessive”), on fields ID, COM, DATA and CRC. or a physical violation or collision on field “preamble” and the “recessive” bit of the “Star Sync” field. • One: CV active Zero: CV inactive FV: Frame Violation FV indicates a physical violation or collision on ACK field of the frame when the TSS463AA is a consumer. One: FV active Zero: FV inactive 34 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 24. FV Status Bit DLC: Consumer EOD field Expected Received Received Received ACK field FV = 0 FV = 1 FV = 1 FV = 1 EOD field Expected Received Received Received ACK field FV = 0 FV = 1 FV = 1 FV = 1 Interrupt Status Register (0x09) 7 RST 6 X 5 X 4 TE 3 TOK 2 RE 1 ROK 0 RNOK • • Read only register. Default value after reset: 1xx0 0000 RST: Reset Interrupt RE indicates that the circuit has detected a valid reset command via the RESET pin or the reset command bit GRES. This interrupt cannot be disabled, since its enable bit is set when a reset is detected. One: Status flag activated Zero: No status flag. TE: Transmit Error Status Flag (or Exceeded Retry) This flag is set only when the Max number of transmission (1 + MR [3:0]) is reached with error of transmission. One: Status flag activated Zero: No status flag. Figure 25. Exceeded Retry with MR[3..0] = 3 1st TX 2nd TX 3rd TX set TE set CHER set CHTx 35 4205B–AUTO–12/04 TOK: Transmit OK Status Flag One: Status flag activated Zero: No status flag. RE: Receive Error Status Flag One: Status flag activated Zero: No status flag. ROK: Receive “with RAK (RAK=1)” OK Status Flag One: Status flag activated Zero: No status flag. RNOK: Receive “with no RAK (RAK=0)” OK Status Flag Interrupt Enable Register (0x0A) One: Status flag activated Zero: No status flag. 7 1 6 X 5 X 4 TEE 3 TOKE 2 REE 1 ROKE 0 RNOKE • • Read/write register. Default value reset: 1xx0 0000 On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as is the general rule. Note: TEE: Transmit Error Enable One: IT enabled. Zero: IT disabled. TOKE: Transmission OK Enable One: IT enabled. Zero: IT disabled. REE: Reception Error Enable One: IT enabled. Zero: IT disabled. ROKE: Reception “with RAK” OK Enable One: IT enabled. Zero: IT disabled. RNOKE: Reception “with no RAK” OK Enable One: IT enabled. Zero: IT disabled. Interrupt Reset Register (0x0B): 7 RSTR 6 0 5 0 4 TER 3 TOKR 2 RER 1 ROKR 0 RNOKR • • Write only register. Reserved bit: 5 and 6. This bit must not be set by user; a zero must always be written to this bit. 36 TSS463-AA 4205B–AUTO–12/04 TSS463-AA RSTR: Reset Interrupt Reset One: Status flag reset. Zero: Status flag unchanged. TER: Transmit Error Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. TOKR: Transmit OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. RER: Receive Error Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. ROKR: Receive “with RAK” OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. RNOKR: Receive “with no RAK” OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. Figure 26. Update of the Status Register RST Internal RESET TE TOK RE ROK RNOK Interrupt Status Register Flag Write Flag Write Flag Write INT Flag Write Flag Write Pin 3 TEE RSTR TER TOKE TOKR REE RER ROKE ROKR RNOKE Interrupt Enable Register RNOKR Interrupt Reset Register EOD SOF BUS 4 TS Set TXG ID+COM+DATA+CRC 1 to 2 TS Set RXG ACK 6 TS Reset RXG, TXG 4 TS Line Status Register (0x04) INT Write “IT Status Register” Write “Last error Register” Write “Last message Register” Write “Message Status” Write “Message Length and Status Register” 37 4205B–AUTO–12/04 Channel Registers There is a total of 14 channel register sets, each occupying 8 bytes for addressing simplicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the identifier tag, identifier mask and command fields plus two 1 x 8-bit registers for DMA pointers and message status. The base_address of each set is: (0x10 + [0x08 * channel_number]). When the TSS463AA is reset either via the external RESET pin or the general reset command, the channel registers are not affected. That is, on power-up of the circuit, all the channel registers start with random values. Due to this fact, the user should take care to initialize all the channel registers before exiting from idle mode. The easiest way to disable a channel register is to set the received and transmitted bits to 1 in the Message Length and Status Register. Table 8. Channel Register Sets Map Channel Number 6 5 4 3 2 1 0 from 0x40 0x38 0x30 0x28 0x20 0x18 0x10 to 0x47 0x3F 0x37 0x2F 0x27 0x1F 0x17 Channel Number 13 12 11 10 9 8 7 from 0x78 0x70 0x68 0x60 0x58 0x50 0x48 to 0x7F 0x77 0x6F 0x67 0x5F 0x57 0x4F Table 9. Channel Register Set Structure Reg. Name ID_MASK ID_MASK (No register) (No register) MESS_L/ STA MESS_PTR ID_TAG/ CMD ID_TAG Offset 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 DRACK ID_T [3: 0] x x x x x x M_L [4:0] M_P [6:0] EXT ID_T [11:4] RAK RNW RTR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 x ID_M [11:4] x x x x x x CHER x x CHTx x x CHRx Bit 2 x Bit 1 x bit 0 x ID_M [3:0] 38 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Identifier Tag and Command Registers The identifier tag and command registers are located at the base_address and base_address + 1. It allows the user to specify the full 12-bit identifier field of the ISO standard and the 4-bit command. 7 ID_T 3 6 ID_T 2 5 ID_T 1 4 ID_T 0 3 EXT 2 RAK 1 RNW 0 RTR base_address + 0x01 7 ID_T 11 6 ID_T 10 5 ID_T 9 4 ID_T 8 3 ID_T 7 2 ID_T 6 1 ID_T 5 0 ID_T 4 base_address + 0x00 • Read/Write registers. ID_T [11:0]: Identifier Tag Upon a reception hit (i.e, a good comparison between the identifier received and an identifier specified, taking the comparison mask into account, as well as a status and command indicating a message to be received), the identifier tag bits value will be rewritten with the identifier bits actually received. (See Section “Message Types”, page 45). No comparison will be done on the command bits, except on EXT bit. The RAK, RNW and RTR bits will be written into the first byte of the Message upon a reception hit. The RNW and RTR bits, as well as the status bits in the length and status register, must be in a valid position for reception or transmission. If not, the message corresponding to this identifier is considered as inactive or invalid. The way of knowing if an acknowledge sequence was requested or not is to check the first byte of the Message. EXT, RAK, RNW and RTR Message Pointer Register The message pointer register at address (base_address + 0x02) is 8 bits wide. It indicates where in the Message DATA RAM area the message buffer is located. 7 DRAK 6 M_P 6 5 M_P 5 4 M_P 4 3 M_P 3 2 M_P 2 1 M_P 1 0 M_P 0 base_address + 0x02 • DRAK: Disable RAK (Used in ‘Spy Mode’) Read/Write register. In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be set. If the message was successfully received, an IT is set (ROK or RNOK). In transmission: no action. One: disable active, “spy mode”. Zero: disable inactive, normal operation. M_P [6:0]: Message Pointer Since the Message DATA RAM area base address is 0x80, the value in this register is the offset from that address. If the message buffer length value is illegal (i.e. zero), this register is redefined as being a link pointer, thus containing the channel number of the channel that contains the actual message pointer, message length and received status. However, the identifier, mask, error and transmitted status used will be that of the originally matched channel. In any case, if a link is intended, the three high bits of M_P [6:0] should be set to 0. 39 4205B–AUTO–12/04 This allows several channels to use the same actual reception buffer in Message DATA RAM, thus diminishing the memory usage. Note: Only 1 level of link is supported. Message Length And Status Register The message length and status register at address (base_address + 0x03) is also 8 bits wide. It indicates the length of reserved for the message in the Message DATA RAM area. 7 M_L 4 6 M_L 3 5 M_L 2 4 M_L 1 3 M_L 0 2 CHER 1 CHTx 0 CHRx base_address + 0x03 • Read/Write register. M_L [4:0]: Message Length The 5 high bits of this register allows the user to specify either the length of the message to be transmitted, or the maximum length of a message receivable in the pointed reception buffer. Note: The first byte in this register does not contain data, but the length of the message received. This implies that the length value has to be equal to or greater than the maximum length of a message to be received in this buffer (or the length of a message to be transmitted) plus 1, thus allowing a maximum length of 30 bytes and a minimum length of 0 byte. If the value of this field is “illegal” (i.e 0x00) then this message pointer is defined as being a link (see Message pointer and register and “Linked Channels” on page 53). M_L [4:0] = 0x00 M_L [4:0] = 0x01 M_L [4:0] = 0x02 ------M_L [4:0] = 0x1D M_L [4:0] = 0x1E M_L [4:0] = 0x1F Note: Linked channel Frame with no DATA field (*) Frame with 1 DATA byte ---------------------Frame with 28 DATA bytes Frame with 29 DATA bytes Frame with 30 DATA bytes Different of a reply request frame with no in-frame reply (deferred reply). CHER: Channel Error Status and Abort Command As status, this bit is set by the TSS463AA when error occurs in transmission or on a received frame. The user must reset it. To abort the transmission defined in the channel, this bit can be set to 1 by the user (see Section “Activate, Idle and Sleep Modes”, page 52 and “Abort” on page 50). CHTx: Channel Transmitted and Transmit Enable Command CHRx: Channel Received and Receive Enable Command The 2 low order bits of this register contain the message status. Together with the RNW and RTR bits of the command register (base_address + 0x01), they define the message type of this channel (see section “Message Types” on page 45). As a general rule, the status bits are only set by the TSS463AA, so the user must reset them to perform a 40 TSS463-AA 4205B–AUTO–12/04 TSS463-AA transmission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded. Identifier Mask Registers The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison between the identifier received and the identifier specified. 7 ID_M 3 6 ID_M 2 5 ID_M 1 4 ID_M 0 3 x 2 x 1 x 0 x base_address + 0x07 7 ID_M 11 6 ID_M 10 5 ID_M 9 4 ID_M 8 3 ID_M 7 2 ID_M 6 1 ID_M 5 0 ID_M 4 base_address + 0x06 • Read/Write registers. ID_M [11:0]: Identifier Mask A value of 1 indicates comparison enabled. A value of 0 indicates comparison disabled. Example: – – ID_M[11:0] = 0x0FF8 Acceptance: ID’s from 0x0FF8 up to 0x0FFF 41 4205B–AUTO–12/04 Mailbox The mailbox contains all the messages received or to be transmitted. Each messages is link to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to 0xFF (see Section “Mapping”, page 26 ). The message (or message buffer) is composed of: • • 1 byte of message status (only used in receiving), n bytes of data. These data are the bytes of the DATA field of the frame with the same organization. The message is pointed by the Message Pointer Register of the channel, the length of the message is given by the Message Length and Status Register of the channel. This area is a pure RAM, it contains a random value after reset. Figure 27. Message Buffer Structure for Reception Message Length and Status Register M_L [4..0] CHER CHTx CHRx Message Pointer Register DRAK M_P [6..0] ( M_L >= n + 2 ) Message Received DATA n M_P + 0x80 + n + 2 Received DATA 0 RAK RNW RTR M_L [4..0] = n+1 received received received received M_P + 0x80 EXT RAK RNW RTR EOD SOF ID [11..0] DATA 0 DATA n FCS ACK EOF Received DATA Frame, immediate or deffered reply 42 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 28. Message Buffer Structure for Transmission Message Length & Status Register M_L [4..0] CHER CHTx CHRx Message Pointer Register DRAK M_P [6..0] ( M_L >= n + 2 ) Message Transmitted DATA n M_P + 0x80 + n + 2 Transmitted DATA 0 M_P + 0x80 (Nothing) RNW RTR EOD SOF ID [11..0] EXT RAK DATA 0 DATA n FCS ACK 2 EOF Transmitted DATA Frame Message Status (Pointed by: Message Pointer Register) 7 RRAK 6 RRNW 5 RRTR 4 RM_L4 3 RM_L3 1 RM_L1 0 RM_L0 RM_L2 • (no significant value in case of message to be transmitted) RRAK: Received RAK Bit This bit is the RAK bit coming from the COM field of the received frame. RRNW: Received RNW Bit This bit is the RNW bit coming from the COM field of the received frame. RRTR: Received RTR Bit This bit is the RTR bit coming from the COM field of the received frame. RM_L[4:0]: Message Length of the Received Frame If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1, even if the reserved length (Message Length and Status Register) is larger. 43 4205B–AUTO–12/04 Figure 29. Message Status Updating Frame Type Node x I, P Data Frame Communication Node A C RAK RNW RTR length Message Status on Node A after IT(*) Immediate Reply I, C P RAK RNW RTR previous value Deferred Reply I, C P RAK RNW RTR previous value C Data Frame I, P previous values Immediate Reply P I, C RAK RNW RTR length Deferred Reply P I, C RAK RNW RTR length P: Producer I: Initiator C: Consumer (*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous. Message Data (string pointed by: Message Pointer Register + 1) 7 6 5 4 DATAn --------DATA0 ------ - --3 2 1 0 DATA0 is the first received (or transmitted) byte, DATAn is the last one. Note: 1. If the length reserved (in the message length and status register) for an incoming frame is 2 bytes greater or more, the TSS463AA will write the 2 bytes of the CRC field in the message string just after DATAn. Because the VAN frame does not content a message length, the only way for the component to know the length of the DATA field is either the message length register value, either the EOD field detection. When the reserved length is too large, at the moment when it detects the EOD, the TSS463AA has already written the 2 bytes of the CRC field, considering these bytes as normal DATA. 2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80. 44 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Message Types There are 5 basic message types defined in the TSS463AA. Two of them (transmit and receive message types) correspond to the normal frame, and the rest correspond to the different versions of reply frames. Transmit Message RNW Initial setup After transmission 0 0 RTR 0 0 CHTx 0 1 CHRx Don’t care Unchanged To transmit a normal data frame on the VAN bus, the user must program an identifier as a Transmit Message. The TSS463AA will then transmit this message on the bus until it has succeeded or the retry count is exceeded. Receive Message RNW Initial setup After transmission 0 0 RTR 1 1 CHTx Don’t care Unchanged CHRx 0 1 The opposite of the transmit message type is the Receive Message type. This message type will not generate any frames on the bus. Instead it will listen to the bus until a frame passes that matches its identifier, with the mask taken into account, and then receive the data in that frame. The data received will be stored in the message buffer and the length of the message received is stored in the first byte of the message buffer. The actual identifier received is stored in the identifier register itself. This identifier may differ from the identifier specified in the register due to the effect of the mask register. Normally this should not interfere with the next identifier comparison since the bits that may differ are masked via the mask register. Reply Request Message RNW Initial setup After transmission (Waiting for reply) After reception (of reply) 1 1 RTR 1 1 CHTx 0 1 CHRx 0 0 1 1 1 1 The Reply Request Message type is a demand to transmit on the VAN bus a reply request. When this message type is programmed, three things can happen. In the first case no other modules on the bus responded with an in-frame reply, and in this case the TSS463AA will set the message type to the after transmission state. When this message type is programmed, the TSS463AA will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. 45 4205B–AUTO–12/04 The second case is that another module on the bus replies with an in-frame reply. In this case the message type will pass immediately into the after reception state, without passing the after transmission state. Reply Request Message without transmission RNW Initial setup After reception 1 1 RTR 1 1 CHTx Don’t care Unchanged CHRx 0 1 In the third case the TSS463AA has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warning! This should be avoided as it may result in an illegal message type (Illegal reply Request). Immediate Reply Message RNW Initial setup After transmission 1 1 RTR 0 0 CHTx 0 1 CHRx 0 1 The immediate Reply Message will attempt to transmit an in-frame reply, using the data in the message buffer. Deferred Reply Message RNW Initial setup After reception (of reply request) 1 1 RTR 0 0 CHTx 0 1 CHRx 1 1 Above a Deferred Reply Message is shown. This message type will immediately transmit a deferred reply frame. Reply Request Detection Message RNW Initial setup After reception 1 1 RTR 0 0 CHTx 1 1 CHRx 0 1 Finally there is the Reply Request Detector Message type. Its purpose is to receive a reply request frame and notify the processor, without transmitting an in-frame reply. Inactive Message RNW Recommended After transmission After reception Illegal reply request Don’t care 0 0 1 RTR Don’t care 0 1 1 CHTx 1 1 Don’t care 0 CHRx 1 Don’t care 1 1 The table above shows all inactive messages types. The last combination will transmit a reply request, but will not receive the reply since its buffer is tagged as occupied. 46 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Priority Among the Different Channels The priority handling on the VAN bus itself is already explained in the Line interface section. The priorities for the messages in the TSS463AA is however slightly different. For instance, it’s possible that an identifier matches two or more of the identifiers programmed into the registers. In this case, it is the lowest identifier number that has priority. i.e., if both identifier 5 and 10 match the identifier received, it is the identifier 5 that will receive the message. However, since the identifier 5 will become an inactive message when it has received the frame, the next time the same identifier is seen on the bus, the corresponding data will be received by identifier 10. The same is valid for messages to be transmitted, i.e. if two or more messages are ready to be transmitted, it is the one with the lowest identifier number that will get priority. Retries, Rearbitrate and Abort Retries and rearbitrate commands are located, respectively, in the Transmit Control Register and in the Command Register. An abort command is located in each channel register set, in the Message Length and Status Register (base_address + 0x03). These three commands are available only when the TSS463AA is a producer. Figure 30. Transmit Function Activate Ch. Enabled in Xmit Mode ? Yes Disable of Current Ch. Select the Lowest Ch. Number and Load ”Max - Retries” No Yes Abort Activated on Current Ch. ? No Wait for Bus Free (EOF+IFS= 12 Timeslots) Decrement Retry Counter Transmit Frame and Wait for the End Abort Abort Required on Current Ch. Rearbitrate? no Yes Retry Needed ? No Rearbitrate 47 4205B–AUTO–12/04 Retries The purpose of the retries feature is to provide, for the user, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal DATA frame or on REPLY REQUEST frame. The maximum number of retries is programmable through MR[3:0] of the Transmit Control Register (0x01). When a channel is enable – bit CHTx = 0 of Message Length and Status Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will count-down to 0, an IT TE is set in the Interrupt Status Register (0x09), and the transmission is stopped. MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see Table 5, “Retries,” on page 28). The number of retries performed, as well as the current channel number associated, can be read in the Transmission Status Register (0x05). The Last Error Status Register (0x07) informs about the trouble uncounted: • Failure cases: – – – • Code viol (CV error bit) Acknowledge error (ACKE error bit) CRC error (FCSE error bit) It should be noticed that contention is considered as normal CSMA/CD protocol and, therefore, is not taken into account in failure cases. So, an 'infinite' number of attempts can be performed if bus contention occurs continuously. There is only one retry counter for all channels. When the user writes the Max_Retries value, all channels start their transmission with this parameter. Rearbitrate The purpose of rearbitrate feature is to postpone a channel already in transmission in order to authorize an higher priority (see Section "Priority Among the Different Channels", page 47) message to be transmit. • • • • Max_retries = 1 (2 transmissions attempts). If Ch8 is in a the retry loop and the user wants to transmit the Ch5 without waiting the end of the loop, the user can use the rearbitrate command. The TSS463AA will then wait until the end of the current transmission, reload the retries counter and enable the Ch5 to transmit. At the end of this transmission Ch5, either when the attempt is successful or the exceeded retry count is reached, the retries counter is reloaded and the transmission is activated for the Ch8 again. Typical Example 48 TSS463-AA 4205B–AUTO–12/04 4205B–AUTO–12/04 First attempt Xmit Ch8 (Load Max-retries) (Load Max-retries) Rearbitrate (Activate Ch5) First attempt Xmit Ch8 Rearbitrate (Activate Ch5) Ex: FCS Error * (not seen by application) Delay Ex: FCS Error * (not seen by application) Viol Delay Viol Figure 31. Rearbritrate Example Figure 32. Idle and Rearbitrate Example Xmit Ch5 Xmit Ch5 (Load Max-retries) (Load Max-retries) Idle command * (not seen by application means no IT generation) Second attempt Xmit Ch8 * (not seen by application means no IT generation) Set CHTx/Ch5 & ITROK EOF+IFS Set CHTx/Ch5 & ITROK EOF+IFS First attempt Xmit Ch8 (Load Max-retries) First attempt Xmit Ch8 (Load Max-retries) (Retries - 1) (not seen by application) Delay Viol Ex: FCS Error (Retries - 1) Second attempt Xmit Ch8 (not seen by application) Delay Ex: FCS Error Viol Set CHER & CHTx /Ch8, and set IT TE Ex: set FSCE status bit Set CHER & CHTx /Ch8, and set IT TE Ex: set FSCE status bit Delay Delay Viol Viol stand-by Idle EOF+IFS: 8 + 4 Timeslots Delay Viol: 12 T imeslots EOF+IFS: 8 + 4 T imeslots Delay Viol: 12 T imeslots TSS463-AA If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at the end of all the transmit attempts (for more information about idle command, see “Activate, Idle and Sleep Modes” on page 52.). 49 Figure 33. Disable Channel After Rearbitrate (Load Max-retries) (Load Max-retries) Disable Ch8(1) (not seen by application) Ex: FCS Error (Activate Ch5) Rearbitrate (not seen by application) Delay Viol Ex: ACK Error Set CHER & CHTx /Ch5, and set IT TE Ex: setACKE status bit Delay Viol stand-by (Retries - 1) KO Delay Viol Second attempt Xmit Ch5 Set CHTx/Ch5 & ITTOK First attempt Xmit Ch8 First attempt Xmit Ch5 OK EOF+IFS stand-by EOF+IFS: 8 + 4 T imeslots Delay Viol: 12 T imeslots (1) The disable is applied setting the CHTx/Ch8 bit to 1. In this case, the TSS463AA completes the current attempt (Ch8) and let the transmission go on the new channel (Ch5 if validated), otherwise it stops all attempts on the current channel. Abort An abort command is dedicated to channels already enabled in transmission or in inframe response. For example, this command can be used to break the retry procedure on one channel. Abort channel is done by setting the Error bit (CHER) in the Message Length and Status Register (base_address + 0x02). This command is taken into account if the channel aborted is not transmitted. When this abort command is really done, the TSS463AA set to 1 the Transmitted bit (CHTx) of the Message Length and Status Register. The abort mechanism is integrated into the transmit function. This mainly means, abort, priority and retries live together in the transmit function. 50 TSS463-AA 4205B–AUTO–12/04 4205B–AUTO–12/04 Figure 34. Abort Example Reset Ch s Initialization Activate Abort Ch0 (before Xmit) Set CHTx/Ch0 Abort Ch13 (before Xmit) Abort Ch4 (during Xmit) 12 Timeslots Xmit Ch4 Xmit Ch6 Set CHTx/Ch4 &ITROK Xmit Ch6 if Previously Failed Set CHTx/Ch6 & ITROK if Successful Xmit Ch6 if Previously Failed Set CHTx/Ch6 & ITROK if Successful TSS463-AA /Ch6 & IT ROK SetorCHTx CHER or IT RE Set CHTx/Ch13 51 Activate, Idle and Sleep Modes Idle and Activate Commands Sleep, idle and activate commands are located in the Command Register (0x03). These three commands are general commands for the TSS463AA. After reset, the TSS463AA starts in idle mode. In this mode, the oscillator operates (CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus. The TxD output (pin 12) is in tri-state mode, a pull-up resistor must be provided externally or by the line driver to avoid floating state on the VAN bus. To activate the TSS463AA, the user must set the activate bit (ACTI) and reset the idle bit (IDLE). Figure 35. Idle and Activate Timings Idle Mode Activate Mode SOF RxD After Reset TxD 3 TS (max) Activate command SOF 8 TS 12 TS TS: Timeslot Period Activate Mode EOD Idle Mode FCS RxD Idle Command INT 4 TS 5 TS In both cases, the idle state can be verified reading the Line Status register (0x04). Sleep Command If the user sets the sleep bit (SLEEP), the TSS463AA enters in sleep mode, regardless of the values of activate and idle bits. It means that, all non-user registers are set-up to reduce the power consumption and the internal oscillator is immediately stopped. Then, accesses to all registers (and to the messages) via the SPI/SCI interface are impossible and CKOUT is not provided. To exit from this mode the user must apply either an hardware reset (external reset pin) either an asynchronous software reset (via the SPI/SCI interface). In a typical application (see F igure 5 ), using the CKOUT feature (pin 8), if the TSS463AA is put in sleep mode, the clock provided to the microcontroller is stopped. So, the system does not run and the only way to awake this application is an external reset. 52 TSS463-AA 4205B–AUTO–12/04 ACK TSS463-AA Linked Channels The linkage feature allows two channels to share the same Message area, the message pointer and the message length assumes this property: • • • Zero value as message length (M_L [4:0] - base_address + 0x03) declares the channel linked to another channel. The number of this other channel is defined in the message pointer field (M_P [6:0] - base_address + 0x02). The pointer and the length values for the Message area are defined only once, in the register set of this other Channel. Only one level of linkage can be created. This means, (see Figure 36) a Channel k can be linked to the Channel i but not to Channel j, already defined as linked to Channel i. All the others can be different between the two channels, for example the ID_Tag. Figure 36. Linkage Mechanism The Channel j linked .... Channel i and j share the same Message area to the Channel i ID_Mask j (lsb) --- Channel j --- ID_Mask j (msb) --- Message for Channels i & j --- 0x00 DRAK ID_Tag j (lsb) CHER CHTx CHRx DATA n i EXT RAK RNW RTR ID_Tag j (msb) ID_Mask i (lsb) --- Channel i --- ID_Mask i (msb) Mess_Len = n+2 DRAK ID_Tag i (lsb) CHER CHTx CHRx Mess_Ptr EXT RAK RNW RTR ID_Tag i (msb) Length = n+2 DATA 0 Message Status This Message area sharing permits either to optimize the allocation of the 128 bytes of DATA, or to perform some special communications between the different nodes of the network. 53 4205B–AUTO–12/04 Electrical Characteristics Absolute Maximum Ratings Ambient temperature under bias: Automotive........................................................-40°C to 125°C Storage Temperature ........................................-65°C to 150°C Voltage on VCC to VSS .......................................... -0.5 to +7.0V Voltage on any pin to VSS ..........................-0.5V to VCC +0.5V *NOTICE: Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions exceeding those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Characteristics Table 10. TA = -40°C to 125°C; VCC = 5V + 10%; VSS = 0V Symbol VIL VIH VHY VOL VOH IL Parameter Input Low Voltage Input High Voltage Hyteresis voltage of trigger CMOS inputs Output Low Voltage Output High Voltage Input Leakage Current (SCLK, MOSI, SS) Output Tristate Leakage Current (MISO) RPU, RPD CIO ICCSB Input pull-up and pulldown resistors I/O Buffer Capacitance Power Supply Current Sleep mode Power Supply Current Idle or Active mode 70 10 50 kΩ pF µA Note 4 Not tested (Note 1) 2.4 5 Min. -0.5 0.7·VCC max 0.4 Max 0.3·VCC·min VCC+0.5 0.4 Unit V V V V V µA see Table IOL = 3.2 mA, Vcc min IOH = -3.2 mA, Vcc min 0 < VIN < VCC Test Conditions IOZ 5 µA 0 < VIN < VCC ICCOP 9 mA (Notes 2, 3) Notes: 1. 2. 3. 4. Sleep Mode ICCSB is measured according to a VSS Clock Signal. Active mode ICCOP is measured at: XTAL = 8 MHz clock, VAN speed rate = 125 KTS/s. ICC is a function of the Clock Frequency. Figure 38 displays a graph showing ICC versus Clock frequency. RESET, RxD0, RxD1, RxD2 inputs. 54 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 37. ICC Figure 38. ICCOP versus Clock Frequency at 125 KTimeslot/s mA 9 8.5 8 7.5 MHz 2 4 6 8 55 4205B–AUTO–12/04 AC Characteristics TA = -40°C to 125°C; VCC = 5V + 10%; VSS = 0V Table 11. Microprocessor Interface CLOAD = 200pF on SPI/SCI Lines Symbol fOP Characteristic Operating Frequency SPI SCI Cycle Time SCI Enable Lead Time Enable Lead Time Clock (SCLK) High Time Clock (SCLK) Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (Time to Data Active from High-Impedance State) Slave Disable Time (Hold Time to HighImpedance State) Data Valid (after Enable Edge) Data Hold Time (Outputs after Enable Edge) INT Float Pulse Width SPI Min dc dc 250 8 4 12 100 100 40 40 0 Max 4 125 100 Unit MHz kHZ ns ms XTAL Period XTAL Period ns ns ns ns ns tCYC tLEAD tLAG tW(SCKH) tW(SCKL) tSU tH tA tDIS tV tHO tIZIL (1) 0 20 200 60 - ns ns ns ns Note: 1. Simulated Data SS (INPUT) t CYC t LEAD FLAG t W(SCKL) t W(SCKH) SCLK (INPUT) t MISO (OUTPUT) A t DIS t SU tH tV tHO MOSI (INPUT) t IZIL t IZIL INT float pulse only when address is 0x08 to 0x0B 56 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Interface Oscillator Characteristics Figure 39. C2 versus Frequency pF 200 100 33 1 Note: 2 4 8 MHz C1 (no capacitance needed) see Figure 5. External Clock Drive Characteristics (XTAL1) Symbol tCHCH tCHCX tCLCX tCLCH tCHCL Parameter Oscillator period High Time Low Time Rise Time Fall Time Min 120 20 20 Max Unit ns ns ns 20 20 ns ns t CHCL t CLCH V IH V IL V IL V IH XTAL1 V IH t CHCX t CHCH t CLCX 57 4205B–AUTO–12/04 Packaging Information SO16 SO A A1 B C D E e H h L N a 2.35 0.10 0.35 0.23 10.10 7.40 1.27 10.00 0.25 0.40 MM 2.65 0.30 0.49 0.32 10.50 7.60 BSC 10.65 0.75 1.27 16 0° 8° 0.093 0.004 0.014 0.009 0.398 0.291 0.050 0.394 0.010 0.016 Inch 0.104 0.012 0.019 0.013 0.413 0.299 BSC 0.419 0.029 0.050 16 0° 8° 58 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Ordering Information Part Number TSS463-AA TSS463-AA: R TSS463A-TERZ(1) Supply Voltage 5V +10% 5V +10% 5V +10% Temperature Range -40°C to +125°C -40°C to +125°C -40°C - +125°C Package SO16 SO16 SO16 Packing Stick Tape and Reel Tape and Reel Note: 1. These products are available in ROHS version. 59 4205B–AUTO–12/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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