U3770M

U3770M CT2 I/Q Modulator and Clock Circuitry Description The U3770M is a quadrature modulator realized using Atmel Wireless & Microcontrollers’ advanced 0.8 micron CMOS process. The IC is especially designed for CT2 applications in conjunction with Atmel Wireless & Microcontrollers’ RF/IF signal processor U2760B and a CT2 baseband controller (i.e., AMD PhoXTM controller Am79C4xx). Together with Atmel Wireless & Microcontrollers’ PLL IC U2783B and the GaAs front end U7001BG, a complete CT2 chip set is available. Electrostatic sensitive device. Observe precautions for handling. Features D Programmable 0.8/1.6-MHz quadrature-modulated carrier generation D More than 26 dB LO and sideband suppression D 18.432 MHz CMOS level clock generation D Supply-voltage range 2.7 V to 3.3 V D Low power consumption, typically 12 mW D SO16 package or die form Block Diagram RRef in 12.8 MHz 2 DIV / 25 Phase 512 kHz comparator LF 11 VCO 14 CLK out 95 9881 Amp. 3 4 13 12 10 6 5 8 7 1, 15, 16 DNC DIV / 2 or DIV / 4 6.4 MHz 3.2 MHz 512 kHz DIV / 36 18.432 MHz VDD DGND AGND PROG TST Qin QBin Iin IBin Dual DFF 9 MOD out Figure 1. Block diagram Ordering Information Extended Type Number U3770M-MFP U3770M-MFPG3 Package SO16 SO16 Tube Taped and reeled Remarks Rev. A3, 07-Sep-00 1 (6) U3770M Functional Description The U3770M has been designed to reduce power consumption and cost of CT2 devices. An innovative CMOS I/Q modulator with extremely low current provides all the advantages of I/Q modulation: – No requirement for FM deviation tuning – Eliminates the Gaussian filter – Simplifies the power ramping control The modulated output carrier can be programmed to be 0.8 MHz or 1.6 MHz by the PROG control pin. The typical supply voltage is 3 V @ 4 mA. To reduce overall system cost, an internal PLL generates an 18.432-MHz clock signal from the system’s 12.8-MHz reference oscillator. This way, only one crystal oscillator is needed in the complete CT2 device. Internally, the 12.8-MHz reference signal is fed into a shaping amplifier and then into two logic dividers, to generate a 512-kHz and a programmable 3.2-MHz or 6.4-MHz clock. This clock is divided by 4 by two D flipflops. The flip-flop outputs drive the four analog switches in quadrature. The local oscillator (LO) supression mixer consists of a pair of analog switches. make a local oscillator (LO) suppression mixer. By summing the other pair outputs the suppression (both LO and side tone) is