APQO14_1

Oscillator THT, programmable Features: - Standard DIL14 package - Low cost to performance - 3.0 ~ 5.5 volt available - Tolerance and stability to ± 25ppm - Ultra low jitter 40 ~ 133 MHz Max capacitive load on outputs for CMOS levels 4.5 V ~ 5.5 V Vdd £ 6 6 MHz 4.5 V ~ 5.5 V Vdd > 66 ~ 133 MHz 3.0 V ~ 3.6 V Vdd £ 4 0 MHz 3.0 V ~ 3.6 V Vdd > 40 ~ 100 MHz Min 3.0 Max 5.5 50 25 50 25 30 15 Unit V pF pF pF pF pF pF C CMOS Drawing APQO 14 Dimensions in mm Order key O Part O=Oscillator - 50.000000M Frequency M=MHz - APQO 14 Type/Package APQO=programmable QO 14=DIL 14 - 50 Tolerance ±ppm - 5.0 Voltage 5.0=5.0Volt 3.3=3.3Volt -A Temperature A= 0°C ~ +70°C /T Option T = Tristate P = Power down / Packaging blank = Tube B= -10°C ~ +60°C C= -10°C ~ +70°C D= -20°C ~ +70°C E= -40°C ~ +85°C auris-GmbH office@auris-gmbh.de www.auris-gmbh.de All specifications are subject to change without notice. 3.3 Oscillator THT, programmable APQO 14 Electrical characteristics Discription Input characteristics (Pin 1) VIL, Low-level input voltage TO Tri-state or power-down Test conditions 4.5 ~ 5.5 V Vdd 3.0 ~ 3.6 V Vdd 4.5 ~ 5.5 V Vdd 3.0 ~ 3.6 V Vdd VIN = 0V VIN = Vdd 4.5 V ~ 5.5 V Vdd, 16 mA IOL 3.0 V ~ 3.6 V Vdd, 8 mA IOL 4.5 V ~ 5.5 V Vdd, -16 mA IOL 4.5 ~ 5.5 Vdd, -16 mA IOL 3.0 V ~ 3.6 V Vdd, -8 mA IOL 4.5 ~ 5.5 Vdd, OUTPUT FREQ £ 133 MHz 3.0 ~ 3.6 Vdd, OUTPUT FREQ £ 100 MHz 4.5 ~ 5.5 Vdd, VIN = 0V 4.5 ~ 5.5 Vdd, VIN = 0.7 V 5.0 Vdd Output is tri-stated Output is tri-stated Min Typ Max 0.8 0.2 Vdd Unit V V V V µA µA V V V V V mA mA µA MÙ KÙ µA VIH, High-level input voltage TO Enable output or no connect 2.0 0.7 Vdd 10 5 0.4 0.4 2.4 Vdd - 0.4 Vdd - 0.4 45 25 50 8.0 200 IIL, Input low current IIH, Input high current Output characteristics VOL, Low-level output voltage VOHTTL, High-level output voltage TTL VOHCMOS High-level CMOS voltage Power supply current (unloaded) Standby current Input pull-up resistor (PIN 1) Tri-state leakage current Output enable mode Power down mode 1.1 50 10 3.0 100 20 Output clock switching characteristics Description Duty cycle TTL @ 1.4 V 4.5 ~ 5.5 Vdd Test conditions £ 50 MHz, CL = 50 pF 50 ~ 66 MHz, CL = 15 pF 66 ~ 125 MHz, CL = 25 pF 125 ~ 133 MHz, CL = 15 pF £ 66 MHz, CL £ 25 pF 66 ~ 125 MHz, CL £ 25 pF 125 ~ 133 MHz, CL £ 15 pF £ 40 MHz, CL £ 30 pF 40 ~ 100 MHz, CL £ 15 pF 0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, CL = 50 0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, CL = 25 0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, CL = 15 0.2 ~ 0.8 Vdd, 4.5 ~ 5.5 Vdd, CL = 50 0.2 ~ 0.8 Vdd, 3.0 ~ 3.6 Vdd, CL = 30 0.2 ~ 0.8 Vdd, 3.0 ~ 3.6 Vdd, CL = 15 From power on PWR_DWN pin LOW to output Hi-Z Min 45 45 40 40 45 40 40 45 40 Typ Max 55 55 60 60 55 60 60 55 60 1.8 1.2 0.9 3.4 4.0 2.4 2 Unit % % % % % % % % % ns ns ns ns ns ns ms ns ns ns ns ns ps ps ps Duty cycle: CMOS @ Vdd / 2 4.5 ~ 5.5 Vdd 3.0 ~ 3.6 Vdd Output clock rise / fall Start up time Power down delay time Synchronous Asynchronous Output disable time Synchronous Asynchronous Output enable time Period Jitter: Ó Peak to peak T/2 10 T/2 10 8 65 65 T+10 15 T+10 15 100 11 99 80 OE pin LOW to output Hi-Z T = Frequency oscillator period 1 - 133 MHz £ 33.000 MHz > 33.000 MHz auris-GmbH office@auris-gmbh.de www.auris-gmbh.de All specifications are subject to change without notice. 3.4