AS8F512K32_07

FLASH F LASH Austin Semiconductor, Inc. 512K x 32 FLASH PIN ASSIGNMENT FLASH MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS • • • • • • • • • • • • • • • • SMD 5962-94612 MIL-STD-883 Fast Access Times: 70, 90, 120 and 150ns Operation with single 5V (±10%) Theta JC= 1.00°C/w User configurable as 512Kx32, 1Mx16, or 2Mx8 Eight Equal Sectors of 64K Bytes for each 512Kx8 Compatible with JEDEC EEPROM command set Any Combination of Sectors can be Erased Supports Full Chip Erase Embedded Erase and Program Algorithms TTL Compatible Inputs and CMOS Outputs Built in decoupling caps for low noise operation Suspend Erase/Resume Function Individual Byte Read/ Write Control Minimum 1,000,000 Program/Erase Cycles per sector guaranteed AS8F512K32 (Top View) 68 Lead CQFP (Q & Q1) FEATURES 66 Lead PGA (P) OPTIONS • Timing 70ns 90ns 120ns 150ns Package Ceramic Quad Flat pack Ceramic Quad Flatpack Pin Grid Array MARKINGS -70 -90 -120 -150 Q Q1 P No. 702 No. 904 • GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8F512K32 is a 16 Megabit CMOS FLASH Memory Module organized as 512Kx32 bits. The AS8F512K32 achieves high speed access (70 to 150 ns), low power consumption and high reliability by employing advanced CMOS memory technology. An on-chip state machine controls the program and erase functions. The embedded byte-program and sector/chip erase functions are fully automatic. Data-protection of any sector combination is accomplished using a hardware sector-protection feature. The Erase/Resume function allows the sector erase operation to read data from, or program to a non-erasing sector, then resume the erase operation. Device operations are selected by using standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal state machine that interprets the commands, controls the erase and programming operations, outputs the status of the device, and outputs data stored in the device. On initial power-up operation, the device defaults to the read mode. AS8F512K32 Rev. 5.2 09/07 For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 FLASH F LASH Austin Semiconductor, Inc. OPERATIONS Read Mode A low-level logic signal is applied to CE\ and OE\ pins to read the output of the AS8F512K32. The CE\ is power control and is used for device selection. The delay from stable address to valid output data is the address access time (tAVQA). The delay from CE\ equals logic low and stable addresses to valid output data is the chip-enable access time (tELQV). The output-enable access time (tGLQV) is the delay from OE\ =low logic to valid output data, when CE\ =low logic and addresses are stable for at least tAVQAtGLQV. Standby Mode Icc supply current is reduced by applying a logic-high on the CE\ to enter the standby mode. In the standby mode, the outputs are placed in the high impedance state. If the device is deselected during erasure or programming, the device continues to draw active current until the operation is complete. Output Disable OE\= VIL or CE\=VIH, output from the device is disabled and the output pins (DQ0 - DQ7) are placed in the high-impedance state. Erasure and Programming Erasure and programming of the AS8F512K32 are accomplished by writing a sequence of commands using standard microprocessor write timings. The commands are written to a command register and input to the command state machine. The command state machine interprets the command entered and initiates program, erase, suspend, and resume operations as instructed. The command state machine acts as the interface between the write-state machine and external chip operations. The write-state machine controls all voltage generation, pulse generation, preconditioning and verification of the contents of the memory. Program and block/chip-erase functions are fully automatic. Once the end of a program or erase operation has been reached, the device internally resets to the read mode. If Vcc drops below the low-voltage-detect level (VLKO), any operation in progress is aborted and the device resets to the read mode. If a byte-program or chip-erase operation is in progress, additional program/erase operations are ignored until the operation completes. Command Definitions Operating modes are selected by writing particular address and data sequences into the command register Command Sequence Table . The device will reset to read mode if an incorrect address and data value or writing them in the incorrect AS8F512K32 Rev. 5.2 09/07 AS8F512K32 sequence transpires. The command register does not fill an addressable memory location. The register is used to store the command sequence, along with the address and data needed by the memory array. Commands are written by setting CE\=VIL and OE\= VIH and bring WE\ from logic-high to logic-low. Addresses are latched on the falling edge of WE\ and data is latched on the rising edge of WE\. Holding WE\ =VIL and toggling CE\ can be used as an alternative. Read/Reset Command The read/reset mode is activated by writing either of the two read/reset command register. The device remains in this mode until one of the other valid command sequences is input into the command register. Memory data can be read with standard microprocessor read-cycle timing in the read mode. On power up, the device defaults to the read/reset mode. A read/reset command sequence if not required and memory data is available. Algorithm-Selection Command The algorithm-selection command allows access to binary code that matches the device with the proper programming and erase-command operations. After writing the three bus cycle command sequence, the first byte of the algorithm-selection code (01) can be read from address XX00. The second byte of the code (A4) can be read from address XX01. This mode remains in effect until another valid command sequence is written to the device. Byte-Program Command Byte-programming is a four-bus-cycle-command sequence. The first three bus cycles put the device into the programsetup state. The fourth bus cycle loads the address location and the data to be programmed into the device. The addresses are latched on the falling edge of WE\ and the data is latched on the rising edge of WE\ in the fourth cycle. The raising edge of WE\ starts the byte-program operation. The embedded byte-programming function automatically provides needed voltage and timing to program and verify the cell margin. Any further commands written to the device during the program operation are ignored. Programming can be preformed at any address location in any order. When erased, all bits are in a logic state 1. Logic 0s are programmed into the device. Attempting to program logic 1 into a bit that has been previously programmed to logic 0 causes the internal pulse counter to exceed the pulse-count limit. This sets the exceed-timing-limit indicator (DQ5) to a logic high state. Only an erase operation can change bits from logic 0 to logic 1. The status of the device during the automatic programming operation can be monitored for the completion using the data-polling feature or the toggle-bit feature . See the “operation status” for the full description. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 FLASH F LASH Austin Semiconductor, Inc. Chip Erase Command Chip-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip erase command. This command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge of WE\ starts the chip erase operation. Any further commands written to the device during the chip erase operation is ignored. The embedded chip erase function automatically provides voltage and timings needed to program and verify all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically. The user is not required to program the memory cells prior to erase. The status of the device during the automatic chip erase operation can be monitored for completion using the data-polling feature. See the "operation status" section for a full description. Sector-Erase Command Sector erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the sector erase command and the sector address location to be erased. Any address location within the desired sector can be used. The addresses are latched on the falling edge of WE\ in the sixth bus cycle. After a delay of 100-ms from the rising edge of WE\, the sector erase operation begins in the selected source. Sectors can be selected to be erased concurrently during the sector-erase command sequence. For each additional sector selected for erase, another bus cycle is issued. The bus cycle loads the next sector-address location and the sectorerase command. The time between the end of the previous bus cycle and the start of the next bus cycle must be less than 100 ms-other wise, the new sector location is not loaded. A time delay of 100 ms from the raising edge of the last WE\ starts the sector erase operation. If there is a falling edge of WE\ within the 100 ms time delay, the timer is reset. One to eight sector address locations can be loaded in any order. The state of the delay timer can be monitored using the sector-erase-delay indicator (DQ3). If DQ3 is logic low, the time delay has not expired. See the “operation status” for the full description. Any commands other than erase-suspend (B0) or sector erase (30) written to the device during the sector erase operation causes the device to exit the sector erase mode. The contents of the sector(s) selected for erase is not valid. To complete the sector-erase operation, reissue the sector erase command. AS8F512K32 The embedded sector erase function automatically provides voltage and timings needed to program and verify all the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. The user is not required to program the memory cells prior to erase. The status of the device during the automatic sector erase operation can be monitored for completion using the data-polling feature or the toggle bit feature. See the "operation status" section for a full description. Erase-Suspend Command Sector-erase operations may be interrupted by the erasesuspend command (B0) , in order to read data from an unaltered sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-suspend command (B0) is latched on the rising edge of WE\. Once the sector-erase operation is in progress, the erase-suspend command request the internal write-state-machine to halt operation at predetermined break points. The erase-suspend command is valid only during the sector-erase operation and is valid only during the byte-programming and chip-erase operations. The sector-erase delay timer expires immediately if the erase-suspend command is issued while the delay is active. After erase-suspend is issued, the device takes between 0.1ms and 15 ms to suspend the operation. The toggle bit must be monitored to determine when the suspend has been executed. When the toggle bit stops toggling, data can be read from sectors that are not selected for erase. See the “operation status” section for a full definition. Reading from a sector marked for erase can result in invalid data. Once the sector-erase operation is suspended, further writes of the erase-suspend command are ignored. Any command other than erase-suspend (B0) or erase-resume (30H) written to the device during the erase-suspend mode causes the device to exit the suspend mode. To complete the sectorerase operation, reissue the sector-erase command sequence. Erase-Resume Command The erase-resume command (30H) restarts a suspended sector erase operation from where it was halted to completion. Erase-resume is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-resume command (30H) is latched on the rising edge of WE\. When an erase-suspend/ eraseresume command combination is written, the internal pulse counter (exceed timing limit) is reset. The erase-resume command is valid only in the erase-suspend state. After the eraseresume command is executed, the device returns to the valid sector-erase state and further writes of the erase-resume commands are ignored. After the device has resumed the sectorerase operation, another erase-resume command can be issued to the device. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS8F512K32 Rev. 5.2 09/07 3 FLASH F LASH Austin Semiconductor, Inc. Operation Status Flags1 Table Device Operations2 Byte-programming in progress Byte-programming exceed time limit Byte-programming complete Sector/chip erase in progress Sector/chip erase exceed time limit Sector/chip erase complete NOTES: 1. T= toggle, D=data, X=data undefined 2. DQ4, DQ2, DQ1, DQ0 are reserved for future use. Status Bit Definition During operation of the automatic embedded program and erase functions, the status of the device can be determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle-bit (DQ6) require multiple successive reads to observe a change in the state of the designated output. Operation Status Flags Table defines the values of the Flag status. Data-Polling DQ7 The data-polling status outputs the complement of the data latched into the DQ7 data register while the write-state machine is engaged in a program or erase operation. Data bit DQ7 changing from complement to true indicates the end of an operation. Data-polling is available only during the byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Datapolling is valid after the rising edge of ?W/E in the last bus cycle of the command sequence loaded into the command register. During a byte-program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the program data register. During the erase operations, reading DQ7 outputs a 0. Upon completion, reading DQ7 outputs a 1. Also, data polling must be performed at a new sector address that is within a sector being erased; otherwise the status is not valid. When using data-polling, the address should remain stable throughout the operation. During a data-polling read, while ?W/E is low, data bit DQ7 can change asynchronously. Depending on the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. A subsequent read of the device is valid. Data-Polling DQ6 The function of toggle-bit status, is to output data on DQ6 that toggles between 1 and 0 while the write-state machine is engaged in a program or erase operation. When toggleAS8F512K32 Rev. 5.2 09/07 AS8F512K32 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 T 0 X 0 X X X D\ T 1 X 0 X X X D\ D D D D D D D D 0 T 0 X 1 X X X 0 T 1 X 1 X X X 1 1 1 1 1 1 1 1 OPERATION STATUS bit DQ6 stops toggling after two consecutive reads to the same address, the operation is complete. The toggle-bit is only available during the byte-programming, chip-erase, and sectorerase timing delay. Toggle-bit data is valid after the raising edge of ?W/E in the last bus cycle of the command sequence loaded into the command register. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid. A subsequent read of the device is valid. Exceed Time Limit DQ5 The program and erase operations use an internal pulse counter to limit the number of pulses applied. If the pulse count limit is exceeded, DQ5 is set to a 1 data state. This indicates that the program or erase operation has failed. DQ7 will not change from complemented data to true data and DQ6 will not stop toggling when read. To continue operation, the device must be reset. This condition occurs when attempting to program a logic 1 state into a bit that has been programmed previously to a logic 0. Only an erase operation can change bits from 0 to 1. After reset, the device is functional and can be erased and reprogrammed. Sector-Load- Timer DQ3 DQ3 is the sector-load timer status bit it determines if the time to load additional sector addresses has expired. DQ3 remains a logic low for 80 µs after completion of a sector-erase sequence. This indicates another sector-erase command sequence can be issued. If DQ3 is at logic high, it indicates that the delay has expired and attempts to issue additional sectorerase commands are ignored. The data polling bit and toggle bit are valid during the 100 µs time delay and can be used to determine if a valid sector erase command has been issued. To ensure additional sector erase commands have been accepted, the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic low on both reads, then the additional sector-erase was accepted. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 FLASH F LASH Austin Semiconductor, Inc. DATA PROTECTION Hardware-Sector Protection Feature This feature disables both programming and erase operations on any combination of one to eight sectors. Commands to program or erase a protected sector do not change the data contained in the sector. The data-polling and toggle bits operate for 2ms to 100ms and then return to valid data. This feature is enabled using high-voltage VID (11.5V to 12V) on address pin A9 and control pin OE\ and VIL on control pin CE\. The device is delivered with all sector unprotected. Sector-unprotected mode is available to unprotect protected sectors. Sector Protect Operation The sector protect mode is activated when WE\=VIH, CE\=VIL , and address pin A9 and control pin OE\ are forced to VID. The sector-select address pins A18, A17, and A16 are used to select the sector to be protected. Address pins A0-A15 and I/O pins DQ0- DQ7 must be stable and can be VIL or VIH. Once the addresses are stable, WE\ is pulsed low for 100 ms. The operation begins on the falling edge of WE\ and terminates on the raising edge of WE\. Sector Protect Verify Verification of sector protection is activated when WE\=VIH, CE\=VIL , OE\=VIL , and address pin A9 is VID. Address pins A0 and A6 are set to VIL , and A1 is set to VIH. The sector address pins A18, A17, and A16 select the sector to be verified. The other addresses can be VIH or VIL. If the sector selected if protected, the DQs output O1. If the sector selected is unprotected the DQs output is 00. Sector protection can also be verified using the algorithmselection command. After issuing the three bus-cycle command sequence, the sector protection status can be read on DQ0. Set address pins A0 = VIL, A1 = VIH, and A6 = VIL. Sector address pins A18, A17, and A16 select the sector to be verified. The remaining addresses are set to VIL. If the sector selected is protected. DQ0 outputs a 1 state, and if the sector selected is unprotected DQ0 outputs a 0 state. This mode remains in effect until another valid sequence is written to the device. Sector Unprotect Prior to sector unprotected, all sectors should be protected using the sector unprotect mode. The sector unprotect is activated when WE\=VIH, and control pin CE\, OE\, and address pin A9 are forced to VID. Address pins A6, A12, and A16 are set to VIH. The sector select address pins A18, A17, and A16 can be VIL or VIH. All eight sectors are unprotected in parallel. Once the inputs are stable, WE\ is pulsed low for 10ms. The unprotect operation begins on the falling edge of WE\ and terminates on the raising edge of WE\. Sector Unprotect Verify Verification of the sector unprotected is activated when WE\ = VIH, OE\ = VIL, CE\ = VIL, and address pin A9 = VID. Select the sector to be verified. Address A1 and A6 are set to VIH and A0 to VIL. The other addresses can be VIL or VIH. If the sector selected is protected, the DQs output a 01, if sector selected is unprotected the DQs output a 00. Sector unprotect can also be read using the algorithm selection command. Low VCC Write Lock Out During power-up and power-down , are locked out for VCC less than VLKO If VCC