AMMC-5618-W50

AMMC - 5618 6 - 20 GHz Amplifier Data Sheet Description Avago Technologies’ AMMC-5618 6-20 GHz MMIC is an efficient two-stage amplifier designed to be used as a cascadable intermediate gain block for EW applications. In communication systems, it can be used as a LO buffer, or as a transmit driver amplifier. It is fabricated using a PHEMT integrated circuit structure that provides exceptional efficiency and flat gain performance. During typical operation with a single 5-V supply, each gain stage is biased for Class-A operation for optimal power output with minimal distortion. The RF input and output have matching circuitry for use in 50-W environments. The backside of the chip is both RF and DC ground. This helps simplify the assembly process and reduces assembly re lated performance variations and costs. For improved reliability and moisture protection, the die is passivated at the active areas. The MMIC is a cost effective alternative to hybrid (discrete FET) amplifiers that require complex tuning and assembly processes. AMMC-5618 Absolute Maximum Ratings [1] Symbol Parameters/ Conditions Units Min. Max. VD1, VD2 Drain Supply Voltage VG1 VG2 ID1 ID2 Pin Tch Tb Tstg Tmax Optional Gate Voltage Optional Gate Voltage Drain Supply Current Drain Supply Current RF Input Power Channel Temp. Operating Backside Temp. Storage Temp. Maximum Assembly Temp. (60 sec max) V V V mA mA dBm °C °C °C °C -55 -65 +165 +300 -5 -5 7 +1 +1 70 84 20 +150 Chip Size: 920 x 920 µm (36.2 x 36.2 mils) Chip Size Tolerance: ± 10µm (±0.4 mils) Chip Thickness: 100 ± 10µm (4 ± 0.4 mils) Pad Dimensions: 80 x 80 µm (3.1 x 3.1 mils or larger) Features • Frequency Range: 6 - 20 GHz • High Gain: 14.5 dB Typical • Output Power: 19.5 dBm Typical • Input and Output Return Loss: < -12 dB • Flat Gain Response: ± 0.3 dB Typical • Single Supply Bias: 5 V @ 107 mA Applications • Driver/Buffer in microwave communication systems • Cascadable gain stage for EW systems • Phased array radar and transmit amplifiers Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. Note: These devices are ESD sensitive. The following precautions are strongly recommended: Ensure that an ESD approved carrier is used when dice are transported from one destination to another. Personal grounding is to be worn at all times when handling these devices. AMMC-5618 DC Specifications / Physical Properties [1] Symbol VD1,VD2 ID1 ID2 ID1 + ID2 θ ch-b Parameters and Test Conditions Recommended Drain Supply Voltage First stage Drain Supply Current ( V D1= 5V, VG1 = Open or Ground) Second stage Drain Supply Current ( V D2= 5V, VG2 = Open or Ground) Total Drain Supply Current ( VG1 = VG2 = Open or Ground, VD1= VD2 = 5 V ) Thermal Resistance [2] (Backside temperature (Tb) = 25°C Unit V mA mA mA °C/W Min. 3 Typical 5 48 59 107 22 140 Max. 7 Notes: 1. Backside temperature Tb = 25°C unless otherwise noted 2. Channel-to-backside Thermal Resistance (θch-b) = 32°C/W at Tchannel ( Tc) = 150°C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data. AMMC-5618 RF Specifications [3, 5] (Tb = 25°C, VDD= 5 V, IDD = 107 mA, Z0 = 50 Ω) Symbol |S21|2 D|S21| RLin RLout |S12| Psat OIP3 DS21 / DT NF 2 2 Parameters and Test Conditions Small-signal Gain Small-signal Gain Flatness Input Return Loss Output Return Loss Isolation Output Power at 1dB Gain Compression @ 20 GHz Saturated Output Power (3dB Gain Compression) @ 20 GHz Output 3rd Order Intercept Point @ 20 GHz Temperature Coefficient of Gain [4] Noise Figure @ 20 GHz Unit dB dB dB dB dB dBm dBm dBm dB/°C dB Min. 12.5 9 9 40 17.5 Typical Max. 14.5 ± 0.3 12 12 45 19.5 20.5 26 -0.023 4.4 6.5 P-1dB Notes: 3. 100% on-wafer RF test is done at frequency = 6, 13 and 20 GHz, except as noted. 4. Temperature Coefficient of Gain based on sample test 5. All tested parameters guaranteed with measurement accuracy ±1.5dB for S12, ±1dB for S11, S21, S22, P1dB and ±0.5dB for NF. AMMC-5618 Typical Performance (Tchuck=25°C, VDD=5V, IDD = 107 mA, Zo=50Ω) 18 15 ISOLATION (dB) 12 GAIN (dB) 9 6 3 0 0 -10 -5 -20 INPUT RL (dB) 4 7 10 13 16 19 22 -30 -40 -50 -60 4 7 10 13 16 19 22 -70 -20 -10 0 -15 -25 4 7 10 13 16 19 22 FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz) Figure 1. Gain Figure 2. Isolation Figure 3. Input Return Loss 0 -5 OUTPUT RL (dB) -10 NF (dB) 10 24 20 16 12 8 8 P1dB (dBm) 6 -15 -20 -25 -30 4 2 4 0 4 7 10 13 16 19 22 0 4 7 10 13 16 19 22 4 7 10 13 16 19 22 FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz) Figure 4. Output Return Loss Figure 5. Noise Figure Figure 6. output Power at 1 dB Gain Compression AMMC-5618 Typical Performance vs. Supply Voltage (Tb=25°C, Zo=50Ω) 18 15 ISOLATION (dB) 12 GAIN (dB) 9 6 3 0 Vdd=4V Vdd=5V Vdd=6V 0 -10 -20 -30 -40 -50 -60 Vdd=4V Vdd=5V Vdd=6V 0 -5 INPUT RL (dB) -10 -15 -20 -25 -30 Vdd=4V Vdd=5V Vdd=6V 4 7 10 13 16 19 22 4 7 10 13 16 19 22 4 7 10 13 16 19 22 FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz) Figure 7. Gain and Voltage Figure 8. Isolation and Voltage Figure 9. Input Return Loss and Voltage AMMC-5618 Typical Performance vs. Supply Voltage (cont.) (Tb=25°C, Zo=50Ω) 0 -5 OUTPUT RL (dB) -10 P1dB (dBm) -15 -20 -25 -30 -35 4 7 10 13 16 19 22 5 15 Vdd=4V Vdd=5V Vdd=6V 25 20 10 Vdd=4V Vdd=5V Vdd=6V 0 4 7 10 13 16 19 22 FREQUENCY (GHz) FREQUENCY (GHz) Figure 10. Output Return Loss and Voltage Figure 11. Output Power and Voltage AMMC-5618 Typical Performance vs. Temperature (VDD=5V, Zo=50Ω) 18 15 ISOLATION (dB) 12 GAIN (dB) 9 6 3 0 -40 C 25 C 85 C 0 -10 -20 -30 -40 -50 -60 -40 C 25 C 85 C 0 INPUT RL (dB) -10 -20 -40 C 25 C 85 C 4 7 10 13 16 19 22 4 7 10 13 16 19 22 -30 4 7 10 13 16 19 22 FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz) Figure 12. Gain and Temperature Figure 13. Isolation and Temperature Figure 14. Input Return Loss and Temperature 0 -40 C 25 C 85 C 8 7 NOISE FIGURE (dB) 6 P1dB (dBm) 5 4 3 2 1 -40 C 25 C 85 C 25 -5 OUTPUT RL (dB) 20 -10 15 -15 10 -40 C 25 C 85 C -20 5 -25 4 7 10 13 16 19 22 0 4 7 10 13 16 19 22 0 4 7 10 13 16 19 22 FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz) Figure 15. Output Return Loss and Temperature Figure 16. Noise Figure and Temperature Figure 17. Output Power and Temperature AMMC-5618 Typical Scattering Parameters[1] (Tb=25°C, VDD= 5 V, IDD = 107 mA) S11 Freq GHz 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 7.00 7.50 8.00 8.50 9.00 9.50 10.00 10.50 11.00 11.50 12.00 12.50 13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50 17.00 17.50 18.00 18.50 19.00 19.50 20.00 20.50 21.00 21.50 22.00 dB -2.4 -2.9 -3.2 -3.6 -4.0 -4.9 -7.3 -12.7 -19.8 -23.6 -24.7 -26.4 -28.2 -26.3 -22.8 -19.9 -17.7 -16.1 -14.8 -13.9 -13.2 -12.6 -12.2 -11.9 -11.6 -11.5 -11.4 -11.4 -11.5 -11.7 -11.9 -12.2 -12.4 -12.4 -12.2 -11.5 -10.5 -9.2 -7.9 -6.7 -5.7 Mag 0.76 0.72 0.69 0.66 0.63 0.57 0.43 0.23 0.1 0.07 0.06 0.05 0.04 0.05 0.07 0.1 0.13 0.16 0.18 0.2 0.22 0.23 0.25 0.26 0.26 0.27 0.27 0.27 0.27 0.26 0.25 0.25 0.24 0.24 0.25 0.27 0.3 0.35 0.4 0.46 0.52 Phase -125 -147 -166 174 152 126 94 67 66 85 87 68 28 -23 -55 -74 -88 -100 -110 -120 -128 -136 -143 -151 -159 -166 -174 177 168 157 146 132 116 98 77 56 34 14 -5 -21 -36 dB -52.0 -35.4 -19.0 -7.4 0.8 7.7 12.5 14.7 15.1 15.1 15.0 15.0 14.9 14.9 14.9 14.8 14.8 14.7 14.7 14.7 14.6 14.6 14.6 14.6 14.7 14.7 14.7 14.8 14.9 14.9 15.0 15.1 15.1 15.2 15.2 15.2 15.0 14.8 14.5 14.1 13.5 0 0.02 0.11 0.43 1.09 2.43 4.2 5.41 5.69 5.69 5.64 5.61 5.59 5.57 5.55 5.52 5.49 5.45 5.43 5.41 5.38 5.37 5.37 5.38 5.4 5.42 5.46 5.49 5.54 5.58 5.63 5.66 5.71 5.75 5.75 5.73 5.65 5.51 5.31 5.05 4.72 S21 Mag Phase 74 -119 -102 -120 -147 178 138 94 60 34 13 -5 -22 -37 -51 -65 -77 -90 -101 -113 -124 -134 -145 -155 -166 -176 174 163 153 142 131 120 109 97 85 73 60 46 33 19 5 dB -80.0 -74.0 -69.1 -59.1 -57.7 -51.8 -48.8 -45.7 -44.5 -44.6 -44.3 -44.0 -43.9 -43.6 -43.3 -43.2 -43.1 -42.9 -42.8 -42.5 -42.5 -42.3 -42.1 -41.9 -41.7 -41.6 -41.4 -41.3 -41.1 -40.8 -40.8 -40.8 -40.5 -40.4 -40.3 -40.1 -39.9 -39.9 -40.0 -39.8 -40.3 0 0 0 0 0 0 0 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 S12 Mag Phase -134 -57 -65 -60 -104 -113 -142 -170 161 142 127 115 103 95 86 77 70 63 57 52 45 40 34 31 24 19 15 9 3 0 -7 -12 -16 -23 -29 -35 -42 -48 -55 -63 -72 dB -0.4 -0.9 -1.6 -2.6 -3.8 -5.3 -6.9 -8.6 -10.1 -11.3 -12.6 -13.9 -15.3 -16.7 -18.2 -19.7 -21.4 -22.8 -24.3 -25.1 -25.1 -24.5 -23.3 -22.2 -21.3 -20.7 -19.8 -19.1 -18.4 -17.7 -17.2 -16.7 -16.2 -15.8 -15.4 -14.9 -14.6 -14.0 -13.8 -13.5 -13.1 S22 Mag 0.95 0.91 0.84 0.75 0.64 0.55 0.45 0.37 0.31 0.27 0.23 0.2 0.17 0.15 0.12 0.1 0.09 0.07 0.06 0.06 0.06 0.06 0.07 0.08 0.09 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.16 0.17 0.18 0.19 0.2 0.2 0.21 0.22 Phase -77 -97 -118 -138 -156 -173 172 160 151 141 130 120 109 98 87 74 60 43 23 1 -22 -44 -60 -73 -85 -95 -105 -113 -121 -126 -132 -138 -143 -148 -154 -158 -163 -166 -172 -176 179 Note: 1. Data obtained from on-wafer measurements Biasing and Operation The AMMC-5618 is normally biased with a single positive drain supply connected to both VD1 and VD2 bond pads as shown in Figure 19(a). The recommended supply voltage is 3 to 5 V. No ground wires are required because all ground connections are made with plated through-holes to the backside of the device. Gate bias pads (VG1 & VG2) are also provided to allow adjustments in gain, RF output power, and DC power dissipation, if necessary. No connection to the gate pad is needed for single drain-bias operation. However, for custom applications, the DC current flowing through the input and/or output gain stage may be adjusted by applying a voltage to the gate bias pad(s) as shown in Figure 19(b). A negative gate-pad voltage will decrease the drain current. The gate-pad voltage is approximately zero volt during operation with no DC gate supply. Refer to the Absolute Maximum Ratings table for allowed DC and thermal conditions. Assembly Techniques The backside of the AMMC-5618 chip is RF ground. For microstripline applications, the chip should be attached directly to the ground plane (e.g., circuit carrier or heatsink) using electrically conductive epoxy[1]. For best performance, the topside of the MMIC should be brought up to the same height as the circuit surrounding it. This can be accomplished by mounting a gold plated metal shim (same length and width as the MMIC) under the chip, which is of the correct thickness to make the chip and adjacent circuit coplanar. The amount of epoxy used for chip and or shim attachment should be just enough to provide a thin fillet around the bottom perimeter of the chip or shim. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. The location of the RF bond pads is shown in Figure 20. Note that all the RF input and output ports are in a Ground-Signal-Ground configuration. RF connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. A single bond wire is sufficient for signal connections, however double-bonding with 0.7 mil gold wire or the use of gold mesh[2] is recommended for best performance, especially near the high end of the frequency range. Thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. Gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams with an ultrasonic power of roughly 55dB for a duration of 76 ± 8 mS. A guided wedge at an ultrasonic power level of 64 dB can be used for the 0.7 mil wire. The recommended wire bond stage temperature is 150 ± 2° C. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. The chip is 100 µm thick and should be handled with care. This MMIC has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up die with vacuum on die center.) This MMIC is also static sensitive and ESD handling precautions should be taken. Notes: 1. Ablebond 84-1 LM1 silver epoxy is recommended. 2. Buckbee-Mears Corporation, St. Paul, MN, 800-262-3824 VD1 VD2 Feedback Network Matching Matching Matching RF Output RF Input VG1 Figure 18. AMMC - 5618 Schematic VG2 To power supply 100 pF chip capacitor To power supply 100 pF chip capacitor gold plated shim gold plated shim RF Input RF Output RF Input RF Output Bonding island or small chip-capacitor To VG1 power supply (a) (b) To VG2 power supply Figure 19. AMMC - 5618 Assembly Diagram 0 920 143 Vd1 355 573 GND Vd2 530 RF RF 530 0 Vg1 Vg2 920 0 79 593 Figure 20. AMMC - 5618 Bond pad locations (dimensions in microns) 0 Ordering Information: AMMC-5618-W10 = 10 devices per tray AMMC-5618-W50 = 50 devices per tray For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3927EN AV02-0070EN - January 15, 2007