Version : 6.0
TECHNICAL
SPECIFICATION
MODEL NO. : PD035OX1
Customer’s Confirmation Customer
By
PD035OX1
PVI’s Confirmation
Confirmed By
Prepared By
FOR MORE INFORMATION:
AZ DISPLAYS, INC. 75 COLUMBIA, ALISO VIEJO, CA, 92656 Http://www.AZDISPLAYS.com
Date: January 22, 2008 This technical specification is subject to change without notice.
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page:1
PD035OX1
TECHNICAL
NO.
-
SPECIFICATION
ITEM
Cover
CONTENTS
PAGE
1
-
Contents
2
1
Application
3
2
Features
3
3
Mechanical Specifications
3
4
Mechanical Drawing of TFT-LCD module
4
5
Input / Output Terminals
5
6
Absolute Maximum Ratings
8
7
Electrical Characteristics
9
8
Pixel Arrangement
15
9
Display Color and Gray Scale Reference
16
10
Block Diagram
17
11
SPI Register Description and Timing Characteristics
21
12
Power On Sequence
22
13
Optical Characteristics
23
14
Handling Cautions
25
15
Reliability Test
26
16
Packing
27
-
Revision History
-
-
Appendix
-
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:2
1. Application
This technical specification applies to 3.5” color TFT-LCD panel PD035OX1.
PD035OX1
The TFT LCD panel applies to videophone, door phone and other electronic products which require high quality flat panel displays.
2. Features
. Amorphous silicon TFT-LCD panel with LED Backlight unit . Support digital 8-bits serial / 24-bits parallel RGB and CCIR601/656 input mode. . OSD overlay supported in CCIR601/656 input mode. . Optimum viewing direction 6 o’clock.
. Provide source and gate drivers control timing. . Image Reversion : Up/Down and Left/Right
3. Mechanical Specifications
Parameter Screen Size Display Format Specifications 3.5 (diagonal) 320 (RGB) x 234 Unit inch dot
Display colors Active Area
262,144
71.6 (H) 52.65 (V)
mm
Pixel Pitch Pixel Configuration Outline Dimension Surface Treatment
0.22375 (H) 0.225 (V) Delta 84.03 (W) 65.24(H) 3.43 (D) Anti – Glare
mm
mm
Back-light W eight
LED 42²5
g
Display model
Normally white
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:3
4. Mechanical Drawing of TFT-LCD Module
PD035OX1
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:4
NO BENDING AREA
PD035OX1
5. Input / Output Terminals
CON1 FPC Down Connect , 30Pins , Pitch : 0.5 mm Pin No Symbol I/O Description Remark
1
D15(G5)
I
Green Data
2
D14(G4)
I
Green Data
3
D13(G3)
I
Green Data
4
D12(G2)
I
Green Data
Note 5-1
5
D11(G1)
I
Green Data
6
D10(G0)
I
Green Data(LSB)
7
VDD2
I
Analog power supply for source driver
Note 5-2
8
V8
I
Gamma correction voltage 8
9
V7
I
Gamma correction voltage 7
10
V6
I
Gamma correction voltage 6
11
V5
I
Gamma correction voltage 5
12
V4
I
Gamma correction voltage 4
Note 5-3
13
V3
I
Gamma correction voltage 3
14
V2
I
Gamma correction voltage 2
15
V1
I
Gamma correction voltage 1
16
VSS2
I
Analog ground for source driver
17
D07(R7)
I
Red Data(MSB)
18
D06(R6)
I
Red Data
19
D05(R5)
I
Red Data
20
D04(R4)
I
Red Data
21
D03(R3)
I
Red Data
Note 5-1
22
D02(R2)
I
Red Data
23
D01(R1)
I
Red Data
24
D00(R0)
I
Red Data(LSB)
25
CLK
I
Clock signal. Latching data at the rising edge
26
HS
I
Horizontal sync input in RGB mode and CCIR601
Note 5-4
27
VS
I
Vertical sync input in RGB mode and CCIR601
Note 5-5
28
DEN
I
Input data enable control.(Normally pull low)
Note 5-6
29
VCC
I
Digital power supply for source driver IC
Note 5-7
30
VCOM
I
Voltage for common electrode
Note 5-8
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:5
PD035OX1
CON2 FPC Down Connect , 30Pins , Pitch : 0.5 mm Pin No Symbol I/O Description Remark
1
VLED
I
Power supply for LED
Note 5-9
2
GLED1
I
Ground for LED
3
GLED2
I
Ground for LED
4
NC
-
NC
5
VGH
I
Positive power for gate driver
Note 5-10
6
VDD1
I
Power supply for gate logic circuit
Note 5-11
7
VSS1
I
Ground for gate driver
8
VEE
I
Negative power for gate driver
Note 5-12
9
VDD1
I
Power supply for gate logic circuit
Note 5-11
10
GND
I
Digital ground for source driver IC
11
RESETB
I
Hardware global reset, (low active)
12
VSET
I
Externally/Internally gamma voltage setup
13
U/D
I
Up/Down control for gate driver
14
L/R
I
Left/Right control for source driver
Note 5-13
15
IF2
I
Select the input data format (Serial RGB, Parallel RGB, CCIR601/656)
16
IF1
I
Note 5-14
17
SPENA
I
Serial port data enable signal (normally pull high)
`18
SPCK
I
Serial port clock. (Normally pull high)
19
SPDA
I/O
Serial port data input/output
20
POL
O
Polarity select for the line inversion control signal Note 5-15
21
D27(B7)
I
Blue Data(MSB)
22
D26(B6)
I
Blue Data
23
D25(B5)
I
Blue Data
24
D24(B4)
I
Blue Data
25
D23(B3)
I
Blue Data
Note 5-1
26
D22(B2)
I
Blue Data
27
D21(B1)
I
Blue Data
28
D20(B0)
I
Blue Data(LSB)
29
D17(G7)
I
Green Data(MSB)
30
D16(G6)
I
Green Data
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:6
PD035OX1
Note 5-1 : Digital data input. DX0 is LSB and DX7 is MSB. If parallel RGB input mode is used, D0X, D1X, and D2X indicate R, G and B data in turn. If serial RGB or CCIR601/656 input mode is selected, only D07~D00 are used, and others short to Vss. Note 5-2 : VDD2 Typ. = +5V Note 5-3 : The output voltage is determined by the digital input data. If digital RGB or CCIR601/656 input mode is selected, The 8 gamma correction reference voltages can be set to externally or generate internally. If VSET = ”H”, the gamma correction voltage generated externally If VSET = “L”, the default value is as below : (When VDD =+5V)
Default Voltage(V)
V1 4.29
V2 3.73
V3 3.33
V4 2.94
V5 2.62
V6 2.22
V7 1.51
V8 0.48
Note 5-4 : Horizontal sync input in digital RGB mode. Or HREF input in CCIR601 mode. ( Short to Vss if not used ) Note 5-5 : Vertical sync input in digital RGB mode. Or V123 input in CCIR601 mode. ( Short to Vss if not used ) Note 5-6 : Digital RGB data input format For digital RGB input data format, both SYNC. Mode and DEN mode are supported. If DEN signal is fixed low, SYNC. Mode is used. Otherwise , DEN mode is used. Note 5-7 : VCC Typ. = +3.3V Note 5-8 : VCOM Typ. +6.0Vpp
Note 5-9 : ILED Typ. = 20mA., VLED Typ. = 9V Note 5-10 : VGH Typ. =+15V. Note 5-11 : VDD1 Typ. +3.3V.
Note 5-12 : VEE Typ. = -15V. Note 5-13 : The definition of L/R , U/D
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:7
PD035OX1
Note 5-14 : IF1,IF2 control the input data format.
IF2,IF1
L,L (default)
Input data format
Serial RGB
L,H
Parallel RGB
H,L
CCIR601
H,H
CCIR656
Note 5-15 : When POL=L, output voltage is negative polarity. When POL=H, output voltage is positive polarity.
6. Absolute Maximum Ratings
Parameter Symbol VCC MIN. -0.3 VSS1=VSS2=0 V Ta = 25 MAX. Unit Remark +7.0 V
Supply voltage for source driver
VDD2
-0.3
+7.0
V
VDD1
-0.3
+7.0
V
Supply voltage for gate driver
H Level VGH
-0.3
+32.0
V
L Level VEE
-22.0
+0.3
V
VGH-VEE
-0.3
+45.0
V
Input signal voltage
VIN
-0.3
VDD+0.3
V
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:8
PD035OX1
7. Electrical Characteristics
7-1 Operating condition VSS1=VSS2=0 V Ta = 25 MAX. Unit Remark +3.6 V +5.5 V +3.6 V +30 V -5 V VCC V 0.3VCC V VCC V 0.2VCC V
Parameter
Supply voltage for source driver
Supply voltage for gate driver
Signal input voltage
Signal output voltage
Logic Analog Logic H level L level H level L level H level L level
Symbol MIN. VCC +3.0 VDD2 +3.8 VDD1 +3.0 VGH +10 VEE -17 VIH 0.7VCC VIL 0 Vo H 0.8VCC Vo L 0
Typ. +3.3 +5.0 +3.3 +15 -15 -
VCOMAC
-
+6.0
-
VP-P
VCOM VCOMDC 1.0 V
AC Component of VCOM
DC Component of VCOM Note 7-1
Note 7-1 : PVI strongly suggests that the VCOMDC level shall be adjustable , and the adjustable level range is 1V 1V , every module’s VCOMDC level shall be carefully adjusted to show a best image performance.
7-2 Recommended driving condition for LED backlight Parameter Supply voltage of LED backlight Supply current of LED backlight Symbol VLED ILED Min 9.0 TYP 10.0 20 MAX 11.0 Unit V mA Remark IL = 20 mA Note 7-2
Backlight Power Consumption
PLED
360
400
440
mW
Note 7-3
Note 7-2 : LED B/L applied information , please refer to the appendix at the end . Note 7-3 : PLED = 2*ILED*VLED .
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. PAGE:9
PD035OX1
7-3 Power consumption Parameter Supply current for gate driver (Hi level) Symbol IGH
IDD1
Supply current for gate driver(Logic)
VSS1=VSS2=0 V Conditions TYP. MAX. Unit VGH +15V mA 0.2 0.5 mA VDD1 +3.3V 0.05 0.1
Ta = 25 Remark
Supply current for gate driver (Low level)
IEE
VEE
-15V
0.2
0.5
mA
VEE center voltage
Supply current for source driver(Analog)
VDD2
VDD2 +5V
5.0
8.0
mA
Supply current for source driver(Logic)
VCC
VCC
+3.3V
4.5
7.0
mA
LCD panel power consumption
-
48
80
mW
Backlight power consumption
PLED
400
440
mW
Total power consumption Above data measured on serial mode:
0.45
0.52
W
If on parallel mode, ICC Typ.= 3.0mA, Max.=5.0mA ; panel power consumption Typ.= 41.5mW panel power consumption Typ.= 51.4mW Max.= 72.8mW. Max.= 89.3mW. If on CCIR601/656 mode, ICC Typ.= 6.0mA, Max.=10.0mA ;
7-4 Timing characteristics of input signals 7.4.1 Serial 8 bits RGB interface Characteristics Symbol CLK period TOSC Data setup time TSU Data hold time THD HS period TH HS pulse width THS HS rising time TCr HS falling time TCf VS pulse width TVS VS rising time TVr VS falling time TVf HS falling to VS falling time for THVO odd field VS falling to HS falling time for THVE even field Min. 12 12 5 1 Typ. 52 1224 90 3 Max. 700 300 5 700 1.5 Unit ns ns ns TOSC TOSC ns ns TH ns us Remark Note 7-4
0
3
-
TOSC
0
3
-
TOSC
VS-DEN time
TVSE
-
21
-
TH
HS-DEN time DEN pulse width
THE TEP
108 -
204 960
264 -
TOSC TOSC
VS period
st
-
262
th
-
TH
Note 7-4 : When SYNC mode is used, 1 data start from 204 CLK after HS fallings.
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PD035OX1
7.4.2 Parallel 24 bits RGB interface Characteristics Symbol CLK period TOSC Data setup time TSU Data hold time THD HS period TH HS pulse width THS HS rising time TCr HS falling time TCf VS pulse width TVS VS rising time TVr VS falling time TVf HS falling to VS falling time for THVO odd field VS falling to HS falling time for THVE even field Min. 12 12 5 1 Typ. 156 408 30 3 Max. 700 300 5 700 1.5 Unit ns ns ns TOSC TOSC ns ns TH ns us Remark Note 7-5
0
3
-
TOSC
0
3
-
TOSC
VS-DEN time
TVSE
-
21
-
TH
HS-DEN time DEN pulse width
THE TEP
36 -
68 320
88 -
TOSC TOSC
VS period
st
-
262
th
-
TH
Note 7-5 : When SYNC mode is used, 1 data start from 68 CLK after HS fallings. 7.4.3 CCIR601/656 Interface Characteristics CLK period Data setup time Data hold time Symbol TOSC TSU THD Min. 12 12 Typ. 37 Max. Unit ns ns ns Remark
7.4.4 Hardware reset timing Characteristics RESETB low pulse width
Symbol TRSB
Min. 200
Typ. -
Max. -
Unit ns
Remark
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PD035OX1
7.5 Timing controller timing chart 7.5.1 Clock and Data waveform
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PD035OX1
7.5.2 HS,VS,DEN timing waveform HS and VS timing relationship
O d d fie ld
HS
THVO
VS
E v e n fie ld
HS
TH V E
VS
HS and DEN timing relationship
HS
T HS
T HE
DEN
HS, VS and DEN timing relationship
HS
VS
T VS
T VSE
DEN
T EP
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PD035OX1
7.5.3 CCIR601 timing waveform (VS_POL=”H”, HS_POL=”L” in Register R2) ITU-R BT.601 NTSC Input Timing
Data Blanking Data
Blanking
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PD035OX1
ITU-R BT.601 PAL Input Timing
Data Blanking Data
Blanking
8. Pixel Arrangement
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PD035OX1
9. Display Color and Gray Scale Reference
Input Color Data
Color
Red
Green
Blue
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black Red (255) Green Basic Blue (255) Color Cyan s Magenta Yellow
0 1 0 0 0 1 1
0 1 0 0 0 1 1
0 1 0 0 0 1 1
00 11 00 00 00 11 11
0 1 0 0 0 1 1
0 1 0 0 0 1 1
0 1 0 0 0 1 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 1 0 1 0 1
0 0 0 1 1 1 0
0 0 0 1 1 1 0
0 0 0 1 1 1 0
00 00 00 11 11 11 00
0 0 0 1 1 1 0
0 0 0 1 1 1 0
0 0 0 1 1 1 0
W hite Red (00) Red (01) Red (02) Darker Red Brighter Red (253) Red (254)
1 0 0 0
1 0 0 0
1 0 0 0
11 00 00 00
1 0 0 0
1 0 0 1
1 0 1 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
11 00 00 00
1 0 0 0
1 0 0 0
1 0 0 0
1 1
1 1
1 1
11 11
1 1
0 1
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
00 00
0 0
0 0
0 0
Red (255) Green (00) Green (01) Green (02) Darker Green Brighter Green Green
1 0 0 0
1 0 0 0
1 0 0 0
11 00 00 00
1 0 0 0
1 0 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 0 0
0 0 0 0
0 0 0 0
00 00 00 00
0 0 0 0
0 0 0 0
0 0 0 0
0 0
0 0
0 0
00 00
0 0
0 0
0 0
1 1
1 1
1 1
1 1
1 1
1 1
0 1
1 0
0 0
0 0
0 0
00 00
0 0
0 0
0 0
Green Blue (00) Blue (01) Blue (02) Darker Blue Brighter Blue (253) Blue (254)
0 0 0 0
0 0 0 0
0 0 0 0
00 00 00 00
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
00 00 00 00
0 0 0 0
0 0 0 1
0 0 1 0
0 0
0 0
0 0
00 00
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
1 1
1 1
11 11
1 1
0 1
1 0
Blue (255)
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
1
1
1
11
1
1
1
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PD035OX1
10. Block Diagram
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PD035OX1
11. SPI Register Description and Timing Characteristics
11.1 Function Control Register Register R0 :Address(A3~A0) Bit 0000
D7 D6 D5 D4 D3 D2 D1 D0 reserve Name STHD1 STHD0 STHP4 STHP3 STHP2 STHP1 STHP0 d Default 0 0 0 0 0 0 0 0
STHD [1:0] : adjust start pulse position by dot STHD1 STHD0 STH position adjust by dot 1 1 -1 1 0 -2 0 0 0 0 1 +1
STHP [4:0] : adjust start pulse position by pixel STHP4 STHP3 STHP2 STHP1 STHP0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1
STH position adjust by pixel -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15
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Register R1 :Address(A3~A0)
0001
PD035OX1
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name STVP3 STVP2 STVP1 STVP0 STVNT1 STVNT0 STVPAL1 STVPAL0 Default 0 0 0 0 0 0 0 1
STVP [3:0] : adjust first line position by line STV position adjust by line STVP3 STVP2 STVP1 STVP0 1 1 1 1 -1 1 1 1 0 -2 1 1 0 1 -3 1 1 0 0 -4 1 0 1 1 -5 1 0 1 0 -6 1 0 0 1 -7 1 0 0 0 -8 0 0 0 0 0 0 0 0 1 +1 0 0 1 0 +2 0 0 1 1 +3 0 1 0 0 +4 0 1 0 1 +5 0 1 1 0 +6 0 1 1 1 +7
STVNT[1:0]: When NTSC mode, the relationship of first line in Even field and Odd field. 00: First line in Even field = First line in Odd field. 01: First line in Even field = First line in Odd field +1. 10: No use. 11: First line in Even field = First line in Odd field –1. STVPAL[1:0]: When PAL mode, the relationship of first line in Even field and Odd field. (Only for CCIR601/656 mode) 00: First line in Even field = First line in Odd field. 01: First line in Even field = First line in Odd field +1. 10: No use. 11: First line in Even field = First line in Odd field –1.
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PD035OX1
Register R2 :Address(A3~A0)
Bit D7 D6 D5
0010
D4 D3 D2 D1
Name
Default
D0 NPC_SE reserved reserved reserved reserved HS_POL VS_POL NPC_IN T 0 0 0 1 0 0 1 0
HS_POL: HS polarity setting. HS_POL = “L”, negative polarity. HS_POL = “H”, positive polarity. VS_POL: VS polarity setting. VS_POL = “L”, negative polarity. VS_POL = “H”, positive polarity. NPC_IN: Define the NTSC/PAL mode by SPI. NPC_IN = “L”, PAL. (Only for CCIR601/656 mode) NPC_IN = “H”, NTSC. NPC_SET: Set the NTSC/PAL auto detection or define by NPC_IN. NPC_SET = “L”, auto detection. NPC_SET = “H”, define by SPI. Register R3 :Address(A3~A0) Bit D7 D6 0011 D5 D4 D3
Name
Default
D2 D1 D0 OSDCLK OSDVSD reserved reserved reserved reserved PWD_EN OSDHSP P 0 0 1 0 1 0 1 1
PWD_EN: Set DAC power saving function. PWD_EN = “L”, disable. The DAC is always power on. PWD_EN = “H”, enable.
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11-2 SPI timing characteristic Characteristics SPCK period SPCK high width SPCK low width Data setup time Data hold time SPENA to SPCK setup time SPENA to SPDA hold time SPENA high pulse width SPDA output latency Symbol TCK TCKH TCKL TSU1 THD1 TCS TCE TCD TCR Min. 60 30 30 12 12 20 20 50 Typ. 1/2 Max. Unit ns ns ns ns ns ns ns ns TCK
PD035OX1
Remark
S I "r e a d "t i m i n g P
SD PA
TU1 TD 1 S H
TR C
1
A 3
A 2
A 1
A 0
D 7
D 6
TK L C
D 5
D 4
D 3
D 2
D 1
D 0
SC K P
SE N P A
TK C
TK H C
TS C
TD C
TE C
S I "w r i t e "t i m i n g P
TU1 T D 1 H S
SD PA
0
A 3
A 2
A 1
A 0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
SC K P
SE N A P
TS C
TK C
TK L C
TK H C
TD C
TE C
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PD035OX1
12. Power On Sequence The Power on sequence only effect by VCC,VSS,VDD,VEE and VGH, the others do not care.
OFF
ON T1 T2
>10ms >10ms
OFF
T3 T4
OFF
Backlight ON
OFF
1) 10ms T1
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