PI2EQX4402NBE

PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater/Equalizer Features Description • Two High Speed PCI Express lanes • Supports PCI Express data rates (2.5 Gbps) on each lane • Adjustable Transmiter De-Emphasis & Amplitude • Adjustable Receiver Equalization • Two Spread Spectrum Reference Clock Buffer Outputs • 100Ω Differential CML I/O’s • Low Power (100mW per Channel) • Standby Mode – Power Down State • VDD Operating Range: 1.8V +/-0.1V • Packaging (Pb-free & Green): - 84-ball LFBGA Pericom Semiconductor’s PI2EQX4402 is a low power, PCI Express compliant signal re-driver. The device provides programmable equalization, amplification, and de-emphasis by using 7 select bits, SEL[0:6], to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX4402 supports four 100 Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the PCI Express signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the PCI Express signal after the re-driver. In addition to providing signal re-conditioning, Pericom’s PI2EQX4402 also provides power management Stand-by mode operated by a Bus Enable pin. Block Diagram Pin Description (Top View)   0 *.%$1!+ 0 $&$-$'# &) 0 0                     
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   .""!+    1                       PS8778E 02/15/06 PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer Pin Description Pin # B1, F1, D2, E2, B3, F3, H4, B8, F8, B10, F10 C3 D3 E1, J1, F2, E3, J3, H7, E8, J8, D9, E9, F9, E10, J10 C8 D8 G3 H3 G8 H8 A3, B4, B5 A4, C4, C5 G2, J2, J4 H2, K2, J5 B6, A5 C6, A6 K3, K4 J6, J9 B7, A7 C7, A8 K9, G9 K10, H9 Pin Name I/O VDD PWR AI+ AI- I I GND PWR BI+ BICI+ CIDI+ DISEL[0:2]_A SEL[0:2]_B SEL[0:2]_C SEL[0:2]_D SEL[3:4]_A SEL[3:4]_B SEL[3:4]_C SEL[3:4]_D SEL[5:6]_A SEL[5:6]_B SEL[5:6]_C SEL[5:6]_D I I I I I I I I I I I I I I I I I I C10 AO+ O D10 AO- O C1 BO+ O D1 BO- O G10 CO+ O H10 CO- O G1 DO+ O H1 DO- O A9, A10, B9, C9 EN_ [A,B,C,D] I Description 1.8V Supply Voltage Positive CML Input Channel A with internal 50Ω pull down Negative CML Input Channel A with internal 50Ω pull down Supply Ground Positive CML Input Channel B with internal 50Ω pull down Negative CML Input Channel B with internal 50Ω pull down Positive CML Input Channel C with internal 50Ω pull down Negative CML Input Channel C with internal 50Ω pull down Positive CML Input Channel D with internal 50Ω pull down Negative CML Input Channel D with internal 50Ω pull down Selection pins for equalizer (see Amplifier Configuration Table) w/ 50KΩ internal pull up Selection pins for amplifier (see Amplifier Configuration Table) w/ 50KΩ internal pull up Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50KΩ internal pull up Positive CML Output Channel A internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Negative CML Output Channel A with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Positive CML Output Channel B with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Negative CMLOutput Channel B with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Positive CMLOutput Channel C with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Negative CMLOutput Channel C with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Positive CMLOutput Channel D with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. Negative CMLOutput Channel D with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. EN_[A:D] is the enable pin with internal 50KΩ pull up resistor. A LVCMOS high provides normal operation. A LVCMOS low selects a low power down mode. 2 PS8778E 02/15/06 PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer Pin Description (Continued) Pin # H6 H5 Pin Name CKINCKIN+ OUT0+, OUT0OUT1+, OUT1IREF EN_CLK NC K5, K6 K7, K8 J7 K1 A1, A2, B2, C2 Inputs EN_[A, B, C, D] High Low I/O I I Description Differential Input Reference Clock O Differential Reference Clock Output O O I N/A External 475Ω resistor connection to set the differential output current Enable output clock pin with internal 50KΩ pull up resistor No connect pins. For normal operation, leave pins floating Outputs O+ / ONormal output No output Inputs EN_CLK High Low Clock Outputs Clock output No clock output Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ –65°C to +150°C Supply Voltage to Ground Potential ................................... –0.5V to +2.5V DC SIG Voltage..........................................................–0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 800mW Operating Temperature.............................................................. 0 to +70°C Output Swing Control SEL3_[A:D] 0 0 1 1 SEL4_[A:D] 0 1 0 1 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Output De-emphasis Adjustment Swing 1x 0.8x 1.2x 1.4x SEL5_[A:D] 0 0 1 1 SEL6_[A:D] 0 1 0 1 De-emphasis 0dB -2.5dB -3.5dB -4.5dB Equalizer Selection SEL0_[A:D] 0 0 0 0 1 1 1 1 SEL1_[A:D] 0 0 1 1 0 0 1 1 SEL2_[A:D] 0 1 0 1 0 1 0 1 Compliance Channel No Equalization [0:1.5dB] @ 1.25 GHz [0:2.5dB] @ 1.25 GHz [0:3.5dB] @ 1.25 GHz [0:4.5dB] @ 1.25 GHz [0:5.5dB] @ 1.25 GHz [0:6.5dB] @ 1.25 GHz [0:7.5dB] @ 1.25 GHz 3 PS8778E 02/15/06 PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer AC/DC Electrical Characteristics for 2.5 Gbps Quad Repeater/Equalizer (VDD = 1.8 ±0.1V) Symbol Ps Parameter Supply Power Latency CML Receiver Input RLRX Return Loss Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage DC Differential Input ZRX-DIFF-DC Impedance ZRX-DC DC Input Impedance Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. Typ. 50 MHz to 1.25 GHz Max. 0.1 0.6 Units W 2.0 ns 12 dB 0.175 1.200 V 150 mV 80 100 120 40 50 60 Ω Equalization JRS Residual Jitter(1,2) JRM Random Jitter(1,2) Total Jitter Deterministic jitter 0.3 0.2 1.5 Ulp-p psrms Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1. FR4 Signal Source A B C Pericom PI2EQX4402 SmA Connector SmA Connector In Out 30IN Figure 1. Test Condition Referenced in the Electrical Characteristic Table 4 PS8778E 02/15/06 PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer AC/DC Electrical Characteristics for 2.5 Gbps x2 Lane Repeater/Equalizer (TA = 0 to 70˚C) Symbol Parameter Conditions Min. Typ. Max. Units 900 mVp-p 150 ps CML Transmitter Output (100Ω differential) VDIFFP Output Voltage Swing Differential Swing | VTX-D+ - VTX-D- | VTX-C Common-Mode Voltage | VTX-D+ + VTX-D- | / 2 tF, tR Transition Time 20% to 80% (1) ZOUT Output resistance Single ended ZTX-DIFF-DC 400 VDD0.3 40 50 60 Ω DC Differential TX Impedance 80 100 120 Ω CTX AC Coupling Capacitor 75 200 nF VTX-DIFFP-P Differential Peak-to-peak Ouput Voltage 0.8 1.8 V 0.65 × VDD VDD VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | LVCMOS Control Pins VIH Input High Voltage VIL Input Low Voltage 0.35 × VDD IIH Input High Current 250 IIL Input Low Current 500 V μA Note: 1. Using K28.7 (0011111000) pattern) 5 PS8778E 02/15/06 PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer AC Switching Characteristics for Clock Buffer (VDD = 1.8 ±0.1V, AVDD = 1.8 ±0.1V) (3) Symbol Trise / Tfall Parameters Rise and Fall Time (measured between 0.175V to 0.525V) (1) Min Max. 125 525 ΔTrise / ΔTfall Rise and Fall Time Variation VHIGH Voltage High including overshoot 660 VLOW Voltage Low including undershoot -200 Absolute crossing point voltages 200 VCROSS ΔVCROSS Total Variation of Vcross over all edges TDC Duty Cycle (input duty cycle = 50%) (2) 75 Units 1 ps 900 550 55 1 1 mV 250 45 Notes 1 1 1 % 2 Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF. Configuration Test Load Board Termination Rs 337 5% Clock TLA CLKBUF Rs 337 5% Clock# TLB Rp 49.97 1% 4757 1% Rp 49.97 1% 2pF 5% 2pF 5% Figure 2. Configuration test load board termination Note: • TLA and TLB are 3” transmission lines. 6 PS8778E 02/15/06 PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer "3# "3# "3# Packaging Mechanical: 84-Ball LFBGA (NB) "3# 0.50 ± 0.05 "3# Ordering Information Ordering Number Package Code Package Description PI2EQX4402NB NB 84-Ball LFBGA PI2EQX4402NBE NB Pb-free & Green 84-Ball LFBGA Notes: s4HERMALCHARACTERISTICSCANBEFOUNDONTHECOMPANYWEBSITEATWWWPERICOMCOMPACKAGING s%0B FREE'REEN s8SUFlX4APE2EEL Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 7 PS8778E 02/15/06