PI6C2409-1
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Zero-Delay Clock Buffer
Product Features
Functional Description
•
•
•
•
The PI6C2409-1 is a PLL based, zero-delay buffer, with the ability
to distribute nine outputs of up to 133MHz at 3.3V.
All the outputs are distributed from a single clock input CLKIN and
output OUT0 performs zero delay by connecting a feedback to PLL.
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 200ps
Internal feedback allows outputs to be synchronized to the
clock input
• Operates at 3.3V VDD
• Space-saving Packages: (Pb-free & Green available)
150-mil SOIC (W)
173-mil TSSOP (L)
PI6C2409-1 has two banks of four outputs that can be controlled by
the selection inputs, SEL1 & SEL2. It also has a powersparing feature:
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all
outputs are referenced from CLKIN. PI6C2409-1 is available in
high drive and industrial environment versions.
An internal feedback on OUT0 is used to synchronize the
outputs to the input; the relationship between loading of this signal
and the outputs determines the input-output delay.
PI6C2409-1 are characterized for both commercial and
industrial operation
Block Diagram
CLKIN
Pin Configuration
PLL
OUT0
MUX
CLKIN
OUTA1
OUTA2
VDD
GND
OUTB1
OUTB2
SEL2
OUTA1
OUTA2
OUTA3
SEL1
SEL2
Decode
Logic
OUTA4
OUTB1
OUTB2
PI6C2409(-1, -1H)
09-0048
1
2
3
4
5
6
7
8
16
15
1 6 - P i n14
W, L 13
12
11
10
9
OUT0
OUTA4
OUTA3
VDD
GND
OUTB4
OUTB3
SEL1
OUTB3
OUTB4
1
PS8613C
03/10/09
PI6C2409-1
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Zero-Delay Clock Buffer
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Input Select Decoding
SEL2
SEL1
OUTA [1-4]
OUTB [1-4]
Output Source
(OUT0)
PLL
0
0
3- State
3- State
PLL
ON
0
1
PLL
3- State
PLL
ON
1
0
CLK IN
CLK IN
CLK IN
O FF
1
1
PLL
PLL
PLL
ON
Pin Description
Pin
Signal
D e s cription
1
C LK IN
Input clock reference frequency (weak pull- down)
2, 3, 14, 15
O UTA[1- 4]
C lock outputs, Bank A
4, 13
VDD
3.3V supply
5, 12
GN D
Ground
6, 7, 10 ,11
O UTB[1- 4]
C lock outputs, Bank B
8
SEL2
Select input, bit 2 (weak pull- up)
9
SEL1
Select input, bit 1 (weak pull- up)
16
O UT0
C lock O utput , internal PLL feedback
09-0048
2
PS8613C
03/10/09
PI6C2409-1
Zero-Delay Clock Buffer
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Zero-Delay and Skew Control
CLKIN Input to OUTx Delay vs. Difference in Loading between OUT0 pin and OUTx pins
CLKIN - Input to OUTx Delay (ps)
800
600
400
200
0
-200
-25
-20
-15
-10
0
-5
5
10
15
-400
20
25
PI6C2409-1H
-600
-800
PI6C2409-1
-900
-1000
Output Load Difference: OUT0 Load - OUTx Load (pF)
The relationship between loading of the OUT0 signal and other outputs determines the input-output delay. Zero delay is achieved when
all outputs, including feedback, are loaded equally.
Maximum Ratings
Supply Voltage to Ground Potential ............................................................................................................................. –0.5V to +7.0V
DC Input Voltage (Except CLKIN) ........................................................................................................................ –0.5V to VDD +0.5V
DC Input Voltage CLKIN ...................................................................................................................................................... –0.5 to 7V
Storage Temperature ................................................................................................................................................... –65ºC to +150ºC
Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC
Junction Temperature .................................................................................................................................................................. 150ºC
Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V
Operating Conditions (VCC = 3.3V ±0.3V)
Parame te r
VDD
TA
CL
CIN
09-0048
De s cription
M in.
M a x.
Units
3 .0
3 .6
V
0
70
Industrial Operating Temperature
–4 0
85
Load Capacitance, below 100 MHz
⎯
30
Load Capacitance, from 100 MHz to 133 MHz
⎯
15
Input Capacitance
⎯
7
Supply Voltage
Commerical Operating Temperature
3
ºC
pF
PS8613C
03/10/09
PI6C2409-1
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Zero-Delay Clock Buffer
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DC Electrical Characteristics for Industrial Temperature Devices
Parame te r
De s cription
Te s t Conditions
M in.
M ax.
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50.0
IIH
Input HIGH Current
VIN = VDD
125
VO L
Output LOW Voltage
IO L = 8mA (–1); IO L = 12mA (–1H)
VO H
Output HIGH Voltage
IO H = –8mA (–1); IO H = –12mA (–1H)
IDD
Bypass, PLL OFF
SEL1 = 0, SEL2 = 1
IDD
Supply Current
Unloaded outputs 100 MHz, Select inputs at VDD or GND
5 4 .0
Unloaded outputs 66 MHz, CLKIN
3 9 .0
Units
0.8
V
N
2.0
0.4
V
2.4
SI
O
R
μA
1. 0
mA
mA
AC Electrical Characteristics for Industrial Temperature Devices
O utput Frequency
Duty C ycle(1) (–1, –1H)
tDC
tF
tSK(O)
t0
Rise Time(1) (–1H)
tSLEW
tJIT
30pF load (–1, –1H)
10pF load, (–1, –1H)
M in.
Typ.
100
10.0
Measured at VDD/2, FOUT = 66.67MHz
40.0
Measured at VDD/2V, FOUT
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