PI7C9X2G404EVAZXAEX

PI7C9X2G404EV PCI EXPRESS GEN 2 PACKET SWITCH 4-Port, 4-Lane, ExtremeLo PCIe2.0 Packet Switch DATASHEET REVISION 8 December 2020 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS39929 Rev 8-2 PI7C9X2G404EV IMPORTANT NOTICE 1. DIODES INCORPORATED AND ITS SUBSIDIARIES (“DIODES”) MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes products described herein and application examples. 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Copyright © 2020 Diodes Incorporated www.diodes.com PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 2 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV REVISION HISTORY Date 09/06/17 12/19/17 Revision Number 07/12/18 2 01/15/19 3 02/20/19 09/12/19 4 5 10/15/19 6 07/29/20 7 12/15/20 8 1 PI7C9X2G404EV Document Number DS39929 Rev 8-2 Description Preliminary Datasheet Reg40h[15:8] next item point to 4ch for both up/downport port MSI register are for both up&downport, not downport only anymore Multiple Message Capable modify form 3b'001 to 3'b010 Update 74h[7], 8Ch[7][12]. Update 340h[4][5] Add cfg offset 300h to 314h Update 8Ch[12] Add cfg offset 318h and 31Ch Update 98h[15:0] Update REG[9c]: trigger[6:3], clear[2], port[1:0], and REG[a0] Update Ini for REG[98][15:0] = 0126 Add cfg offset B0h to FFh Delete Misc Control 5 (offset 314h) Updated section 15 Ordering Information Added Fig 13-3 Part Marking Update Feature Add Chap 6.2 and 6.3 Update 7.2.54 OPERATION MODE –OFFSET 98h Add Chap 13 Update Table 9-3 Update Table 12-1 Updated Section 1 Features Updated 3.2 Port Configuration Signals Updated Section 7.2.125 MISC CONTROL 0 REGISTER – OFFSET 300h Updated Section 7.2.126 MISC CONTROL 1 REGISTER – OFFSET 304h Updated Section 10 Power Management Updated Section 12.1 Absolute Maximum Ratings New revision number due to document control process Updated Section 12.4 Power Consumption Updated Section 15 Ordering Information Updated Section 1 Features Updated Section 3.1 PCI Express Interface Signals Updated Table 5-2 Receiver Signal Detect Threshold Updated Figure 14-3 Part Marking Updated Section 8 Clock Scheme Updated Section 5-1 Physical Layer Circuit Updated Table 6-1, 6-3, 6-5 and 6-6 Updated Figure 6-6 and 6-9 Updated Section 6.1.4 and 7.2.2 Updated Notes for Table 12-2 DC Electrical Characteristics For Datasheet Status Change Page 3 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV TABLE OF CONTENTS 1  FEATURES .................................................................................................................................................................... 10  2  GENERAL DESCRIPTION ......................................................................................................................................... 11  3  PIN DESCRIPTION...................................................................................................................................................... 13  3.1  3.2  3.3  3.4  3.5  4  PIN ASSIGNMENTS .................................................................................................................................................... 18  4.1  5  PCI EXPRESS INTERFACE SIGNALS .................................................................................................... 13  PORT CONFIGURATION SIGNALS ....................................................................................................... 14  MISCELLANEOUS SIGNALS.................................................................................................................. 15  JTAG BOUNDARY SCAN SIGNALS ...................................................................................................... 16  POWER PINS ............................................................................................................................................. 16  PIN LIST OF 136-PIN AQFN ...................................................................................................................... 18  FUNCTIONAL DESCRIPTION .................................................................................................................................. 19  5.1  PHYSICAL LAYER CIRCUIT .................................................................................................................. 19  5.1.1  RECEIVER DETECTION ................................................................................................................... 19  5.1.2  RECEIVER SIGNAL DETECTION ..................................................................................................... 20  5.1.3  RECEIVER EQUALIZATION ............................................................................................................. 20  5.1.4  TRANSMITTER SWING...................................................................................................................... 20  5.1.5  DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS .................................................................... 20  5.1.6  DRIVE AMPLITUDE .......................................................................................................................... 21  5.1.7  DRIVE DE-EMPHASIS ...................................................................................................................... 22  5.1.8  TRANSMITTER ELECTRICAL IDLE LATENCY ............................................................................... 22  5.2  DATA LINK LAYER (DLL) ...................................................................................................................... 22  5.3  TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) .............................................. 23  5.4  ROUTING .................................................................................................................................................. 23  5.5  TC/VC MAPPING ...................................................................................................................................... 23  5.6  QUEUE ....................................................................................................................................................... 23  5.6.1  PH ....................................................................................................................................................... 24  5.6.2  PD ....................................................................................................................................................... 24  5.6.3  NPHD ................................................................................................................................................. 24  5.6.4  CPLH .................................................................................................................................................. 24  5.6.5  CPLD .................................................................................................................................................. 24  5.7  TRANSACTION ORDERING ................................................................................................................... 24  5.8  PORT ARBITRATION .............................................................................................................................. 25  5.9  VC ARBITRATION ................................................................................................................................... 25  5.10  FLOW CONTROL ..................................................................................................................................... 26  5.11  TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) ............................................. 26  5.12  ACCESS CONTROLS SERVICE .............................................................................................................. 26  6  EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS ............................................................................. 27  6.1  EEPROM INTERFACE ............................................................................................................................. 27  6.1.1  AUTO MODE EERPOM ACCESS ..................................................................................................... 27  6.1.2  EEPROM MODE AT RESET .............................................................................................................. 27  6.1.3  EEPROM SPACE ADDRESS MAP .................................................................................................... 27  6.1.4  MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS .......................................... 30  6.2  SMBUS INTERFACE ................................................................................................................................. 42  6.2.1  SMBUS WRITE ................................................................................................................................... 43  6.2.2  SMBUS READ..................................................................................................................................... 44  6.3  I2C SLAVE INTERFACE ........................................................................................................................... 45  PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 4 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV 6.3.1  6.3.2  7  I2C REGISTER WRITE ACCESS ........................................................................................................ 46  I2C REGISTER READ ACCESS .......................................................................................................... 48  REGISTER DESCRIPTION ........................................................................................................................................ 51  7.1  REGISTER TYPES .................................................................................................................................... 51  7.2  TRANSPARENT MODE CONFIGURATION REGISTERS .................................................................... 51  7.2.1  VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 53  7.2.2  DEVICE ID REGISTER – OFFSET 00h ............................................................................................. 54  7.2.3  COMMAND REGISTER – OFFSET 04h ............................................................................................ 54  7.2.4  PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................. 54  7.2.5  REVISION ID REGISTER – OFFSET 08h ......................................................................................... 55  7.2.6  CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 55  7.2.7  CACHE LINE REGISTER – OFFSET 0Ch ......................................................................................... 55  7.2.8  PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 56  7.2.9  HEADER TYPE REGISTER – OFFSET 0Ch...................................................................................... 56  7.2.10  PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 56  7.2.11  SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 56  7.2.12  SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 56  7.2.13  SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 56  7.2.14  I/O BASE ADDRESS REGISTER – OFFSET 1Ch .............................................................................. 56  7.2.15  I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ............................................................................. 57  7.2.16  SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 57  7.2.17  MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 57  7.2.18  MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 58  7.2.19  PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 58  7.2.20  PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h .................................... 58  7.2.21  PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 58  7.2.22  PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 59  7.2.23  I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ................................................... 59  7.2.24  I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.................................................. 59  7.2.25  CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 59  7.2.26  INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................. 59  7.2.27  INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 59  7.2.28  BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 59  7.2.29  POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h ................................................ 60  7.2.30  POWER MANAGEMENT DATA REGISTER – OFFSET 44h ............................................................ 61  7.2.31  PPB SUPPORT EXTENSIONS – OFFSET 44h .................................................................................. 61  7.2.32  DATA REGISTER – OFFSET 44h ...................................................................................................... 61  7.2.33  MSI CAPABILITY REGISTER – OFFSET 4Ch .................................................................................. 62    MESSAGE CONTROL REGISTER – OFFSET 4Ch ................................................................................... 62  7.2.34 .................................................................................................................................................................. 62    MESSAGE ADDRESS REGISTER – OFFSET 50h..................................................................................... 62  7.2.35 .................................................................................................................................................................. 62  7.2.36  MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h ............................................................... 62  7.2.37  MESSAGE DATA REGISTER – OFFSET 58h.................................................................................... 62  7.2.38  VENDOR SPECIFIC CAPABILITY REGISTER – OFFSET 64h........................................................ 62  7.2.39  XPIP CSR0 – OFFSET 68h (Test Purpose Only) ............................................................................... 63  7.2.40  XPIP CSR1 – OFFSET 6Ch (Test Purpose Only)............................................................................... 63  7.2.41  REPLAY TIME-OUT COUNTER – OFFSET 70h .............................................................................. 63  7.2.42  ACKNOWLEDGE LATENCY TIMER – OFFSET 70h ....................................................................... 63  7.2.43  SWITCH OPERATION MODE – OFFSET 74h (Upstream Port) ...................................................... 64  7.2.44  SWITCH OPERATION MODE – OFFSET 74h (Downstream Port) .................................................. 65  7.2.45  XPIP_CSR2 – OFFSET 78h ............................................................................................................... 65  7.2.46  PHY PARAMETER 1 – OFFSET 78h (Upstream Port Only) ............................................................. 65  7.2.47  PHY PARAMETER 2 – OFFSET 7Ch ................................................................................................ 65  PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 5 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV 7.2.48  7.2.49  7.2.50  7.2.51  7.2.52  7.2.53  7.2.54  7.2.55  7.2.56  7.2.57  7.2.58  7.2.59  7.2.60  7.2.61  7.2.62  7.2.63  7.2.64  7.2.65  7.2.66  7.2.67  7.2.68  7.2.69  7.2.70  7.2.71  7.2.72  7.2.73  7.2.74  7.2.75  7.2.76  7.2.77  7.2.78  7.2.79  7.2.80  7.2.81  7.2.82  7.2.83  7.2.84  7.2.85  7.2.86  7.2.87  7.2.88  7.2.89  7.2.90  7.2.91  7.2.92  7.2.93  7.2.94  7.2.95  7.2.96  7.2.97  7.2.98  7.2.99  7.2.100  7.2.101  7.2.102  XPIP_CSR3 – OFFSET 80h ............................................................................................................... 66  XPIP_CSR4 – OFFSET 84h ............................................................................................................... 66  XPIP_CSR5 – OFFSET 88h ............................................................................................................... 66  TL_CSR0 – OFFSET 8Ch ................................................................................................................... 67  PHY PARAMETER 3 – OFFSET 90h ................................................................................................. 68  PHY PARAMETER 4 - OFFSET 94h .................................................................................................. 68  OPERATION MODE –OFFSET 98h .................................................................................................. 68  LTSSM DEBUG CONTROL REGISTER – OFFSET 9Ch .................................................................. 68  LTSSM DEBUG DATA OUTPUT REGSITER – OFFSET ACh ......................................................... 69  SSID/SSVID CAPABILITY REGISTER – OFFSET B0h ..................................................................... 69  SUBSYSTEM ID REGISTER – OFFSET B4h ..................................................................................... 69  GPIO CONTROL REGISTER – OFFSET B8h (Upstream Port Only) ............................................... 69  EEPROM CONTROL REGISTER – OFFSET BCh (Upstream Port Only) ........................................ 71  EEPROM ADDRESS REGISTER – OFFSET BCh (Upstream Port Only) ......................................... 71  EEPROM DATA REGISTER – OFFSET BCh (Upstream Port Only) ................................................ 72  PCI EXPRESS CAPABILITY REGISTER – OFFSET C0h ................................................................. 72  DEVICE CAPABILITIES REGISTER – OFFSET C4h ....................................................................... 72  DEVICE CONTROL REGISTER – OFFSET C8h .............................................................................. 73  DEVICE STATUS REGISTER – OFFSET C8h................................................................................... 74  LINK CAPABILITIES REGISTER – OFFSET CCh ............................................................................ 74  LINK CONTROL REGISTER – OFFSET D0h ................................................................................... 75  LINK STATUS REGISTER – OFFSET D0h ........................................................................................ 76  SLOT CAPABILITIES REGISTER – OFFSET D4h (Downstream Port Only) ................................... 77  SLOT CONTROL REGISTER – OFFSET D8h (Downstream Port Only) .......................................... 78  SLOT STATUS REGISTER – OFFSET D8h (Downstream Port Only).............................................. 79  DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h .................................................................... 79  DEVICE CONTROL REGISTER 2 – OFFSET E8h............................................................................ 79  DEVIDE STATUS REGISTER 2 – OFFSET E8h................................................................................ 80  LINK CAPABILITIES REGISTER 2 – OFFSET ECh ......................................................................... 80  LINK CONTROL REGISTER 2 – OFFSET F0h ................................................................................. 80  LINK STATUS REGISTER 2 – OFFSET F0h ..................................................................................... 80  SLOT CAPABILITIES REGISTER 2 – OFFSET F4h ......................................................................... 80  SLOT CONTORL REGISTER 2 – OFFSET F8h ................................................................................ 80  SLOT STATUS REGISTER 2 – OFFSET F8h..................................................................................... 81  PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER – OFFSET 100h ...... 81  UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 81  UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 82  UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................. 83  CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ...................................................... 84  CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ......................................................... 84  ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ......................... 84  HEADER LOG REGISTER – OFFSET From 11Ch to 128h .............................................................. 85  PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER – OFFSET 140h ............................ 85  PORT VC CAPABILITY REGISTER 1 – OFFSET 144h .................................................................... 85  PORT VC CAPABILITY REGISTER 2 – OFFSET 148h .................................................................... 86  PORT VC CONTROL REGISTER – OFFSET 14Ch........................................................................... 86  PORT VC STATUS REGISTER – OFFSET 14Ch ............................................................................... 86  VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h ........................................................ 86  VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h ........................................................... 87  VC RESOURCE STATUS REGISTER (0) – OFFSET 158h................................................................ 87  VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch ....................................................... 88  VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h ........................................................... 88  VC RESOURCE STATUS REGISTER (1) – OFFSET 164h............................................................ 89  VC ARBITRATION TABLE REGISTER – OFFSET 170h............................................................... 89  PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h ....................... 89  PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 6 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV 7.2.103  7.2.104  7.2.105  7.2.106  7.2.107  7.2.108  7.2.109  7.2.110  7.2.111  7.2.112  7.2.113  7.2.114  7.2.115  7.2.116  7.2.117  7.2.118  7.2.119  7.2.120  7.2.121  7.2.122  7.2.123  7.2.124  7.2.125  7.2.126  7.2.127  7.2.128  7.2.129  7.2.130  7.2.131  7.2.132  7.2.133  7.2.134  7.2.135  7.2.136  7.2.137  7.2.138  PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER – OFFSET 20Ch ..................... 90  DATA SELECT REGISTER – OFFSET 210h ................................................................................. 90  POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................... 90  POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................... 91  ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only) ................. 91  ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only) .................................... 91  EGRESS CONTROL VECTOR – OFFSET 228h (Downstream Port Only) ................................... 92  LTR EXTENDED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only) ...................... 92  MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) .............................. 93  MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) ....................... 93  LI PM SUBSTATES EXTENDED CAPABILITY HEADER – OFFSET 240h ................................. 93  L1 PM SUBSTATES CAPABILITY REGISTER – OFFSET 244h ................................................... 93  L1 PM SUBSTATES CONTROL 1 REGISTER – OFFSET 248h .................................................... 94  L1 PM SUBSTATES CONTROL 2 REGISTER – OFFSET 24Ch ................................................... 94  DPC EXTENDED CAPABILITY HEADER – OFFSET 250h (Downstream Port Only) ................ 94  DPC CAPABILITY REGISTER – OFFSET 254h (Downstream Port Only) ................................... 94  DPC CONTROL REGISTER – OFFSET 254h (Downstream Port Only)....................................... 94  DPC STATUS REGISTER – OFFSET 258h (Downstream Port Only) ........................................... 95  DPC ERROR SOURCE ID REGISTER – OFFSET 258h (Downstream Port Only) ...................... 95  PTM EXTENDED CAPABILITY HEADER REGISTER – OFFSET 260h (Upstream Port Only) .. 96  PTM CAPABILITY REGISTER – OFFSET 264h (Upstream Port Only) ....................................... 96  PTM CONTROL REGISTER – OFFSET 268h (Upstream Port Only) ........................................... 96  MISC CONTROL 0 REGISTER – OFFSET 300h ........................................................................... 96  MISC CONTROL 1 REGISTER – OFFSET 304h ........................................................................... 97  MISC CONTROL 2 REGISTER – OFFSET 308h ........................................................................... 97  MISC CONTROL 3 REGISTER – OFFSET 30Ch .......................................................................... 97  MISC CONTROL 4 REGISTER – OFFSET 310h ........................................................................... 97  PHY/DLL/TL ERROR COUNTER – OFFSET 318h ....................................................................... 97  MEMORY ECC ERROR MASK AND STATUS – OFFSET 31Ch ................................................... 98  PORT PHYSICAL LAYER COMMAND AND STATUS REGISTER – OFFSET 320h .................... 98  PORT DISABLE/QUIET/TEST PATTERN RATE REGISTER – OFFSET 324h............................. 99  CSR_LED0 – OFFSET 328h......................................................................................................... 100  CSR_LED1 – OFFSET 32Ch ........................................................................................................ 100  LTSSM_CSR – OFFSET 33Ch ...................................................................................................... 100  MAC_CSR – OFFSET 340h .......................................................................................................... 100  TL_CSR1 – OFFSET 344h............................................................................................................ 101  8  CLOCK SCHEME ...................................................................................................................................................... 102  9  IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................................................. 104  9.1  9.2  9.3  9.4  9.5  INSTRUCTION REGISTER .................................................................................................................... 104  BYPASS REGISTER ............................................................................................................................... 104  DEVICE ID REGISTER ........................................................................................................................... 104  BOUNDARY SCAN REGISTER............................................................................................................. 105  JTAG BOUNDARY SCAN REGISTER ORDER .................................................................................... 105  10  POWER MANAGEMENT ......................................................................................................................................... 107  11  POWER SEQUENCE ................................................................................................................................................. 108  12  ELECTRICAL AND TIMING SPECIFICATIONS ................................................................................................ 109  12.1  12.2  12.3  12.4  ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 109  DC SPECIFICATIONS ............................................................................................................................ 109  AC SPECIFICATIONS ............................................................................................................................ 110  POWER CONSUMPTION ....................................................................................................................... 111  PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 7 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV 12.5  OPERATING AMBIENT TEMPERATURE ........................................................................................... 111  13  THERMAL DATA ...................................................................................................................................................... 112  14  PACKAGE INFORMATION..................................................................................................................................... 113  15  ORDERING INFORMATION................................................................................................................................... 115  PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 8 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV TABLE OF FIGURES FIGURE 5-1 DRIVER OUTPUT WAVEFORM ................................................................................................................... 21  FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X2G404EV........................................................... 42  FIGURE 6-2 SMBUS WRITE COMMAND FORMAT, TO WRITE TO A PI7C9X2G404EV REGISTER (PEC DISABLE)........ 43  FIGURE 6-3 SMBUS READ COMMAND FORMAT, TO READ THAT RETURNS CFG REGISTER VALUE (PEC DISABLED) . 44  FIGURE 6-4 STANDARD DEVICES TO I2C BUS CONNECTION BLOCK DIAGRAM ............................................................ 45  FIGURE 6-5 I2C WRITE PACKET ................................................................................................................................... 47  FIGURE 6-6 I2C REGISTER WRITE ACCESS EXAMPLE .................................................................................................. 47  FIGURE 6-7 I2C WRITE COMMAND PACKET EXAMPLE ................................................................................................ 48  FIGURE 6-8 I2C READ COMMAND PACKET .................................................................................................................. 49  FIGURE 6-9 I2C REGISTER READ ACCESS EXAMPLE .................................................................................................... 49  FIGURE 6-10 I2C READ COMMAND PACKET ................................................................................................................ 50  FIGURE 11-1 INITIAL POWER-UP SEQUENCE ............................................................................................................. 108  FIGURE 14-1 PACKAGE OUTLINE DRAWING .............................................................................................................. 113  FIGURE 14-2 PACKAGE BOTTOM VIEW...................................................................................................................... 114  FIGURE 14-3 PART MARKING .................................................................................................................................... 114  LIST OF TABLES TABLE 5-1 RECEIVER DETECTION THRESHOLD SETTINGS ........................................................................................... 19  TABLE 5-2 RECEIVER SIGNAL DETECT THRESHOLD .................................................................................................... 20  TABLE 5-3 RECEIVER EQUALIZATION SETTINGS ......................................................................................................... 20  TABLE 5-4 TRANSMITTER SWING SETTINGS ................................................................................................................ 20  TABLE 5-5 DRIVE AMPLITUDE BASE LEVEL REGISTERS.............................................................................................. 21  TABLE 5-6 DRIVE AMPLITUDE BASE LEVEL SETTINGS................................................................................................ 21  TABLE 5-7 DRIVE DE-EMPHASIS BASE LEVEL REGISTER ............................................................................................ 22  TABLE 5-8 DRIVE DE-EMPHASIS BASE LEVEL SETTINGS ............................................................................................ 22  TABLE 5-9 SUMMARY OF PCI EXPRESS ORDERING RULES .......................................................................................... 25  TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION .................................................................................................... 42  TABLE 6-2 BYTES FOR SMBUS WRITE ........................................................................................................................ 43  TABLE 6-3 SAMPLE SMBUS WRITE BYTE SEQUENCE ................................................................................................. 43  TABLE 6-4 BYTES FOR SMBUS READ .......................................................................................................................... 44  TABLE 6-5 SMBUS BLOCK WRITE PORTION ............................................................................................................... 44  TABLE 6-6 I2C ADDRESS PIN CONFIGURATION ............................................................................................................ 45  TABLE 6-7 I2C REGISTER WRITE ACCESS .................................................................................................................... 46  TABLE 6-8 I2C COMMAND FORMAT FOR WRITE ACCESS............................................................................................. 46  TABLE 6-9 I2C COMMAND FORMAT FOR READ ACCESS .............................................................................................. 48  TABLE 7-1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION .................................................................................... 89  TABLE 7-2 TABLE ENTRY SIZE IN 4 BITS ..................................................................................................................... 90  TABLE 8-1 AC SWITCHING CHARACTERISTICS .......................................................................................................... 102  TABLE 8-2 CONNECTION MAP FOR REFCLKO_P/N[3:0] ......................................................................................... 102  TABLE 8-3 OUTPUT CONTROL FOR REFCLKO_P/N[3:0] ......................................................................................... 102  TABLE 9-1 INSTRUCTION REGISTER CODES ............................................................................................................... 104  TABLE 9-2 JTAG DEVICE ID REGISTER .................................................................................................................... 104  TABLE 9-3 JTAG BOUNDARY SCAN REGISTER DEFINITION ...................................................................................... 105  TABLE 12-1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 109  TABLE 12-2 DC ELECTRICAL CHARACTERISTICS ...................................................................................................... 109  TABLE 12-3 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (5.0 GBPS) CHARACTERISTICS110  TABLE 12-4 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (2.5 GBPS) CHARACTERISTICS110  TABLE 12-5 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (5.0 GBPS) CHARACTERISTICS ......... 111  TABLE 12-6 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (2.5 GBPS) CHARACTERISTICS ......... 111  TABLE 12-7 POWER CONSUMPTION ........................................................................................................................... 111  TABLE 12-8 OPERATING AMBIENT TEMPERATURE .................................................................................................... 111  TABLE 13-1 THERMAL DATA..................................................................................................................................... 112  PI7C9X2G404EV Document Number DS39929 Rev 8-2 Page 9 of 115 December 2020 www.diodes.com © Diodes Incorporated PI7C9X2G404EV 1 FEATURES                                 4-lane PCI Express Gen 2 Switch with 4 PCI Express ports Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching Peer-to-peer switching between any two downstream ports 150 ns typical latency for packet routed through Switch without blocking Integrated reference clock for downstream ports Strapped pins configurable with optional EEPROM or SMBus SMBus interface support Compliant with System Management (SM) Bus, Version 1.0 Compliant with PCI Express Base Specification Revision 2.1 Compliant with PCI Express CEM Specification Revision 2.0 Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2 Compliant with Advanced Configuration Power Interface (ACPI) Specification Reliability, Availability and Serviceability Supports Data Poisoning and End-to-End CRC Advanced Error Reporting and Logging IEEE 1149.1 JTAG interface support Advanced Power Saving Empty downstream ports are set to idle state to minimize power consumption Link Power Management Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states Supports PCI-PM L1.1 and ASPM L1.1 of L1 PM Sub-state Active state power management for L0s and L1 states Device State Power Management Supports D0, D3Hot and D3Cold device power states 3.3V Aux Power support in D3Cold power state Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR Extended Virtual Channel capability Two Virtual Channels (VC) and Eight Traffic Class (TC) support Disabled VCs’ buffer is assigned to enabled VCs for resource sharing Independent TC/VC mapping for each port Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable Weighted RR Supports Isochronous Traffic Isochronous traffic class mapped to VC1 only Strict time based credit policing Supports up to 512-byte maximum payload size Programmable driver current and de-emphasis level at each individual port Support Access Control Service (ACS) for peer-to-peer traffic Support Address Translation (AT) packet for SR-IOV application Support OBFF and LTR Support Surprise Hot-Plug (DPC) Support End-to-End Data Protection with ECC Low Power Dissipation: 300 mW typical in L0 normal mode Industrial Temperature Range -40o to 85oC Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ 136-pin aQFN 10mm x 10mm package Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain