ZABG6002JB20TC

NOT RECOMMENDED FOR NEW DESIGN USE ZABG6003 ZABG6002 LOW POWER 6 STAGE FET LNA AND MIXER BIAS CONTROLLER Summary The ZABG6002 is a programmable low-power depletion mode FET bias and mixer controller intended primarily for satellite Low Noise Blocks (LNBs). Designed to provide system flexibility the ZABG6002 can be programmed to bias six low noise amplifier (LNA) stages or four LNA and two active mixer stages, allowing the ZABG6002 to be used in several system designs. Combining advanced IC process and packaging techniques, the ZABG6002 operates with minimal current over a wide supply voltage. The small package and reduced component count minimizes the PCB area whilst enhancing overall LNB reliability. • • • G4 Vcc D4 D1 G5 D3 D6 G3 G6 RcalM Rcal1 FETs Protected Against Overstress During Powerup and Powerdown. Internal negative Supply Generator Allowing Single Supply Operation (Available for External use) Low Quiescent Supply Current, 1.6mA Typical Low External Component Count Csub Rcal2 • D5 G2 Csub • • D2 Cnb2 • QFN2044 Cnb1 • • Six-Stage FET Bias Controller, Two Configurable as Mixer Stages Operating Range of 3.0V to 8.0V Amplifier FET Drain Voltages set at 2.0V, Mixer Drain Voltage set at 0.25V Amplifier FET Drain Current Selectable from 0 to 15mA, Mixer Current from 0 to 7.5mA Switchable FETs for Power Management FET Drain Voltages and currents Held Stable Overtemperature and VCC Variations Gnd • Pin Assignments G1 Features QSOP20 1 D1 Vcc G1 D4 D2 G4 Applications G2 D5 • Twin LNBs D3 G5 • Quad LNBs G3 D6 • US LNBs RcalM G6 • Microwave Links • Gnd Rcal1 PMR and Cellular Telephone Systems Cnb1 Rcal2 Cnb2 Csub ZABG6002 Document number: DS32078 Rev. 2 - 3 ZXHF 5002 ZABG 6002 ZLNB 102 Right Horizontal ZABG 6002 2x2 MUX Left Vertical Twin LNB System Diagrams 1 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Device Description The ZABG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs with a minimum of external components whilst operating from a minimal voltage supply and using minimal current. The ZABG6002 has six FET bias stages that can be user programmed to provide either a two plus four arrangement of amplifier FET stages or a two plus two arrangement of amplifier FET stages along with two active mixer FET stages. Programming of the FET bias stage arrangement and the operating currents of each FET group is achieved by resistors connected to the Rcal1, Rcal2 and RcalM pins, allowing input FETs to be biased for optimum noise, amplifier FETs for optimum gain and mixer FETs (if used) for optimum conversion gain. Amplifier FETs can be operated at currents in the range 0 to 15mA and mixer FETs in the range 0.5 to 7.5mA. Drain voltages of amplifier stages are set at 2.0V and mixer stages at 0.3V. The drain supplies are current limited to approximately 5% above the operating currents set by their associated Rcal resistors. As an additional feature the Rcal pins can also be used as logic inputs to disable pairs of FETs as part of a power management scheme or simply an alternative to LNA switching. Driven to a logic high (>3.0V), the inputs disable their associated FET bias stages by switching gate feeds to -2.5V and drain feeds open circuit. Depletion mode FETs require a negative voltage bias supply when operated in grounded source circuits. The ZABG6002 includes an integrated low noise switched capacitor DC-DC converter generating a regulated output of -2.5V to allow single supply operation. To aid efficiency and 3.3V systems the ZABG6002 has been design to used with supply rails of 3.3V to 8V It is possible to use less than the devices full complement of FET bias controls, unused drain and gate connections can be left open circuit without affecting operation of the remaining bias circuits. To protect the external FETs the circuits have been designed to ensure that, under any conditions including power up/down transients, the gate drive from the bias circuits cannot exceed -3V. Additionally each stage has its own individual current limiter. Furthermore if the negative rail experiences a fault condition, such as overload or short circuit, the drain supply to the FETs will shut down avoiding excessive current flow. The ZABG6002 is available in the 20 pin 4mm × 4mm QFN or QSOP20 package. Device operating temperature is -40°C to 85°C to suit a wide range of environmental conditions. ZABG6002 Document number: DS32078 Rev. 2 - 3 2 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Maximum Ratings Parameter Supply Voltage Supply Current Power Dissipation Operating Temperature Range Junction Temperature Storage Temperature Range Rating -0.6 to +10 100 600 -40 to +85 125 -40 to 150 Unit V mA mW °C °C °C Electrical Characteristics Measured at TAMB = 25°C, VCC = 3.3V (Note 1), RCAL1 = RCAL2 = 36K (setting ID1/2/4/5 to 10mA), RCALM = 68K (setting ID3/6 to 5mA) unless otherwise stated Parameter Operating Voltage Range Supply Current Min. Typ. Max. — Conditions VCC Symbol 3.0 — 8.0 Unit V ID1-6 = 0 ICC — 1.6 4.0 mA ID1-6 = 10mA, no RCALM ICC(L) — 62 64 mA ICSUB = 0 VCSUB -3.0 -2.65 -2.0 V ICSUB = -200uA VCSUB(L) — -2.55 -2.0 V — FOSC 150 260 600 kHz Current Range — IG -100 — +500 µA Voltage Low ID = 12mA, IG = -10uA VG(L) -3.0 -2.5 -2.0 V ID = 8mA, IG = 0 VG(H) 0 0.7 1.0 V ID = 0, IG = -10µA, VRCAL1-2 = 3.0V VG(DIS) -3.0 -2.5 -2.0 V Current Range — IG -100 — +500 µA Voltage Low ID = 6mA, IG = -10µA VG(L) -3.0 -2.5 -2.0 V Voltage High ID = 4mA, IG = 0 VG(H) 0 0.7 1.0 V ID = 0, IG = -10µA, VRCAL2 = VRCALM 3.0V VG(DIS) -3.0 -2.5 -2.0 V Current Range — ID 0 — 15 mA Current Operating Standard Application Circuit ID(OP) 8 10 12 mA Current Disabled VD = 0, VRCAL = 3.0V ID(DIS) — — 10 µA Voltage Operating ID = 10mA VD(OP) 1.8 2.0 2.2 V Substrate Voltage Oscillator Frequency Gate Characteristics Gate (G1 to G6, resistor RCALM not present) Voltage High (*1) Voltage Disabled Gate (G3 and G6, resistor RCALM present) (*1) Voltage Disabled Drain Characteristics Drain (D1 to D6, resistor RCALM not present) (*1) ZABG6002 Document number: DS32078 Rev. 2 - 3 3 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Electrical Characteristics (Cont.) Measured at TAMB = 25°C, VCC = 3.3V (Note 1), RCAL1 = RCAL2 = 36K (setting ID1/2/4/5 to 10mA), RCALM = 68K (setting ID3/6 to 5mA) unless otherwise stated Parameter Drain Characteristics Conditions Symbol Min. Typ. Max. Unit 0.5 — 7.5 mA Drain (D3 and D6, resistor RCALM present) Current Range — IDM Current Operating Standard Application Circuit IDM(OP) 4 5 6 mA Current Disabled (*1) VD = 0, VRCAL = 3.0V, RCALM not present IDM(DIS) — — 10 µA Voltage Operating ID = 5mA VDM(OP) 0.25 0.3 0.35 V — VRCAL(DIS) 1.8 2.7 3.0 V 1.7 10 µA RCAL(1 and 2) Disable Threshold (*1) Input Current VRCAL = 3.0V IRCAL(DIS) Disable Threshold (*1) — RCALM(DIS) 1.5M 3.3M 5.0M Ω RCALM Range — RCALM 39k — 390k Ω RCALM Voltage and Temperature Dependence (RCALM not present) delta ID vs VCC VCC = 3.3V to 8.0V dID/dVCC — 1.2 — %/V delta ID vs TOP TOP = -40°C to +85°C dID/dTOP — 0.05 — %/°C delta VD vs VCC VCC = 3.3V to 8.0V dVD/dVCC — 0.05 — %/V delta VD vs TOP TOP = -40°C to +85°C dVD/dTOP — 50 — ppm/°C Drain Voltage CGATE-GND = 10nF, CDRAIN-GND = 10nF VD(NOISE) — — 0.02 Vpk-pk Gate Voltage CGATE-GND = 10nF, CDRAIN-GND = 10nF VG(NOISE) — — 0.005 Vpk-pk Output Noise Notes: 1. To disable FET stages 3 and 6, pin RCAL2 must be set to 3V or above and pin RCALM should be open circuit. See applications section for further information. 2. The characteristics are measured using up to three external reference resistors, RCAL1, RCAL2 and RCALM, wired from pins RCAL1/2/M to ground. Resistor RCAL1 sets the drain current of FETs 1 and 4. If RCALM is not present, resistor RCAL2 sets the drain currents of FETs 2, 3, 5 and 6. If RCALM is present, resistor RCAL2 sets the drain currents of FETs 2 and 5 and RCALM sets the drain currents of FETs 3 and 6. 3. The negative bias voltages are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB of value 47nF are required for this purpose. 4. The QFN2044 exposed pad must either be connected to Csub or left open circuit. 5. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production. 6. ESD sensitive, handling precautions are recommended. ZABG6002 Document number: DS32078 Rev. 2 - 3 4 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Typical Characteristics Measured at TAMB = 25°C, VCC = 3.3V, RCAL1 = RCAL2 = 36K (setting ID to 10mA), RCALM = 68K (setting ID3/6 to 5mA) unless otherwise stated ZABG6002 Drain Voltage (D1 - D6) vs Temperature ZABG6002 Drain Current (D1 - D6) vs Temperature 2.3 20 18 2.2 16 Drain Current (mA) Drain Voltage (V) 14 2.1 2 1.9 12 10 8 6 4 1.8 2 1.7 0 -40 -20 0 20 40 60 80 -40 -20 0 Temperature (°C) 40 60 80 ZABG6002 Drain Current (D3 & D6 only) vs Temperature ZABG6002 Drain Voltage (D3 & D6 only) vs Temperature 0.5 10 0.4 8 Drain Current (mA) Drain Voltage (V) 20 Temperature (°C) 0.3 0.2 6 4 2 0.1 0 0 -40 -20 0 20 40 60 -40 80 -20 0 20 40 60 80 Temperature (°C) Temperature (°C) ZABG6002 Substrate Voltage vs Substrate Current -2 Substrate Voltage (V) -2.2 -2.4 -2.6 -2.8 -3 0 50 100 150 200 250 Substrate Current (uA) ZABG6002 Document number: DS32078 Rev. 2 - 3 5 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Typical Characteristics (continued) Measured at TAMB = 25°C, VCC = 3.3V, RCAL1 = RCAL2 = 36K (setting ID to 10mA), RCALM = 68K (setting ID3/6 to 5mA) unless otherwise stated ZABG6002 Drain Voltage vs Drain Current (D1-D6) ZABG6002 Drain Current vs RCAL 2.2 15 Drain Current (mA) Drain Voltage (V) 2.1 2 10 5 1.9 1.8 0 0 5 10 15 10 Drain Current (mA) 100 1000 RCAL (k) ZABG6002 Drain Voltage vs Drain Current (D3 & D6 only) ZABG6002 Drain Current vs RCALM 0.5 10 Drain Current (mA) Drain Voltage (V) 0.4 0.3 0.2 5 0.1 0 0 0 5 10 Drain Current (mA) ZABG6002 Document number: DS32078 Rev. 2 - 3 10 100 1000 RCAL (k) 6 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Application Information The ZABG6002 is a flexible device and can be set up in a number of ways. 1. 6 LNA stages to provide standard bias to the GaAs or HEMT FETs 2. 4 LNA stages to provide standard bias to the GaAs or HEMT FETs plus two active mixer stages 3. Power down FET groups for LNA switching or power saving. The truth table below shows the function of these features. Rcal1 Gnd Gnd Gnd Gnd 3V 3V 3V 3V Rcal2 Gnd Gnd 3V 3V Gnd Gnd 3V 3V RcalM Open Gnd Open Gnd Open Gnd Open Gnd FET Stage 2nd LNA Stages Bias 2 Bias 5 On On On On Off Off Off Off On On On On Off Off Off Off 1st LNA Stages Rcal Pin Resistor Termination Bias 1 On On On On Off Off Off Off Bias 4 On On On On Off Off Off Off 3rd LNA/Mixer Stages Bias 3 Bias 6 On On Mixer Mixer Off Off Mixer Mixer On On Mixer Mixer Off Off Mixer Mixer ZABG6002 in 6 LNA Mode L* C* C1 10nF JF2 Vcc G4 D4 Vcc D1 G1 Below is a partial applications circuit for the ZABG6002 showing all external components needed for biasing one of the six FET stages available as a normal LNA bias. Each bias stage is provided with a gate and drain pin. The drain pin provides a regulated 2.0V supply that includes a drain current monitor. The drain current taken by the external FET is compared with a user selected level, generating a signal that adjusts the gate voltage of the FET to obtain the required drain current. If for any reason, an attempt is made to draw more than the user set drain current from the drain pin, the drain voltage will be reduced to ensure excess current is not taken. The gate pin drivers are also current limited. D2 D5 G2 G5 D3 D6 ZABG6002 G3 G6 RcalM Rcal1 C* CNB 47nF Rcal2 RCAL2 36k CSUB 47nF * Stripline Elements Csub Cnb2 Cnb1 C2 10nF Gnd L* RCAL1 36k The bias stages are split up into two groups, with the drain current of each group set by an external RCAL resistor. RCAL1 sets the drain currents of stages 1 and 4, whilst RCAL2 sets the drain currents of stages 2, 3, 5, and 6. This allows the optimization of drain currents for differing tasks such as input stages where noise can be critical and later amplifier stages where gain may be more important. A graph showing the relationship between the value of RCAL and ID is provided in the Typical Characteristics section of this datasheet. To ensure that the mixer function is disabled the RCALM pin should be left open circuit. ZABG6002 Document number: DS32078 Rev. 2 - 3 7 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Application Information (continued) ZABG6002 in 4 LNA and 2 Active Mixer Mode L* C* C1 10nF JF2 G4 Vcc D4 Vcc D1 G1 Below is a partial applications circuit for the ZABG6002 showing all external components needed for biasing one of the four FET stages available for LNA bias and one of the two mixer bias stages. Each LNA bias stage is provided with a gate and drain pin. The drain pin provides a regulated 2.0V supply that includes a drain current monitor. Each mixer bias stage is provided with a gate and drain pin. The drain pin provides a regulated 0.3V supply that includes a drain current monitor but optimized to the requirements of an active mixer. The drain current taken by the external FET (LNA and Mixer) is compared with a user selected level, generating a signal that adjusts the gate voltage of the FET to obtain the required drain current. If for any reason, an attempt is made to draw more than the user set drain current from the drain pin, the drain voltage will be reduced to ensure excess current is not taken. The gate pin drivers are also current limited. L* D2 D5 G2 G5 D3 D6 ZABG6002 G3 G6 RcalM Rcal1 C3 10nF C* JFM L* Rc al2 Cs ub Cnb2 Cnb1 C2 10nF Gnd L* C* VLO CNB 47nF RCALM 68k C4 10nF C* RCAL2 36k CSUB 47nF RCAL1 36k * Stripline Elements The bias stages are split up into three groups, with the drain current of each group set by an external RCAL resistor. RCAL1 sets the LNA drain currents of stages 1 and 4 and RCAL2 sets the drain currents of LNA stages 2 and 5. RCALM sets the mixer drain currents of stages 3 and 6. This allows the optimization of drain currents for differing tasks such as input stages where noise can be critical and later amplifier stages where gain may be more important. A graph showing the relationship between the value of RCAL and ID is provided in the Typical Characteristics section of this datasheet. ZABG6002 Document number: DS32078 Rev. 2 - 3 8 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 General Operation In both modes the RCAL 1 and RCAL 2 pins can also be used as logic inputs. If set to a logic high state (>3.0V), the associated FET bias stages programmed for LNA use (2V drains) are disabled by driving gate pins to -2,5V and switching drain pins open-circuit. This feature can be used as part of a power management system that turns off any unwanted stages in a multi input receiver. The ZABG6002 includes a switched capacitor DC-DC converter that is used to generate the negative supply required to bias depletion mode FETs used in common source circuit configuration as shown above. This converter uses two external capacitors, CNB the charge transfer capacitor and CSUB the output reservoir capacitor. The circuit provides a regulated -2.5V supply both for gate driver use and for external use if required (for extra discrete bias stages, mixer bias, local oscillator bias etc.). The -2.5V supply is available from the CSUB pin. If any bias stages are not required, their gate and drain pins may be left open circuit. If all bias stages associated with an RCAL resistor are not required, then this resistor may be omitted. It must be noted that the exposed pad of the QFN package must be either left floating or connected to Csub. Ordering Information Device ZABG6002JB20TC ZABG6002Q20TC Package QFN2044 QSOP20 Reel Size (inches) 13 13 Tape Width (mm) 12 16 Quantity per Reel 3000 2500 Marking Information QFN2044 QSOP20 Pin 1 Part Name Date Code Year/Week ZABG6002 Document number: DS32078 Rev. 2 - 3 ZABG 6002 YYWW Part Name Date Code ZABG6002 YYWW Pin 1 9 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. QSOP20 DIM A A1 A2 D ZD b c e E E1 L θ h ZABG6002 Document number: DS32078 Rev. 2 - 3 Millimeters MIN 1.35 0.10 1.25 8.56 Inches MAX 1.75 0.25 1.50 8.74 MIN 0.053 0.004 0.049 0.337 0.30 0.25 0.008 0.007 6.20 3.99 1.27 8° 0.50 0.228 0.150 0.016 0° 0.010 0.058 REF 0.20 0.18 1.47 REF 0.64 BSC 5.79 3.81 0.41 0° 0.25 MAX 0.069 0.010 0.059 0.344 0.012 0.010 0.025 BSC 10 of 12 www.diodes.com 0.244 0.157 0.050 8° 0.020 January 2019 © Diodes Incorporated ZABG6002 Package Outline Dimensions (continued) Please see http://www.diodes.com/package-outlines.html for the latest version. QFN2044 DIM D E D2 E2 A A1 A3 b L e z aaa bbb ccc Min. 3.95 3.95 2.40 2.40 0.57 0 — 0.20 0.35 — — ZABG6002 Document number: DS32078 Rev. 2 - 3 Max. 4.05 4.05 2.60 2.60 0.63 0.05 — 0.30 0.45 — — 0.25 0.10 0.10 Typ. 4.00 4.00 2.50 2.50 0.60 0.02 0.15 0.25 0.40 0.50 0.875 11 of 12 www.diodes.com January 2019 © Diodes Incorporated ZABG6002 IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. 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