PFF3000-12-069RD is a 3 kW DC/DC front-end converter that
provides a main output 12.5 VDC from -40 to -72 VDC bus voltages to
power Intermediate Bus Architectures (IBA) in high-performance and
high-reliability servers, routers, and network switches.
Features include very high efficiency, high reliability, low output voltage
noise, and excellent dynamic response to load / input changes.
•
Best-in-class, platinum equivalent efficiency
•
Input voltage range: -40 to -72 VDC
•
Up to 3 kW output power - 244 A output current
•
Hot-plug capable
•
Parallel operation with active analog current sharing
•
2 Status LEDs: DC input OK and warning / fault signaling
•
High density design: 30.5 W/in3
•
Form factor: 555 x 69 x 42 mm (21.85 x 2.72 x 1.65 in)
•
Full digital controls for improved performance
•
RoHS Compliant
•
Reverse polarity, over temperature, output overvoltage, and
overcurrent protections
•
I2C communication interface for control, programming, and monitoring
with Power Management Bus protocol
•
High Performance Servers
•
Routers
•
Switches
PFF3000-12-069RD
2
PFF
3000
Product Family Power Level
PFF Front-Ends
1
3000 W
-
12
-
Dash
V1 Output
Dash
12.5 V
069
R
D
Option Code
Blank: Standard model
Width
Airflow
Input
69 mm
R: Reversed1
D: DC
Front to Rear
PFF3000-12-069RD power supply is a fully digital controlled, highly efficient front-end converter. It incorporates state-of-the-art
technology and uses an interleaved forward converter topology with active clamp and synchronous rectification to reduce
component stresses, thus providing increased system reliability and very high efficiency.
With a wide DC input voltage range and minimal linear output power derating with ambient temperature, PFF3000-12-069RD
maximizes power availability in demanding server, switch, and router applications. The frontend is fan cooled and ideally suited
for server integration with a matching airflow path.
Active OR-ing devices on the main output ensure no reverse load current and render the supply ideally suited for operation in
redundant power systems. The standby output (12V/2A) provides power to external power distribution and management
controllers. Its protection with an active OR-ing device provides for maximum reliability.
Status information is provided with two front-panel LEDs. In addition, the power supply can be controlled via I2C bus. This allows
full monitoring of the supply, including input and output voltage, current, power, and inside temperatures. Cooling is managed by
a fan controlled by the DSP controller. The fan speed is adjusted automatically depending on the actual power demand and supply
temperature and can be overridden through the I2C bus.
Figure 1. PFF3000-12-0069RD Block Diagram
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Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-term reliability,
and cause permanent damage to the supply.
PARAMETER
CONDITIONS / DESCRIPTION
Vi maxc
Continuous
Maximum Input
MIN
MAX
UNITS
-75
VDC
General Condition: TA = 0… 45 °C unless otherwise noted.
PARAMETER
DESCRIPTION / CONDITION
VI start
Minimum operating input voltage
Communication available, DSP running
VI nom
Nominal input voltage
VI
Input voltage
Normal operation (from VI min to VI max)
II
Input current
II pk
Inrush current limitation
VI on_uv
Turn-on input voltage low
Ramping up
VI off_uV
Turn-off input voltage low
Ramping down
VI on_ov
Turn-on input voltage high
Ramping down
VI off_oV
Turn-off input voltage high
Ramping up
-72.0
VI nom, 0.2 ∙ I1 nom, V1 nom, TA = 25 °C
90.0
93.8
%
VI nom, 0.5 ∙ I1 nom, V1 nom, TA = 25 °C
94.0
95
%
VI nom,
91.0
93
%
Η
Efficiency (fan power not included)
MIN
NOM
MAX
UNIT
35
VDC
53
VDC
-72
VDC
VI > VI min
85
A
From Vi min to Vi max, TA = 25°C
100
A
-42.5
-43.5
VDC
-38.0
-39.5
VDC
-68.5
-69.5
VDC
-75.0
VDC
I1 nom, V1 nom, TA = 25 °C
-40
4.1 INPUT FUSE
Fast-acting 100 A input fuse in series on minus DC rail inside the PSU protects against severe defects. The fuse is not accessible
from the outside and is not therefore a serviceable part.
4.2 INRUSH CURRENT & REVERSE POLARITY PROTECTION
Internal bulk capacitors will be charged through NTC resistors connected from bulk cap minus pin to the DC rail minus, thus
limiting the inrush current. After the inrush phase, NTC resistors are then shorted with MOSFETs connected in parallel. Inrush
control is managed by the digital controller (DSP).
Parallel connected MOSFETs in series to the DC minus rail input act as a reverse polarity blocking element (Fig. 1). In case of
a short at the input voltage or input reverse polarity, these MOSFETs will open and prevent the bulk caps to be discharged via
the input. Reverse polarity control is managed by a fast-acting analog circuit.
NOTE: In order to keep max inrush current below II max, it is not recommended to repeat plug-in/-out operations within 20 s.
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4.3 INPUT UNDER-VOLTAGE
If input voltage VI is below the input under-voltage lockout threshold VI min, main output will be inhibited. Once the input voltage
returns within the normal operating voltage range, main output voltage will be enabled again and converter returns into normal
operation.
4.4 EFFICIENCY
High efficiency is achieved by using state-of-the-art silicon power devices, thus minimizing conduction and switching losses by
an optimized design and layout. Synchronous rectifiers on the output stage reduce losses in the high current output path. Fan
speed is digitally controlled in order to keep all components below critical operating temperature.
96
95
Efficiency [%]
94
93
92
91
90
Vi = 53Vdc, fan internal, standby proportional loaded
Vi =53Vdc, fan external, standby unloaded
89
Platinum
88
0
500
1000
1500
2000
2500
3000
Po [W]
Figure 2. Efficiency vs. Load Current
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General Condition: TA = 0…45 °C unless otherwise noted.
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
Main Output V1
V1 nom
V1 set
Nominal main output voltage
Main output voltage set-point
accuracy
0.5 ∙ I1 nom, TA = 25 °C
12.5
0.5 ∙ I1 nom, TA = 25 °C
-0.5
dV1 tot
Total regulation
P1 nom
Nominal main output power
VI min to VI max, 0 to 100% I1 nom,
TA min to TA max
V1 = V1 nom ± 1.0% V1 nom
I1 nom
Nominal main output current
V1 = V1 nom ± 1.0% V1 nom
-1.0
IV1 lim
IV1 ol
VDC
+0.5
% V1 nom
+1.0
% V1 nom
3000
W
244
A
See table Protection
Short time over load current
V1 = 12.3 VDC,
Ta min to Ta max, maximum duration 20 ms
(See Section 5.2 and 6)
280
A
Current limit during short time
overload V1
Main output ripple voltage
V1 nom, I1 nom, 20 MHz BW
dV1 Load
Load regulation
Vi nom, 0 – 100% I1 nom
170
mV
dV1 droop
Droop
0 – 100% I1 nom
0.7
mV/A
dV1 Line
Line regulation
VI = VI min…VI max
0
mV
dIshare
Current sharing accuracy
dV1dyn
Dynamic load regulation
Start-up time from DC input
Deviation I1 tot / N, I1 > 30% I1 nom
I1 = 10%...50% I1 nom,
I1 tot = I1 + ΔI1, ΔI1 = 50 % I1 nom,
dIo / dt = 1 A/µs,
recovery within 1% of V1 nom
V1 = 10.8 VDC
Rise time (monotonic)
V1 = 10%...90% V1 nom, 50% I1 nom
Hold-up time
0.5 ∙ I1, VI = VI nom
Capacitive loading
TA = 25 °C
IV1 ol lim
V1 pp
T1rec
tV1_Pwr_On
tV1 rise
tV1_holdup
Cload
Recovery time
See table Protection
160
mVpp
-5
+5
%
-0.6
+0.6
V
1
ms
See table on/ off signal timings
4.5
ms
2
ms
10000
µF
Standby Output VSB
VSB nom
Nominal standby output voltage
0.5 ∙ ISB nom, TA = 25 °C
VSB set
Standby output set-point accuracy
0.5 ∙ ISB nom, TA = 25 °C
dVSB tot
Total regulation
PSB nom
Nominal standby output power
Vi min to Vi max, 0 to 100% ISB nom,
TA min to TA max
VSB = VSB nom ± 0.5% VSB nom
ISB nom
Nominal standby output current
VSB = VSB nom ± 0.5% VSB nom
VSB pp
Standby output ripple voltage
VSB nom, ISB nom, 20 MHz BW
12.00
-1.0
+1.0
-1.0
+1.0
VDC
% VSB
nom
% VSB
nom
24
W
2
A
120
mVpp
IVSB lim
Current limit
tVSB lim
Over load current limit time on VSB
Time to hit hiccup when in over current
dVSB
Load regulation
0 – 100% ISB nom
220
mV
Droop
110
mV/A
Start-up time from DC input
0 – 100% ISB nom
ISB = 5%...50% ISB nom,
ISB tot = I1 + ΔI1, Δ ISB = 50 % ISB nom,
dIo / dt = 1 A/µs,
recovery within 1% of VSB nom
VSB = 90% VSB nom
Rise time (monotonic)
VSB = 10%...90% VSB nom
Hold-up time
Isb=0…2A, VI > 48V
Capacitive loading
TA = 25 °C
dVSBdyn
TSBrec
tVSB_Pwr_On
tVSB rise
tVSB_holdup
Cload
Dynamic load regulation
Recovery time
See table Protection
See table Protection
-0.6
+0.6
V
5
ms
See table on/ off signal timings
0.1
5
ms
260
1000
ms
µF
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5.1 OUTPUT VOLTAGE RIPPLE
The internal output capacitance at the power supply output (behind OR-ing element) is minimized to prevent disturbances
during hot plug. In order to provide low output ripple voltage in the application, external capacitors should be added close to
the power supply output. The setup of Figure 3 has been used to evaluate suitable capacitor types. The capacitor combinations
of Table 1 and Table 2 should be used to reduce the output ripple voltage.
The ripple voltage is measured with 20 MHz BWL, close to the external capacitors.
Figure 3. Output Ripple Test Setup
NOTE: Care must be taken when using ceramic capacitors with a total capacitance of 1 µF to 50 µF on output V1, due to their
high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects.
External Capacitor V1
2Pcs 47µF/16V/X5R/1210
1Pcs 1000µF/16V/Low ESR
Aluminum/ø10x20
1Pcs 270µF/16V/Conductive
Polymer/ø8x12
2Pcs 47µF/16V/X5R/1210 plus
1Pcs 270µF Conductive Polymer OR
1Pcs 1000µF Low ESR AlCap
dV1max
Unit
160
mVpp
160
mVpp
160
mVpp
90
mVpp
Table 1. Suitable Capacitors for V1
External capacitor VSB
1Pcs 270µF/16V/Conductive
Polymer/ø8x12
dVSBmax
Unit
120
mVpp
Table 2. Suitable Capacitors for VSB
The output ripple voltage on VSB is influenced by the main output V1. Evaluating VSB output ripple must be done when
maximum load is applied to V1.
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5.2 OUTPUT ISOLATION
Main and standby outputs and all signals are galvanic isolated from the chassis and protective earth connection, although the
applied voltage VI has not to exceed 75 Vpk in order to prevent catastrophic damage to the PSU.
Figure 4. Turn-on at VI = VI-nom, I1 = I1-nom (2 ms/div)
CH3 (blue): V1 (2 V/div), CH4 (green): I1 (100 A/div)
Figure 5. Turn-off at VI = VI-nom, I1 = I1-nom (2 ms/div)
CH3 (blue): V1 (2 V/div), CH4 (green): I1 (100 A/div)
Figure 6. Load transient on V1, 12 A to 122 A (1 ms/div)
CH3 (blue): V1 (0.5 V/div), CH4 (green): I1 (100 A/div)
Figure 7. Load transient on V1, 122 A to 12 A (1 ms/div)
CH3 (blue): V1 (0.5 V/div), CH4 (green): I1 (100 A/div)
Figure 8. Load transient on V1, 122 A to 244 A (1 ms/div)
CH3 (blue): V1 (0.5 V/div), CH4 (green): I1 (100 A/div)
Figure 9. Load transient on V1, 244 A to 122 A (1 ms/div)
CH3 (blue): V1 (0.5 V/div), CH3 (green): I1 (100 A/div)
Figure 10. Inrush current, VI = VI-nom, I1 = I1-nom (200 ms/div)
CH3(blue): VIN (20 V/div), CH4 (green): IIN (20 A/div)
Figure 11. Short circuit on main output (500 µs/div)
CH3 (blue): V1 (2 V/div), CH4 (green): I1 (100 A/div)
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PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
Ta < 45°C
Ta = 60 °C 1
IV1 ol lim
IV1 SC
Current limit during short time
overload V1
Max Short Circuit Current V1
V1 < 3 V
1
See Figure 26 for linear power derating > 45°C
2
Limit set don’t include effects of main output capacitive discharge.
350 2
6.1 AUTOMATIC RETRY
Any fault condition on main output V1 will shut down the main output and attempt to recover from the fault 5 times before
latching off. The time between each restart attempt is 10 s. The fault latch and fault counter can be reset by disconnecting the
input voltage or by toggling the PSON_L input. If the unit operates for more than 10 min with no failure, then the failure counter
will be reset automatically. A failure on the standby output VSB will shut down both outputs, whereas a failure on main output
V1 will only shut down this output, while VSB will continue to operate and communicate.
6.2 OVERVOLTAGE PROTECTION
The PSU provides a fixed threshold overvoltage (OV) protection, implemented with a hardware comparator. Once an
overvoltage (OV) condition has been triggered, the supply will shut down and latch the fault condition.
6.3 UNDERVOLTAGE DETECTION
As both main and standby outputs are monitored, LEDs and the PWOK_L pin will warn if V1 or VSB exceed ± 7% of its nominal
voltage. Output undervoltage protection is provided on both outputs. When either V1 or VSB falls below 93% of its nominal
voltage, the output is inhibited.
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6.4 OUTPUT OVER-CURRENT PROTECTION
MAIN OUTPUT
Two different over current protection features are implemented on the main output.
The 1st protection - a static over current protection will shut down the output, if the output current does exceed IV1 lim for more
than 20 ms. If the output current is increased slowly this protection will shut down the supply. The main output current limitation
level IV1 lim will decrease if the ambient (inlet) temperature increases beyond 45 °C (see Figure 26).
The 2nd protection - a substantially rectangular output characteristic controlled by a software feedback loop. This protects the
power supply and system during the 20 ms blanking time of the static over current protection. If the output current is rising
fast and reaches IV1 ol lim, the supply will immediately reduce its output voltage to prevent the output current from exceeding IV1
ol lim. When the output current is reduced below IV1 ol lim, the output voltage will return to its nominal value.
Figure 12. Current limitation on main output
STANDBY OUTPUT
On the standby output a hiccup type over current protection is implemented. This protection will shut down the standby output
immediately when standby current reaches or exceeds IVSB lim. After an off-time of 1s the output automatically tries to restart.
If the overload condition is removed the output voltage will reach again its nominal value VSB = VSB nom ± 1%.
At continuous overload condition the output will repeatedly trying to restart with 1s intervals.
Figure 13. Current limitation on standby output
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PARAMETER
VI mon
Input voltage
II mon
Input current
PI mon
Input power
V1 mon
Main output voltage
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
VI min ≤ VI ≤ VI max
-2.5
+2.5
%
II > 20 A
8 A< II ≤ 20 A
PI > 700 W
330 W 134 A
24 A < I1 ≤ 75 A
Po1 > 400 W
300 W < Po1 ≤ 400 W
-2.0
-1.5
-5
-20
+2.0
+1.5
+5
+20
%
A
%
W
%
I1 mon
Main output current
Po1 mon
Main output power
VSB mon
Standby voltage
-2
+2
ISB mon
Standby current
-0.2
0.2
A
PSB mon
Standby output power
-2.4
2.4
W
ELECTRICAL CHARACTERISTICS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
V
PSKILL / PSKILL_IN / PSON_L inputs
VIL
Input low level voltage
-0.2
+0.8
VIH
Input high level voltage
2.0
3.6
V
IIL, H
Maximum input sink or source current
0
1
mA
Rpu PSKILL(_IN)
Internal pull-up resistor on PSKILL
10
kΩ
RpuPSON_L
Internal pull-up resistor on PSON_L
10
kΩ
PWOK_L output
VOL
Output level voltage
Vpu PWOK_L
External pull-up voltage
Rpu PWOK_L
Recommended external pull-up resistor on
PWOK_L at Vpu PWOK_L = 3.3 V
Low level output
All outputs are turned on and within regulation
High level output
In standby mode or V1 / VSB have triggered a
fault condition
Isink < 4 mA
-0.2
0.4
V
12
V
10
kΩ
INOK_L output
VOL
Output low level voltage
VpuINOK_L
External pull-up voltage
Rpu INOK_L
Recommended external pull-up resistor on
INOK_L at Vpu INOK_L = 3.3 V
Low level output
Input voltage is within range for PSU to operate
High level output
Input voltage is not within range for PSU to
operate
Isink < 4 mA
-0.2
0.4
V
12
V
10
kΩ
SMB_ALERT_L output
VOL
Output low level voltage
Vpu SMALT_L
External pull-up voltage
Rpu SMALT_L
Recommended external pull-up resistor on
SMB_ALERT_L at Vpu SMALT_L = 3.3 V
Low level output
PSU is in warning or failure condition
High level output
PSU is ok
Isink < 4 mA
-0.2
10
0.4
V
12
V
kΩ
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8.2 INTERFACING WITH SIGNALS
A 15 V Zener diode is added on all signal pins versus signal ground SGND to protect internal circuits from negative and high
positive voltage. Signal pins of several supplies running in parallel can be interconnected directly. A supply having no input
power will not affect the signals of other PSUs running in parallel.
The current share bus pin (ISHR_BUS) must be interconnected without any additional components; as protection element,
a 15 V Zener diode is connected to the signal reference SGND. The share bus is disconnected (analog switch) from internal
circuits when the power supply is switched off.
8.3 LED STATUS - FRONT LEDs
The PSU has two front LEDs showing its status: DC Input LED is green colored and indicates DC power ON / OFF, DC
Output LED is bi-colored green and yellow and shows DC output OK or a warning/fault status as listed in Table 1.
OPERATING CONDITION
LED SIGNALING
IN: DC Input LED
DC line within range
DC line UV / OV condition
Bootload
Solid Green
OFF
Blinking green: OFF (1:1)
OUT: DC Output LED
Normal Operation
Solid Green
PSKILL_IN_L - Left open
PSON_L - High, PSKILL_L - High
Power Management Bus Command
OPERATION
DC line UV / OV condition
V1 or VSB out of regulation
Over temperature shutdown
Output over voltage shutdown (V1 or VSB)
Output under voltage shutdown (V1 or VSB)
Output over current shutdown (V1 or VSB)
Both FANs blocked
Over temperature warning
Minor fan regulation error (> 5 %, < 15 %)
Or one of the FANs blocked
Bootload
Blinking Yellow (1:1)
Solid Yellow
Blinking Yellow/Green (2:1)
Blinking Yellow/Green (1:1)
Blinking Green (1:1)
Table 3. LED Status
8.4 PRESENT_L
PRESENT_L is a trailing pin within the connector and will contact only once all other connector contacts. This active-low pin
is used to indicate to a power distribution unit controller that a supply is plugged in. Maximum sink current on PRESENT_L
pin should not exceed 10 mA.
Figure 14. PRESENT_L signal pin
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8.5 PSKILL_L / PSKILL_IN_L INPUT
PSKILL_L input is an active-low trailing pin in the output connector and is used to disconnect the main output as soon as
the power supply is being pulled out. This pin should be connected to SGND in the power distribution unit. Standby output
will remain on, regardless of the PSKILL_L input state.
PSKILL_IN_L input is an active-low signal pin in the input connector and is used to disconnect the main output as soon as
the input connector is plugged out. This pin should be connected to SGND on the input connector mating part. Standby
output will remain on, regardless of the PSKILL_L input state.
8.6 DC TURN-ON / DROP-OUTS / INOK_L
The INOK_L signal indicates whether the DC input voltage is within the operating range and the power supply can turn on.
The power supply will automatically turn-on when connected to the DC line within the operating voltage range under the
condition that the PSON_L signal is pulled low. INOK_L is an active low open collector output that requires an external pullup voltage to maximum 12.0 V.
8.7 PSON_L INPUT
PSON_L is an internally pulled-up (3.3 V) input signal to enable / disable the main output V1. This active-low pin is also
used to clear any latched fault condition. Timing parameters are listed in Table 2.
8.8 PWOK_L SIGNAL
PWOK_L is an open collector output that requires an external pull-up voltage to maximum 12 V, indicating whether both V1
and VSB outputs are within regulation. This pin is active-low; timing parameters are listed in Table 2.
8.9 SIGNAL TIMING
OPERATING CONDITION
MIN
MAX
UNIT
tV1_rise
See table Output Parameter
tVSB_rise
See table Output Parameter
tINOK_On
INOK_L delay at dropout
0
700
ms
tINOK_On_Pwr_On
INOK_L delay at coldstart
500
1800
ms
tINOK_to_VSB_rise
INOK_L to VSB delay
1
5
ms
tVSB_Pwr_On
Vin to VSB delay
520
1805
ms
tV1_Pwr_On
Vin to V1 delay
700
3000
ms
tPWOK_On
V1 in regulation to PWOK_L
280
320
ms
tV1_fall
monotonic
tVSB_fall
monotonic
tINOK_Off
INOK_L delay
0
1.8
ms
tINOK_warn
INOK_L to V1 out of regulation (0.5 I1), VI > 48V
tV1_holdup
See table Output Parameter
tVSB_holdup
See table Output Parameter
tPWOK_Off
V1 out of regulation to PWOK_L
tPSON_On
PSON_L to V1 in regulation
tPSON_Off
PSON_L to V1 out of regulation
tPSKILL(_IN)_On
PSKILL(_IN)_L to V1 in regulation
tPSKILL(_IN)_Off
PSKILL(_IN)_L to V1 out of regulation
1.0
ms
0
5
ms
150
170
ms
0
5
ms
150
170
ms
0
5
ms
Table 4. On-/Off- Signal Timings
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Figure 15. Power on Delay, Rise Time and Signaling
Figure 16. Power Removed Holdup, Fall Time and Signaling
Figure 17. Turn On Delay, Rise Time and Signaling
Figure 18. Turn Off, Fall Time and Signaling
Figure 19. Dropout and Signaling
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8.10
CURRENT SHARE
The PSU has an active current share scheme implemented for main output V1. ISH_BUS current share pins of all units in parallel
need to be interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will
disconnect its ISHR_BUS pin from the share bus: this will prevent dragging the output down (or up) in such cases.
Master / Slave current share function implemented by the controller uses an analog bus: the power supply providing the largest
current among the group is automatically the Master. The other supplies will operate as Slaves and increase their output current
to a value close to the Master by slightly increasing their output voltage. The output voltage increase is limited to +250 mV.
Standby output uses an analog passive current-share method (droop-output voltage characteristic).
Maximum available main and stand-by power in (non)-redundant topology is listed in Table 5.
No. of paralleled
PSUs
Max available power on
main output without redundancy
Max available power on
main output with n+1 redundancy
Max available power
on standby output
1
2
3000 W
-
24 W
5850 W
3000 W
24 W
3
8700 W
5850 W
24 W
4
11550 W
8700 W
24 W
5
14400 W
11550 W
24 W
6
17250 W
14400 W
24 W
Table 5. Available power when multiple PSUs are operating
8.11
SENSE INPUTS
Main output sense lines have been implemented in order to compensate voltage drops on the load wires: a maximum voltage
drop of 200 mV on the positive rail and 100 mV on the PGND rail is allowed. If sense inputs are not connected (open), main
output voltage will rise by 250 mV; therefore, if sense inputs are not used, they should be connected to the power output and
SGND, close to the power supply connector. The sense inputs are protected against short circuit and reverse polarity. If the
sense lines are shorted (or reverse polarized) at start-up condition, then V1 will be regulated by 500 mV higher than the reference
voltage for 100 ms and later the PSU will shut down reporting a sense fault error. If the sense lines are shorted (or reverse
polarized) during operation, then the unit will shut down immediately.
8.12
I2C / POWER MANAGEMENT BUS COMMUNICATION
The PSU is a communication slave device only: it never initiates messages on the I2C / SMBus. It recognizes any time Start /
Stop bus conditions and the interface driver in the supply is referred to the SGND. Communication bus voltage and timing are
defined by:
•
•
•
•
•
•
100 kΩ internal pull-up resistors
SDA / SCL IOs must be pull-up externally to 3.3 ± 0.3 V
Pull-up resistor should be 2 kΩ to 5 kΩ to ensure SMBUS
compliant signal rise times
Full SMBus clock speed of 100 kbps
Clock stretching limited to 1 ms
SCL low time-out of > 25 ms with recovery time within 10 ms
Figure 20. Physical layer of communication interface
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PFF3000-12-069RD
15
SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate:
this is a logical OR of the shutdown and warning events. Communication to the DSP will be possible as long as the input
voltage is provided. If no input voltage is present, communication to the unit is possible as long as it is connected to a live V SB
output (e.g. provided by a redundant unit); if only V1 is provided, communication is not possible.
PARAMETER
MIN
MAX
UNIT
ViL
Input low voltage
CONDITION
-0.2
0.4
V
ViH
Input high voltage
2.1
3.6
V
Vhys
Input hysteresis
0.15
VoL
Output low voltage
tr
Rise time for SDA and SCL
tof
Output fall time ViHmin ➔ ViLmax
Ii
Input current SCL / SDA
Ci
Capacitance for each SCL / SDA
fSCL
SCL clock frequency
Rpu
External pull-up resistor
tHDSTA
Hold time (repeated) START
fSCL ≤ 100 kHz
4.0
µs
tLOW
Low period of the SCL clock
fSCL ≤ 100 kHz
4.7
µs
tHIGH
High period of the SCL clock
fSCL ≤ 100 kHz
4.0
µs
tSUSTA
Setup time for a repeated START
fSCL ≤ 100 kHz
4.7
tHDDAT
Data hold time
fSCL ≤ 100 kHz
0
tSUDAT
Data setup time
fSCL ≤ 100 kHz
250
µs
tSUSTO
Setup time for STOP condition
fSCL ≤ 100 kHz
4.0
µs
tBUF
Bus free time between STOP and START
fSCL ≤ 100 kHz
4.7
µs
4 mA sink current
V
0
0.4
V
20 + Rb Cb1
300
ns
10 pF < Cb1 < 400 pF
20 + Rb Cb1
250
ns
0.1 VDD < Vi < 0.9 VDD
-10
10
µA
10
pF
0
100
kHz
1000 ns / Cb1
Ω
µs
3.45
µs
EEPROM_WP
ViL
Input low voltage
-0.2
0.4
ViH
Input high voltage
2.1
3.6
V
Ii
Input sink or source current
-1
1
mA
Rpu
Internal pull-up resistor to 3.3V
1
V
Ω
10k
Cb = Bus line capacitance in pF, typically in the range of 10 pF…400 pF, Rb = 100 Ω
Table 6. I2C / SMBus Specification
tof
tLOW
tHIGH
tLOW
tr
SCL
tSUSTA
tHDSTA
tHDDAT tSUDAT
tSUSTO
tBUF
SDA
Figure 21. I2C / SMBus Timing
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8.13
ADDRESS
The unit supports the Power Management Bus communication protocol with a fixed address at 0x20. The EEPROM is at fixed
address = 0xA0.
8.14
CONTROLLER ACCESS
The controller and the EEPROM in the power supply share the same I2C bus physical layer (see Figure 23). In order to write to
the EEPROM, the write protection needs to be disabled by setting EEPROM_WP input correctly. EEPROM_WP=HIGH: write
disabled; EEPROM_WP=LOW: write enabled.
Figure 22. I2C Bus to Controller and EEPROM
8.15
EEPROM PROTOCOL
The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read
commands are defined, it is recommended to use the single byte write / read commands.
WRITE
The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte
with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus
should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory.
S Address W A
Data Address
A
Data
A
P
READ
The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data
address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the
data byte at the specified location.
S Address W A
S Address R
A
Data Address
Data
A
nA P
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PFF3000-12-069RD
8.16
17
POWER MANAGEMENT BUS PROTOCOL
The Power Management Bus is an open standard protocol that defines means of communicating with power conversion and
other devices. For more information, please see the System Management Interface Forum web site at: www.powerSIG.org.
Power Management Bus command codes are not register addresses. They describe a specific command to be executed.
PFF3000-12-069RD supply supports the following basic command structures:
•
Clock stretching limited to 1 ms
•
SCL low time-out of >25 ms with recovery within 10 ms
•
Recognized any time Start/Stop bus conditions
WRITE
The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte
or after the first data byte (Byte command) or then after sending 2 data bytes (Word command).
S Address W A
Data Low Byte1) A
1)
Command
A
Data High Byte1) A
P
Optional
In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFF3000-12-069RA Power
Management Bus Communication Manual BCA.00070 for further information.
S Address W A
Byte 1
Command
A
A
Byte Count
A
Byte N
A
P
READ
The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word.
S Address W A
S Address R
1)
A
Command
A
Data (Low) Byte A
Data High Byte1) nA P
Optional
In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFF3000-12-069RD Power
Management Bus Communication Manual BCA.00216 for further information.
S Address W A
Byte Count
A
Command
Byte 1
A
A
S Address R
Byte N
A
nA P
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8.17
GRAPHICAL USER INTERFACE
Bel Power Solutions provides its I2C Utility: a Windows® XP / Vista / Win7 compatible graphical user interface (GUI), allowing
PFF3000-12-069RD programming and monitoring. This utility can be downloaded at belfuse.com/power-solutions and
supports both the PSI and Power Management Bus protocols. The GUI allows automatic finding of connected units to the
communication bus and will show them in the navigation tree. In, the monitoring view the power supply can be controlled and
monitored.
Figure 23. Monitoring dialog of the I2C utility (example)
In order to achieve best cooling results, sufficient airflow through the supply must be ensured; airflow shall not be blocked or
obstructed by placing large objects close to the output connector at the rear of the supply. PFF3000-12-069RD is provided with a
front-to-rear airflow, thus meaning the air enters through the power supply handle side (front) and leaves at the rear side.
PFF3000-12-069RD has been designed for horizontal operation. The internal fan is controlled by a microprocessor: fan rpm is
then adjusted to provide optimal cooling air and is a function of output power, inlet and internal MOSFETs temperature.
Figure 24. Airflow direction
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PFF3000-12-069RD
19
3000
Main Output Power [W]
Fan Speed [1000xRPM]
25
20
15
45°C
35°C
25°C
10
5
2250
1500
750
0
0
0%
20%
40%
60%
80%
100%
0
12
36
48
60
Ambient Temperature [°C]
Main Output Current I1 / I1 nom [%]
Figure 25. Fan speed vs. main output load
10.1
24
Figure 26. Thermal power derating
IMMUNITY
NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003.
PARAMETER
DESCRIPTION / CONDITION
ESD Contact Discharge
ESD Air Discharge
Radiated Electromagnetic Field
Burst
Surge
RF Conducted Immunity
10.2
CRITERION
IEC / EN 61000-4-2, ± 8 kV, 25 + 25 discharges per test point
(metallic case, LEDs, connector body)
IEC / EN 61000-4-2, ± 15 kV, 25 + 25 discharges per test point
(non-metallic user accessible surfaces)
IEC / EN 61000-4-3, 10 V/m, 1 kHz / 80% Amplitude Modulation,
1µs Pulse Modulation, 10 kHz…2GHz
IEC / EN 61000-4-4, level 3,
DC port ± 1kV, 1 minute
IEC / EN 61000-4-5
Line to earth: level 2, ± 1kV
Line to line: level 3, ± 1kV
IEC / EN 61000-4-6, level 3, 10 Vrms, CW, 0.1… 80 MHz
A
A
A
A
A
A
EMISSION
PARAMETER
DESCRIPTION / CONDITION
CRITERION
Conducted Emission
EN55022 / CISPR 22: 0.15… 30 MHz, QP and AVG
Class A
Radiated Emission
EN55022 / CISPR 22: 30 MHz… 1 GHz, QP
Class A
Acoustical Noise
Sound power statistical declaration (ISO 9296, ISO 7779, IS9295)
load
@ 50 %
60 dBA
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Maximum electric strength testing is performed in factory according to IEC / EN 60950 and UL 60950. Input - to - output electric
strength tests should not be repeated in the field. Bel Power Solutions will not honour any warranty claims resulting from electric
strength field tests.
PARAMETER
DESCRIPTION / CONDITION
CRITERION
Approved to the latest edition of the following standards:
• IEC60950-1 2nd edition (CB)
• EN60950-1 2nd Edition (Nemko)
• UL/CSA0950-1 2nd Edition (cCSAus)
Input (DCIN+ / DCIN-) to case (PE)
Agency Approvals
Isolation Strength
Approved by independent
body
(see CE declaration)
Basic
Input (DCIN+ / DCIN-) to output
Basic
Output to case (PE)
Creepage / Clearance
Functional
Primary (DCIN+ / DCIN-) to protective earth (PE)
According to safety
standard
Primary to secondary
Input to case
Electrical Strength Test
According to safety
standard
Input to output
Output and signals to case
PARAMETER
DESCRIPTION / CONDITION
MIN
Vi min to Vi max, I1 nom, ISB nom at 4000 m
MAX
UNIT
0
NOM
+40 *
°C
TA
Ambient temperature
0
+45
°C
TAext
Extended temperature range
Derated output
+45
+55
°C
TS
Storage temperature
Non - operational
-40
+70
°C
Altitude
Operational, above sea level
-
4000
m
Operational: TA = 40 °C
7
85
%
Non-Operational
5
93
%
Vi min to Vi max, I1 nom, ISB nom at 1800 m
Relative humidity
Na
Audible noise
Vi nom, 50 % Io nom,
TA = 25 °C at by-stander position
Cooling
System back pressure
Operational:
Non-Operational:
11ms, half-sine
11ms, half-sine
IEC60068-2-27
Operational:
Non-Operational:
Swept-sine, 5-500-5 Hz
Swept-sine, 5-500-5 Hz
Random, 10-500 Hz
IEC60068-2-32
Edge drop, Corner drop, topple
Shock
IEC60068-2-27
Vibration
Fall test
60
dBA
0.5
7
30
in H20
g pk
1
4
3.5
gpk
1
m
NOTE: * System airflow will assist the PSU airflow
PARAMETER
Dimensions
m
Weight
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
Width
69
mm
Height
42
mm
Depth
555
mm
2.66
kg
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21
NOTE: A 3D step file of the power supply casing is available on request.
Figure 27. ISO front and rear view
Figure 28. Front and rear view
Figure 29. Top view
Figure 30. Front and rear view
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Input
Output
S1
IN1
Aux1
Aux3
Aux2
Aux4
S2
S1
IN2
P1
Connector: Anderson Power SBS75XPRBLK-BK
Counterpart:
Housing: Anderson Power SBS75XBLK
Power pins IN1/2 (AWG6): Anderson Power 1339G2
Sockets Aux1/2 (AWG24-20): Anderson Power PM16S2024S32
P2
S3
S2
P3
P4
S4
S3
P5
S4
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
B1
B2
B3
B4
B5
A1
A2
A3
A4
A5
Connector: Amphenol/FCI 51939-768LF
Counterpart: Amphenol/FCI 51915-401LF
A1 and A2 are trailing pins (short pins)
For main output pins (S1-S4), see section 14
14.1 INPUT CONNECTOR PINOUT
PIN
NAME
DESCRIPTION
IN1
DCIN-
Input voltage negative
IN2
DCIN+
Input voltage positive
Input Power
Input Signals
Aux1
reserved
Aux2
reserved
Aux3
PSKILL_IN_L
Input connector power supply kill
Aux4
SGND
Signal ground
Table 7. Input Connector Pinout
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23
14.2 OUTPUT CONNECTOR PINOUT
Output
S1, S2
PGND
+12 VDC main output ground
S3, S4
V1
+12 VDC main output
PE
P1
P2
Protective Earth
empty
P3
P4
Protective Earth
empty
P5
Protective Earth
Output Signals
A1
PSKILL_L
Power supply kill (trailing pin):
active low
B1
PWOK_L
Power OK signal output:
active low
C1
INOK_L
Input OK signal:
active low
D1
PSON_L
Power supply on input:
active low
A2
PRESENT_L
Power supply present (trailing pin):
active low
B2
SGND
Signal ground * (return)
C2
SGND
Signal ground * (return)
D2
SGND
Signal ground * (return)
A3
SCL
I2C clock signal line
B3
SDA
I2C data signal line
C3
SMB_ALERT_L
SMB alert signal output:
D3
ISHR_BUS
V1 current share bus
A4
EEPROM_WP
EEPROM Write protect
B4
RSVD
Reserved
C4
V1_SNS_R
Main output negative sense
D4
V1_SNS
Main output positive sense
A5
VSB
Standby positive output
B5
VSB
Standby positive output
C5
VSB_R
Standby ground *
D5
VSB_R
Standby ground *
active low
NOTE: * These pins should be connected to SGND on the system.
See section 7 for pull-up resistor settings of signal pins - All signal pins are referred to SGND.
Table 8. Output Connector Pinout
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PFF3000-12-069RD
See also SPSPFF3-01 datasheet BDC.00887
The recommended pin configuration below is based on company’s own Shelf design and provided here as reference. Customer pin lengths
within the range indicated is acceptable.
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PFF3000-12-069RD
ITEM
25
DESCRIPTION
ORDERING PN
SOURCE
N/A
belfuse.com/power-solutions
I2C Utility
Windows Vista/7/8 compatible
GUI to program, control and
monitor PFE Front-Ends (and
other I2C units)
DOCUMENT NUMBER
DESCRIPTION
BCA.00447
PFF3000-12-069RD Installation Instruction
BCA.00216
PFF3000-12-069RD Power Management Bus Communication Manual
BCD.00887
Power Shelf SPSPFF3-01G datasheet
BCD.00820
NAC2006-01 datasheet
REV
DESCRIPTION
008
PSU PRODUCT
VERSION
DATE
AUTHOR
First release version
Jan-2018
RK/MS
011
Product photo updated; Output and Protection table update; Added EEPROM
and Power Management Bus Protocol chapters; General unification with
PFE3000 product
Mar-2018
RK/MS
AA
Update readback and protection table, release to AA
June-2018
AB
Update input voltage from positive to negative values, Correct (swap) Pi and
Po readback tolerances
Aug-2018
AC
Remove preliminary watermark
RK
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems,
equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
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