P650-U

PL IA NT Features ■ Formerly ■ ■ ■ ■ ■ ■ Applications ■ Mb Ethernet port protection ■ Gb Ethernet port protection ■ Isolated and floating interfaces brand Extremely high speed performance Blocks high voltages and currents Low insertion loss Two TBU™ protectors in one small package Very high bandwidth; GHz compatible RoHS compliant*, UL Recognized *R oH S CO M TBU™ P650-U and P850-U Protectors Transient Blocking Units - TBU™ Devices Agency Approval UL recognized component File # E315805. Industry Standards Description Telcordia ITU-T GR-1089 Port Type 3, 5 Port Type 2, 4 Model P650-U P850-U P850-U Bourns® Model P650-U and P850-U products are high speed, unidirectional protection components, constructed using MOSFET semiconductor technology, designed to protect against faults caused by short circuits, AC power cross, induction and lightning surges. The TBU™ high speed protector, triggering as a function of the MOSFET, blocks surges and provides an effective barrier behind which sensitive electronics are not exposed to large voltages or currents during surge events. The TBU™ device is provided in a surface mount DFN package and meets industry standard requirements such as RoHS and Pb Free solder reflow profiles. Absolute Maximum Ratings (Tamb = 25 °C) Symbol Vimp Vrms Top Tstg Parameter K.20, K.20E, K.21, K.21E, K.45 Value P650-Uxxx-WH P850-Uxxx-WH P650-Uxxx-WH P850-Uxxx-WH 650 850 300 425 -40 to +85 -65 to +150 Unit V V °C °C Maximum protection voltage for impulse faults with rise time ≥ 1 µsec Maximum protection voltage for continuous Vrms faults connected as a series pair (refer to page 3 Test Configuration Diagram) Operating temperature range Storage temperature range Electrical Characteristics (Tamb = 25 °C) Symbol Iop Parameter P650-U180-WH Maximum current through the device that will not cause P650-U260-WH current blocking P850-U180-WH P850-U260-WH P650-U180-WH Typical current for the device to go from normal operating P650-U260-WH state to protected state P850-U180-WH P850-U260-WH P650-U180-WH P650-U260-WH Maximum current through the device P850-U180-WH P850-U260-WH P650-Uxxx-WH ™ Series resistance of the TBU device P850-Uxxx-WH Line-to line series resistance difference between two TBU™ device Maximum time for the device to go from normal operating P650-Uxxx-WH state to protected state P850-Uxxx-WH Current through the triggered TBU™ device with 50 Vdc circuit voltage Voltage below which the triggered TBU device will transition to normal operating state ™ Min. Typ. Max. 180 260 180 260 Unit mA Itrigger 220 330 220 330 360 520 360 520 7 9 0.5 1 1 11 14 mA Iout mA RTBU Rbal tblock Iquiescent Vreset 6 8 Ω Ω µs mA V P650-Uxxx-WH P850-Uxxx-WH The P-U Series TBU™ devices are unidirectional; specifications are valid for input direction only. For the output direction, the TBU™ device is a resistor. *RoHS Directive 2002/95/EC Jan 27 2003 including Annex. Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TBU™ P650-U and P850-U Protectors Typical Performance Characteristics V-I Characteristics I ITRIG Trigger Current 1/R Time to Block vs. Fault Current 1 0.1 Time to Block (sec) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 0.1 1 10 100 1000 Reset Voltage Threshold V Fault Current (A ) Trigger Current vs. Temperature 140 120 % of Trigger Current 100 80 60 40 20 -40 -20 0 20 40 60 80 Temperature (°C) Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TBU™ P650-U and P850-U Protectors Operational Characteristics The graphs below demonstrate the operational characteristics of the TBU. For each graph the fault voltage, protected side voltage, and current is presented. V1 V2 Load TEST CONFIGURATION DIAGRAM P650-U Lightning, 650 V P850-U Lightning, 850 V 3 3 100 V/div. 100 V/div. 200 mA/div. 2 2 1 1 1 us/div. Ch1 V1 Ch2 V2 Ch3 Current Ch1 V1 1 us/div. Ch2 V2 Ch3 Current P650-U Power Fault, 120 Vrms, 25 A P850-U Power Fault, 230 Vrms, 25 A 3 200 mA/div. 3 2 1 2 200 mA/div. 1 Ch1 V1 4 ms/div. Ch2 V2 4 ms/div. Ch3 Current Ch1 V1 Ch2 V2 Ch3 Current Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 200 mA/div. 100 V/div. 100 V/div. TBU™ P650-U and P850-U Protectors Product Dimensions L E B J C K F G N J Dim. A B Min. 6.15 (.242) 7.65 (.301) 0.80 (.031) 0.000 (.000) 0.50 (.020) 1.20 (.047) 4.20 (.165) 2.45 (.096) 0.20 (.008) 0.45 (.018) 0.65 (.026) 0.20 (.008) 0.70 (.028) 3.20 (.126) DIMENSIONS: Typ. 6.25 (.246) 7.75 (.305) 0.85 (.033) 0.025 (.001) 0.55 (.022) 1.25 (.049) 4.25 (.167) 2.50 (.098) 0.25 (.010) 0.50 (.020) 0.70 (.028) 0.25 (.010) 0.75 (.030) 3.25 (.128) MM (INCHES) Max. 6.35 (.250) 7.85 (.309) 0.90 (.035) 0.050 (.002) 0.60 (.024) 1.30 (.051) 4.30 (.169) 2.55 (.100) 0.30 (.012) 0.55 (.022) 0.75 (.030) 0.30 (.012) 0.80 (.031) 3.30 (.130) 4 A 5 6 H C P 3 2 1 D E H PIN 1 D N F G H J K L N P Q TOP VIEW SIDE VIEW BOTTOM VIEW Recommended Pad Layout 2.525 (.099) 0.50 (.020) 0.575 (.023) 1.25 (.049) 0.70 (.028) 4.275 (.168) 0.375 (.015) Pad Designation Pad # Apply 1 In1 2 NC 3 Out1 4 Out2 5 NC 6 In2 NC = Solder to PCB; do not make electrical connection, do not connect to ground. TBU™ devices have matte-tin termination finish. Suggested layout should use non-solder mask define (NSMD). Recommended stencil thickness is 0.10-0.12 mm (.004-.005 in.) with stencil opening size 0.025 mm (.0010 in.) less than the device pad size. As when heat sinking any power device, it is recommended that, wherever possible, extra PCB copper area is allowed. For minimum parasitic capacitance, do not allow any signal, ground or power signals beneath any of the pads of the device. Block Diagram 6 4 3 TBU™ Device Load Side Thermal Resistances Symbol Rth(j-a) Parameter Junction to leads (package) Junction to leads (per TBU) Value 105 202 Unit °C/W °C/W Line Side 1 Reflow Profile Profile Feature Average Ramp-Up Rate (Tsmax to Tp) Preheat - Temperature Min. (Tsmin) - Temperature Max. (Tsmax) - Time (tsmin to tsmax) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5 °C of Actual Peak Temp. (tp) Ramp-Down Rate Time 25 °C to Peak Temperature Pb-Free Assembly 3 °C/sec. max. 150 °C 200 °C 60-180 sec. 217 °C 60-150 sec. 260 °C 20-40 sec. 6 °C/sec. max. 8 min. max. Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 3312 - 2 mm SMD Trimming Potentiometer TBU™ P650-U and P850-U Protectors How to Order Typical Part Marking P 650 - U 180 - WH Form Factor P = Two TBU™ protectors in one device Impulse Voltage Rating 650 = 650 V 850 = 850 V Directional Indication for Paired Devices U = Unidirectional Iop Indicator 180 = 180 mA 260 = 260 mA PIN 1 MANUFACTURER’S TRADEMARK* MARKING NUMBER 65UB = P650-U180-WH 65UC = P650-U260-WH 85UB = P850-U180-WH 85UC = P850-U260-WH MANUFACTURING DATE CODE* - 1ST DIGIT INDICATES THE YEAR’S 6-MONTH PERIOD. - 2ND DIGIT INDICATES THE WEEK NUMBER IN THE 6-MONTH PERIOD. - 3RD & 4TH DIGITS INDICATE SPECIFIC LOT FOR THE WEEK. 6-MONTH PERIOD CODES: A = JAN-JUN 2009 C = JAN-JUN 2010 B = JUL-DEC 2009 D = JUL-DEC 2010 E = JAN-JUN 2011 F = JUL-DEC 2011 EXAMPLE: ARBC - 1ST DIGIT ‘A’ = JAN-JUN 2009 - 2ND DIGIT ‘R’ = WEEK 18; WEEK OF APRIL 27 - 3RD & 4TH DIGITS ‘BC’ = LOT SPECIFIC INFORMATION *TRANSITION FROM FULTEC TRADEMARK AND LOT CODE TO BOURNS TRADEMARK AND DATE CODE IN 2009. Packaging Specifications (per EIA468-B) P0 E B t TOP COVER TAPE N D C F W D P2 A B0 K0 A0 P G (MEASURED AT HUB) USER DIRECTION OF FEED CENTER LINES OF CAVITY D1 EMBOSSMENT QUANTITY: 3000 PIECES PER REEL Device P650-U, P850-U A0 Min. 6.5 (.256) K0 Min. 1.4 (.055) Max. 1.6 (.063) Max. 6.7 (.264) A Min. 326 (12.835) Max. 330.25 (13.002) B0 Min. 8.0 (.315) P Min. 11.9 (.469) Max. 12.1 (.476) Min. 3.9 (.159) Max. 8.2 (.323) Min. 1.5 (.059) Min. 1.5 (.059) B Max. 2.5 (.098) D Max. 1.6 (.063) P0 Max. 4.1 (.161) Min. 1.9 (.075) Min. 1.5 (.059) Min. 12.8 (.504) C Max. 13.5 (.531) D1 Max. P2 Max. 2.1 (.083) Min. 0.25 (.010) Min. 1.65 (.065) Min. 20.2 (.795) D Max. E Max. 1.85 (.073) t Max. 0.35 (.014) G Ref. 16.5 (.650) F Min. 7.4 (.291) W Min. 15.7 (.618) DIMENSIONS: N Ref. 102 (4.016) Device P650-U, P850-U Device P650-U, P850-U max. 7.6 (.299) Max. 16.3 (.642) MM (INCHES) Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TBU™ P650-U and P850-U Protectors Reference Applications A cost-effective protection solution utilizes the Bourns® TBU™ protection devices. The diagrams below illustrate common configurations of these components. The graph at the bottom demonstrates the operational characteristics of the circuit. Typical Configuration Diagrams P850-U Tx P850-U V1 V2 Tx G5200AS P850-U Rx P850-U Rx G5200AS P850-U Tx G5200AS P850-U Rx P850-U Rx G5200AS 2000 V, 22 pF 3 RJ 45 connector P850-U Tx 2000 V, 22 pF GbE Ethernet Protection Up to 1500 V Common-Mode Lightning Protection 100 V/div. 200 mA/div. RJ 45 connector GbE Ethernet Protection Up to 6000 V Common-Mode Lightning Protection 2 Asia-Pacific: Tel: +886-2 2562-4117 • Fax: +886-2 2562-4116 Europe: Tel: +41-41 768 5555 • Fax: +41-41 768 5510 1 µs/div. Ch1 V1 Ch2 V2 Ch3 Current 1 The Americas: Tel: +1-951 781-5500 • Fax: +1-951 781-5700 www.bourns.com P850-U with G5200AS 4000 V Lightning 10/700 µsec, 150 A Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. REV. 03/10 COPYRIGHT©2008, BOURNS, INC. LITHO IN U.S.A. e 12/08 FU0801