TISP5070H3BJ THRU TISP5190H3BJ
FORWARD-CONDUCTING UNIDIRECTIONAL THYRISTOR
OVERVOLTAGE PROTECTORS
TISP5xxxH3BJ Overvoltage Protector Series
Analogue Line Card and ISDN
Protection
SMB Package (Top View)
Additional Information
Click these links for more information:
- Analogue SLIC
- ISDN U Interface
- ISDN Power Supply
A 1
2 K
8 kV 10/700, 200 A 5/310 ITU-T
K.20/21/45 rating
PRODUCT TECHNICAL INVENTORY SAMPLES
SELECTOR LIBRARY
MD5UFCAB
Device Symbol
Ion-Implanted Breakdown Region
- Precise and Stable Voltage
Agency Recognition
K
Description
Low Voltage Overshoot under Surge
UL
Device Name
VDRM
V
V(BO)
V
TISP5070H3BJ
TISP5080H3BJ
TISP5095H3BJ
TISP5110H3BJ
TISP5115H3BJ
TISP5150H3BJ
TISP5190H3BJ
-58
-65
-75
-80
-90
-120
-160
-70
-80
-95
-110
-115
-150
-190
Rated for International Surge Wave
Shapes
Wave
Shape
Standard
IPPSM
A
2/10
GR-1089-CORE
500
8/20
ANSI C62.41
300
10/160
TIA-968-A
250
10/700
ITU-T K.20/21/45
200
10/560
TIA-968-A
160
10/1000
GR-1089-CORE
100
CONTACT
File Number: E215609
............UL Recognized Component
SD5XAD
A
Description
These devices are designed to limit overvoltages on the telephone and data lines.
Overvoltages are normally caused by a.c. power system or lightning flash disturbances
which are induced or conducted on to the telephone line. A single device provides 2-point
protection and is typically used for the protection of ISDN power supply feeds. Two devices,
one for the Ring output and the other for the Tip output, will provide protection for single
supply analogue SLICs. A combination of three devices will give a low capacitance protector
network for the 3-point protection of ISDN lines.
The protector consists of a voltage-triggered unidirectional thyristor with an anti-parallel
diode. Negative overvoltages are initially clipped by breakdown clamping until the voltage
rises to the breakover level, which causes the device to crowbar into a low-voltage on state.
This low-voltage on state causes the current resulting from the overvoltage to be safely
diverted through the device. The high crowbar holding current helps prevent d.c. latchup as
the diverted current subsides. Positive overvoltages are limited by the conduction of the antiparallel diode.
How to Order
Device
TISP5xxxH3BJ
Package
Carrier
BJ (J-Bend
Embossed
DO-214AA/SMB) Tape Reeled
Order As
TISP5xxxH3BJR-S
Marking
Code
Std.
Quantity
5xxxH3
3000
Insert xxx value corresponding to protection voltages of 070, 080, 110, 115 and 150.
JANUARY 1998 – REVISED JULY 2019
WARNING Cancer and Reproductive Harm
www.P65Warnings.ca.gov
*RoHS Directive 2015/863, Mar 31, 2015 and Annex.
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of
this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
Absolute Maximum Ratings, TA = 25 °C (Unless Otherwise Noted)
Rating
'5070H3BJ
'5080H3BJ
'5095H3BJ
'5110H3BJ
'5115H3BJ
'5150H3BJ
'5190H3BJ
Repetitive peak off-state voltage (see Note 1)
Symbol
Value
Unit
VDRM
-58
-65
-75
-80
-90
-120
-160
V
IPPSM
±500
±300
±250
±220
±200
±200
±200
±160
±100
A
ITSM
55
60
2.1
A
diT/dt
±400
A/μs
TJ
-40 to +150
°C
Tstg
-65 to +150
°C
Non-repetitive peak impulse current (see Notes 2, 3 and 4)
2/10 μs (GR-1089-CORE, 2/10 μs voltage wave shape)
8/20 μs (IEC 61000-4-5, 1.2/50 μs voltage, 8/20 μs current combination wave generator)
10/160 μs (TIA-968-A, 10/160 μs voltage wave shape)
5/200 μs (VDE 0433, 10/700 μs voltage waveshape)
0.2/310 μs (I3124, 0.5/700 μs waveshape)
5/310 μs (ITU-T K.44, 10/700 μs voltage waveshape used in K.20/21/45)
5/310 μs (FTZ R12, 10/700 μs voltage waveshape)
10/560 μs (TIA-968-A, 10/560 μs voltage wave shape)
10/1000 μs (GR-1089-CORE, 10/1000 μs voltage wave shape)
Non-repetitive peak on-state current (see Notes 2, 3 and 5)
20 ms, 50 Hz (full sine wave)
16.7 ms, 60 Hz (full sine wave)
1000 s 50 Hz/60 Hz a.c.
Initial rate of rise of on-state current, GR-1089-CORE 2/10 μs wave shape
Junction temperature
Storage temperature range
NOTES: 1.
2.
3.
4.
5.
See Figure 9 for voltage values at lower temperatures.
Initially the device must be in thermal equilibrium with TJ = 25 °C.
The surge may be repeated after the device returns to its initial conditions.
See Figure 10 for current ratings at other temperatures.
EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring
track widths. Derate current values at -0.61 %/°C for ambient temperatures above 25 °C. See Figure 8 for current ratings at other
durations.
Electrical Characteristics, TA = 25 °C (Unless Otherwise Noted)
Parameter
IDRM
V(BO)
V(BO)
Repetitive peak off-state current
Breakover voltage
Impulse breakover voltage
Test Conditions
Min Typ Max
Unit
TA = 25 °C
TA = 85 °C
-5
-10
μA
dv/dt = -250 V/ms, RSOURCE = 300 Ω
'5070H3BJ
'5080H3BJ
'5095H3BJ
'5110H3BJ
'5115H3BJ
'5150H3BJ
'5190H3BJ
-70
-80
-95
-110
-115
-150
-190
V
dv/dt ≥ -1000 V/μs, Linear voltage ramp,
Maximum ramp value = -500 V
di/dt = -20 A/μs, Linear current ramp,
Maximum ramp value = -10 A
'5070H3BJ
'5080H3BJ
'5095H3BJ
'5110H3BJ
'5115H3BJ
'5150H3BJ
'5190H3BJ
-80
-90
-105
-120
-125
-160
-200
V
VD = VDRM
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
Electrical Characteristics, TA = 25 °C (Unless Otherwise Noted)
Parameter
I(BO)
Breakover current
VF
Forward voltage
Test Conditions
dv/dt = -250 V/ms, RSOURCE = 300 Ω
Min Typ Max
Unit
-150
-600
mA
3
V
5
V
IF = 5 A, tW = 500 μs
VFRM
Peak forward recovery voltage
VT
On-state voltage
dv/dt ≤ +1000 V/μs, Linear voltage ramp,
Maximum ramp value = +500 V
di/dt = +20 A/μs, Linear current ramp,
Maximum ramp value = +10 A
IT = -5 A, tw = 500 μs
IH
Holding current
IT = -5 A, di/dt = +30 mA/ms
-150
CO
NOTE:
Off-state current
Off-state capacitance
(see Note 6)
V
mA
-5
dv/dt Critical rate of rise of off-state voltage Linear voltage ramp, maximum ramp value < 0.85VDRM
ID
-3
-600
kV/μs
VD = -50 V
TA = 85 °C
-10
f = 1 MHz, Vd = 1 V rms, VD = -1 V
'5070H3BJ
'5080H3BJ
'5095H3BJ
'5110H3BJ
'5115H3BJ
'5150H3BJ
'5190H3BJ
300
280
260
240
214
140
140
420
390
365
335
300
195
195
f = 1 MHz, Vd = 1 V rms, VD = -2 V
'5070H3BJ
'5080H3BJ
'5095H3BJ
'5110H3BJ
'5115H3BJ
'5150H3BJ
'5190H3BJ
260
245
225
205
180
120
120
365
345
315
285
250
170
170
f = 1 MHz, Vd = 1 V rms, VD = -50 V
'5070H3BJ
'5080H3BJ
'5095H3BJ
'5110H3BJ
'5115H3BJ
'5150H3BJ
'5190H3BJ
90
80
73
65
56
35
35
125
110
100
90
80
50
50
f = 1 MHz, Vd = 1 V rms, VD = -100 V
'5150H3BJ
'5190H3BJ
30
30
40
30
μA
pF
6. Up to 10 MHz the capacitance is essentially independent of frequency. Above 10 MHz the effective capacitance is strongly
dependent on connection inductance.
Thermal Characteristics, TA = 25 °C (Unless Otherwise Noted)
Parameter
RθJA
Junction to ambient thermal resistance
Test Conditions
265 mm x 210 mm populated line card,
4-layer PCB, IT = ITSM(1000)
NOTE:
Min
Typ
EIA/JESD51-3 PCB, IT = ITSM(1000)
(see Note 7)
Max
Unit
113
°C/W
50
7. EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
Parameter Measurement Information
+i
Quadrant I
Forward
Conduction
Characteristic
IPPSM
IFSM
IFRM
IF
VF
V (BR)M
VD
V DRM
-v
I(BR)
V (BR)
ID
IDRM
+v
IH
I(BO)
VT
V(BO)
IT
ITRM
ITSM
Quadrant III
IPPSM
Switching
Characteristic
-i
PM-TISP5xxx-001-a
Figure 1. Voltage-Current Characteristic for Terminal Pair
All Measurements are Referenced to the Thyristor Anode, A (Pin 1)
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
Typical Characteristics
OFF-STATE CURRENT
vs
JUNCTION TEMPERATURE
TC5XAFA
1.10
100
Normalized Breakover Voltage
ID - Off-State Current - μA
10
1
0·1
VD = -50 V
0·01
NORMALIZED BREAKOVER VOLTAGE
vs
JUNCTION TEMPERATURE
TC5XAIA
1.05
1.00
0.95
0·001
-25
0
25
50
75
100
125
-25
150
Figure 2.
tW = 100 μs
2.0
50
40
30
20
15
10
7
VF
VT
2
1.5
1
0.7
TC5LAC
75
100
125
150
TC5XAD
1.5
70
5
4
3
50
NORMALIZED HOLDING CURRENT
vs
JUNCTION TEMPERATURE
Normalized Holding Current
IT , IF - On-State Current, Forward Current - A
TA = 25 °C
100
25
Figure 3.
ON-STATE AND FORWARD CURRENTS
vs
ON-STATE AND FORWARD VOLTAGES
200
150
0
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
1.0
0.9
0.8
0.7
0.6
0.5
1
1.5
2
3
4 5
7
10
VT , VF- On-State Voltage, Forward Voltage - V
Figure 4.
0.4
-25
0
25
50
75
100
125
TJ - Junction Temperature - °C
150
Figure 5.
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
Typical Characteristics
300
150
100
90
80
70
60
'5070
'5080
'5095
'5110
'5115
50
'5150 &
'5190
40
30
1
2
3
5
10
20 30
50
V D - Negative Off-state Voltage - V
Figure 6.
100
'5115
'5110
'5095
'5080
180
'5070
TJ = 25 °C
V d = 1 Vrms
C - Differential Off-State Capacitance - pF
Coff - Capacitance - pF
TC5XAEB
190
200
20
DIFFERENTIAL OFF-STATE CAPACITANCE
vs
RATED REPETITIVE PEAK OFF-STATE VOLTAGE
'5150
OFF-STATE CAPACITANCE
vs
OFF-STATE VOLTAGE TC5XABBa
170
160
150
C = Coff(-2 V) - Coff(-50 V)
140
130
120
110
100
90
80
58 65
75 80
90
120
VDRM - Negative Repetitive Peak Off-State Voltage - V
Figure 7.
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
ITSM(t) - Non-Repetitive Peak On-State Current - A
Rating and Thermal Information
30
NON-REPETITIVE PEAK ON-STATE CURRENT
vs
CURRENT DURATION
TI5HAC
VGEN = 600 Vrms, 50/60 Hz
RGEN = 1.4*VGEN/ITSM(t)
20
EIA/JESD51-2 ENVIRONMENT
EIA/JESD51-3 PCB
TA = 25 °C
15
10
9
8
7
6
5
4
3
2
1.5
0·1
1
10
100
1000
t - Current Duration - s
Figure 8.
VDRM DERATING FACTOR
vs
MINIMUM AMBIENT TEMPERATURE
1.00
IMPULSE RATING
vs
AMBIENT TEMPERATURE
TI5XAD
700
600
0.99
BELLCORE 2/10
500
IEC 1.2/50, 8/20
400
Impulse Current - A
0.98
Derating Factor
TC5XAA
0.97
0.96
300
FCC 10/160
250
ITU-T 10/700
200
FCC 10/560
150
0.95
120
0.94
0.93
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25
TAMIN - Minimum Ambient Temperature - °C
Figure 9.
BELLCORE 10/1000
100
90
80
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TA - Ambient Temperature - °C
Figure 10.
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
APPLICATIONS INFORMATION
Deployment
These devices are two terminal overvoltage protectors. They may be used either singly to limit the voltage between two points (Figure 11) or in
multiples to limit the voltage at several points in a circuit (Figure 12).
SIGNAL
AI4XAC
R1a
R1b
TISP5xxxH3BJ
- D.C.
Figure 11. Power Supply Protection
In Figure 11, the TISP5xxxH3BJ limits the maximum voltage of the negative supply to -V(BO) and +VF. This configuration can be used for
protecting circuits where the voltage polarity does not reverse in normal operation. In Figure 12, the two TISP5xxxH3BJ protectors, Th4 and
Th5, limit the maximum voltage of the SLIC (Subscriber Line Interface Circuit) outputs to -V(BO) and +VF. Ring and test protection is given by
protectors Th1, Th2 and Th3. Protectors Th1 and Th2 limit the maximum tip and ring wire voltages to the ±V(BO) of the individual protector.
Protector Th3 limits the maximum voltage between the two conductors to its ±V(BO) value. If the equipment being protected has all its
vulnerable components connected between the conductors and ground, then protector Th3 is not required.
OVERCURRENT
PROTECTION
TIP
WIRE
RING/TEST
PROTECTION
TEST
RELAY
RING
RELAY
SLIC
RELAY
SLIC
PROTECTION
TISP5xxxH3BJ
S3a
R1a
Th1
Th4
S2a
S1a
SLIC
Th3
Th2
RING
WIRE
Th5
R1b
S3b
S1b
TEST
EQUIPMENT
S2b
VBAT
RING
GENERATOR
AI4XAA
Figure 12. Line Card SLIC Protection
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
APPLICATIONS INFORMATION (CONTINUED)
The star-connection of three TISP5xxxH3BJ protectors gives a protection circuit which has a low differential capacitance to ground (Figure 13).
This example, a -100 V ISDN line is protected. In Figure 13, the circuit illustration A shows that protector Th1 will be forward biased as it is
connected to the most negative potential. The other two protectors, Th2 and Th3 will be reverse biased as protector Th1 will pull their common
connection to within 0.5 V of the negative voltage supply.
C0.5 V
600 pF
Th1
Th3
26 pF
29 pF
26 pF
SIGNAL
C-99.5 V
29 pF
Th2
A) STAR-CONNECTED
U-INTERFACE
PROTECTOR
- 100 V
C-99.5 V
1 pF
B) EQUIVALENT
TISP5150H3BJ
CAPACITANCES
- 100 V
C) DELTA EQUIVALENT
SHOWS 25 pF
LINE UNBALANCE
- 100 V
AI4XAB
Figure 13. ISDN Low Capacitance U-Interface Protection
Illustration B shows the equivalent capacitances of the two reverse biased protectors (Th2 and Th3) as 29 pF each and the capacitance of
the forward biased protector (Th1) as 600 pF. Illustration C shows the delta equivalent of the star capacitances of illustration B. The protector
circuit differential capacitance will be 26 - 1 = 25 pF. In this circuit, the differential capacitance value cannot exceed the capacitance value of the
ground protector (Th3).
A bridge circuit can be used for low capacitance differential. Whatever the potential of the ring and tip conductors are in Figure 14, the array of
steering diodes, D1 through to D6, ensure that terminal 1 of protector Th1 is always positive with respect to terminal 2. The protection voltage
will be the sum of the protector Th1, V(BO), and the forward voltage of the appropriate series diodes. It is important to select the correct diodes.
Diodes D3 through to D6 divert the currents from the ring and tip lines. Diodes D1 and D2 will carry the sum of the ring and tip currents and
so conduct twice the current of the other four diodes. The diodes need to be specified for forward recovery voltage, VFRM, under the expected
impulse conditions. (Some conventional a.c. rectifiers can produce as much as 70 V of forward recovery voltage, which would be an extra 140 V
added to the V(BO) of Th1). In principle the bridge circuit can be extended to protect more than two conductors by adding extra legs to the bridge.
RING
1
TIP
D1
D3
D5
D2
D4
D6
2 Th1
AI5XAC
Figure 14. Low Capacitance Bridge Protection Circuit
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
APPLICATIONS INFORMATION
ISDN Device Selection
The ETSI Technical Report ETR 080:1993 defines several range values in terms of maximum and minimum ISDN feeding voltages. The
following table shows that ranges 1 and 2 can use a TISP5110H3BJ protector and ranges 3 to 5 can use a TISP5150H3BJ protector.
Feeding Voltage
Maximum
V
Standoff Voltage
VDRM
V
51
69
-75
TISP5095H3BJ
66
70
-80
TISP5110H3BJ
-120
TISP5150H3BJ
Range
Minimum
V
1
2
3
91
99
4
90
110
5
105
115
Device Name
Impulse Testing
To verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various impulse wave forms.
The table below shows some common values.
Peak Voltage
Setting
V
Voltage
Waveshape
μs
Peak Current
Value
A
2500
2/10
1000
10/1000
1500
800
Current
Waveshape
μs
TISP5xxxH3BJ
25 °C Rating
A
500
2/10
500
100
10/1000
100
10/160
200
10/160
250
0
10/560
100
10/560
160
0
1500
9/720 †
37.5
5/320 †
200
0
1000
9/720 †
25
5/320 †
200
0
I3124
1500
0.5/700
37.5
0.2/310
200
0
ITU-T K.20/21/45
1500
4000
6000
10/700
37.5
100
150
5/310
200
0
Standard
GR-1089-CORE
TIA-968-A
Series
Resistance
Ω
0
† TIA-968-A terminology for the waveforms produced by the ITU-T recommendation K.21 10/700 impulse generator.
If the impulse generator current exceeds the protector’s current rating then a series resistance can be used to reduce the current to the protector’s
rated value and so prevent possible failure. The required value of series resistance for a given waveform is given by the following calculations.
First, the minimum total circuit impedance is found by dividing the impulse generator’s peak voltage by the protector’s rated current. The impulse
generator’s fictive impedance (generator’s peak voltage divided by peak short circuit current) is then subtracted from the minimum total circuit
impedance to give the required value of series resistance. In some cases the equipment will require verification over a temperature range. By
using the rated waveform values from Figure 10, the appropriate series resistor value can be calculated for ambient temperatures in the range of
-40 °C to 85 °C.
If the devices are used in a star-connection, then the ground return protector, Th3 in Figure 13, will conduct the combined current of protectors
Th1 and Th2. Similarly in the bridge connection (Figure 14), the protector Th1 must be rated for the sum of the conductor currents. In these
cases, it may be necessary to include some series resistance in the conductor feed to reduce the impulse current to within the protector’s ratings.
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP5xxxH3BJ Overvoltage Protection Series
APPLICATIONS INFORMATION
AC Power Testing
The protector can withstand currents applied for times not exceeding those shown in Figure 8. Currents that exceed these times must be
terminated or reduced to avoid protector failure. Fuses, PTC (Positive Temperature Coefficient) resistors and fusible resistors are overcurrent
protection devices which can be used to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one ampere.
In some cases it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. The current versus
time characteristic of the overcurrent protector must be below the line shown in Figure 8. In some cases there may be a further time limit
imposed by the test standard (e.g. UL 1459 wiring simulator failure).
Capacitance
The protector characteristic off-state capacitance values are given for d.c. bias voltage, VD, values of -1 V, -2 V and -50 V. The TISP5150H3BJ
and TISP5190H3BJ are also given for a bias of -100 V. Values for other voltages may be determined from Figure 6. Up to 10 MHz, the
capacitance is essentially independent of frequency. Above 10 MHz, the effective capacitance is strongly dependent on connection inductance.
In Figure 12, the typical conductor bias voltages will be about -2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance
caused by biasing one protector at -2 V and the other at -50 V. For example, the TISP5070H3BJ has a differential capacitance value of 166 pF
under these conditions.
Normal System Voltage Level
The protector should not clip or limit the voltages that occur in normal system operation. Figure 9 allows the calculation of the protector VDRM
value at temperatures below 25 °C. The calculated value should not be less than the maximum normal system voltages. The TISP5150H3BJ,
with a VDRM of -120 V, can be used to protect ISDN feed voltages having maximum values of -99 V, -110 V and -115 V (range 3 through to range
5). These three range voltages represent 0.83 (99/120), 0.92 (110/120) and 0.96 (115/120) of the -120 V TISP5150H3BJ VDRM. Figure 9 shows
that the VDRM will have decreased to 0.944 of its 25 °C value at -40 °C. Thus, the supply feed voltages of -99 V (0.83) and -110 V (0.92) will not
be clipped at temperatures down to -40 °C. The -115 V (0.96) feed supply may be clipped if the ambient temperature falls below -21 °C.
JESD51 Thermal Measurement Method
To standardize thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51 standard. Part 2 of the standard
(JESD51-2, 1995) describes the test environment. This is a 0.0283 m3 (1 ft3 ) cube which contains the test PCB (Printed Circuit Board)
horizontally mounted at the center. Part 3 of the standard (JESD51-3, 1996) defines two test PCBs for surface mount components; one for
packages smaller than 27 mm on a side and the other for packages up to 48 mm. The SMB (DO-214AA) measurements used the smaller 76.2
mm x 114.3 mm (3.0 ” x 4.5 ”) PCB. The JESD51-3 PCBs are designed to have low effective thermal conductivity (high thermal resistance) and
represent a worse case condition. The PCBs used in the majority of applications will achieve lower values of thermal resistance and so can
dissipate higher power levels than indicated by the JESD51 values.
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www.bourns.com
“TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in the U.S. Patent and Trademark Office.
“Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries.
JANUARY 1998 – REVISED JULY 2019
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
Legal Disclaimer Notice
This legal disclaimer applies to purchasers and users of Bourns® products manufactured by or on behalf of Bourns, Inc. and
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Unless otherwise expressly indicated in writing, Bourns® products and data sheets relating thereto are subject to change
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