TISP61089QBDR-S

TISP61089QB PROGRAMMABLE OVERVOLTAGE PROTECTOR QUAD FORWARD-CONDUCTING P-GATE THYRISTOR TISP61089QB SLIC Overvoltage Protector Quad Voltage-Programmable Protector - Wide -20 V to -155 V Programming Range - Low 5 mA max. Gate Triggering Current - High 150 mA min. Holding Current - Rated for ITU-T and YD/T-950 10/700 impulses - Rated for Telcordia Intra-building impulses Additional Information Click these links for more information: PRODUCT TECHNICAL INVENTORY SAMPLES SELECTOR LIBRARY CONTACT 10/700 Protection Voltage Specified D Package (Top View) Element Protection Level 40 A, 5/310 Diode +12 Crowbar VGG = -48 V 1 8 K2 G1,G2 2 7 A G3,G4 3 6 A 4 5 K4 K1 -64 K3 .................................................UL Recognized Component MDRXAN Device Symbol K1 Description Bourns® TISP61089QB is a quad forward-conducting buffered p-gate overvoltage protector. It is designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The TISP61089QB limits voltages that exceed the SLIC supply rail voltage. The TISP61089QB parameters are specified to allow equipment compliance with Telcordia GR-1089-CORE Intra-building, ITU-T K.20, K.21 and K.45 and YD/T-950. G1,G2 K2 A The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region of -20 V to -155 V. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. As the protection voltage will then track the negative supply voltage the overvoltage stress on the SLIC is minimized. A K3 G3,G4 Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition. As the overvoltage subsides, the high holding current of the crowbar helps prevent d.c. latchup. SDRXAIA K4 These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high reliability and are virtually transparent in normal operation. The TISP61089QB buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction. The TISP61089QB is available in an 8-pin plastic small-outline surface mount package. How to Order Device Package TISP61089QB 8 Pin Small Outline (D008) Carrier Embossed Tape Reeled Order As Marking Code TISP61089QBDR-S 1089QB Standard Quantity 2500 JULY 2010 – REVISED AUGUST 2016 WARNING Cancer and Reproductive Harm www.P65Warnings.ca.gov *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089QB SLIC Overvoltage Protector Absolute Maximum Ratings, TJ = 25 °C (Unless Otherwise Noted) Rating Symbol Value VDRM -170 V -40 °C ≤ TJ ≤ 85 °C VGKRM -167 V Repetitive peak off-state voltage, IG = 0 -40 °C ≤ TJ ≤ 85 °C Repetitive peak gate-cathode voltage, VKA = 0 U nit Non-repetitive peak on-state pulse current (see Notes 1 and 2) 10/1000 μs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) 5/310 μs (ITU-T K.20/21/45, YD/T-950, open circuit voltage waveshape 10/700) 8/20 μs (ITU-T K.44, May 2012, Appendix A.3-4) 2/40 μs (IEC61000-4-5, 1.2/50 μs open circuit voltage, 2 ohm + 10 ohm, see Note 4) 2/10 μs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) 30 40 60 85 120 ITSP Non-repetitive peak on-state current, 60 Hz (see Notes 1, 2 and 3) ITSM 900 s Non-repetitive peak gate current, 2/10 μs pulse, cathodes commoned (see Notes 1 and 2) A A 0.5 IGSM 40 A TJ -40 to +150 °C Tstg -40 to +150 °C Junction temperature Storage temperature range NOTES: 1. Initially the protector must be in thermal equilibrium with TJ = 25 °C. The surge may be repeated after the device returns to its initial conditions. 2. These non-repetitive rated currents are peak values for either polarity. The rated current values may be applied to any cathodeanode terminal pair. Additionally, all cathode-anode terminal pairs may have their rated current values applied simultaneously (in this case the anode terminal current will be four times the rated current value of an individual terminal pair). 3. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. 4. Combination wave generator as specified in ITU-T K.20, K.21, K.44. Recommended Operating Conditions Min CG Gate decoupling capacitor Typ Max 100 Unit nF Electrical Characteristics, TJ = 25 °C (Unless Otherwise Noted) Parameter ID Off-state current V(BO) Breakover voltage VF Forward voltage VFRM Peak forward recovery voltage Max Unit VD = VDRM, VGK = 0 Test Conditions Min Typ -5 μA 10/700 μs, IT = -40 A, RS = 55 Ω, VGG = -48 V, CG = 100 nF -64 V 3 V IF = 5 A, tw = 200 μs 10/700 μs, IF = 40 A, RS = 55 Ω, VGG = -48 V, CG = 100 nF 12 IH Holding current IGAS Gate reverse current VGG = VGK = VGKRM, VKA = 0 -5 μA IGT Gate trigger current IT = 3 A, tp(g) ≥ 20 μs, VGG = -100 V 5 mA Gate trigger voltage IT = 3 A, tp(g) ≥ 20 μs, VGG = -100 V 2.5 V VGT CAK NOTE: IT = -1 A, di/dt = 1 A/ms, VGG = -100 V V Anode-cathode off-state f = 1 MHz, Vd = 1 V IG = 0, (see Note 5) capacitance - 150 mA VD = -3 V 100 VD = -48 V 50 pF 5. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. JULY 2010 – REVISED AUGUST 2016 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089QB SLIC Overvoltage Protector Thermal Characteristics Parameter RθJA Junction to free air thermal resistance Test Conditions Ptot = 0.8 W, TA = 25 °C 5 cm2, FR4 PCB Min Typ Max Unit 160 °C/W Parameter Measurement Information JULY 2010 – REVISED AUGUST 2016 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089QB SLIC Overvoltage Protector Applications Information Typical Applications Circuit Figure 2 shows a typical TISP61089QB SLIC card protection circuit. The incoming line conductors, RING1/RING2 and TIP1/TIP2, connect to the relay matrix via the series overcurrent protection. Positive temperature coefficient (PTC) thermistors can be used for overcurrent protection. The resistance of the PTC thermistor will reduce the prospective current from the surge generator for the TISP61089QB. -V BAT1 MF-SD013/250 100nF TIP1 SLIC #1 RING1 TISP61089QB TIP2 SLIC #2 RING2 GND -V BAT2 100nF MF-SD013/250 Asia-Pacific: Tel: +886-2 2562-4117 • Email: asiacus@bourns.com EMEA: Tel: +36 88 885 877 • Email: eurocus@bourns.com The Americas: Tel: +1-951 781-5500 • Email: americus@bourns.com www.bourns.com “TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in the U.S. Patent and Trademark Office. “Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries. JULY 2010 – REVISED AUGUST 2016 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. Legal Disclaimer Notice This legal disclaimer applies to purchasers and users of Bourns® products manufactured by or on behalf of Bourns, Inc. and P[ZHɉSPH[LZJVSSLJ[P]LS`¸)V\YUZ¹ Unless otherwise expressly indicated in writing, Bourns® products and data sheets relating thereto are subject to change ^P[OV\[UV[PJL