BS616LV1012EIG70

BSI FEATURES Very Low Power/Voltage CMOS SRAM 64K X 16 bit DESCRIPTION BS616LV1012 • Wide Vcc operation voltage : 2.4 ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade : 22mA (@55ns) operating current I- grade : 23mA (@55ns) operating current C-grade : 17mA (@70ns) operating current I- grade : 18mA (@70ns) operating current 0.4uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin The BS616LV1012 is a high performance, very low power CMOS Static Random Access Memory organized as 65,536 words by 16 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.4uA at 3V/25oC and maximum access time of 55ns at 3V/85oC. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV1012 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1012 is available in the JEDEC standard 44-pin TSOP Type II and 48-pin BGA package. PRODUCT FAMILY PRODUCT FAMILY BS616LV1012EC BS616LV1012AC BS616LV1012EI BS616LV1012AI OPERATING TEMPERATURE Vcc RANGE SPEED (ns) 55ns:2.8~3.6V 70ns:2.5~3.6V POWER DISSIPATION STANDBY Operating (ICCSB1, Max) (ICC, Max) PKG TYPE Vcc=3.0V Vcc=3.0V 55ns Vcc=3.0V 70ns +0 C to +70 C O O 2.4V ~ 3.6V 55/70 1.3uA 22mA 17mA TSOP2-44 BGA-48-0608 TSOP2-44 BGA-48-0608 -40 C to +85 C O O 2.4V ~ 3.6V 55/70 2.5uA 23mA 18mA PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 6 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC BLOCK DIAGRAM A8 A13 A15 A14 A12 A7 A6 A5 A4 Address Input Buffer BS616LV1012EC BS616LV1012EI 18 Row Decoder 512 Memory Array 512 x 2048 2048 DQ0 16 Data Input Buffer 16 Column I/O 2 3 4 5 A LB OE A0 A1 A2 NC . . . . DQ15 . . . . Write Driver Sense Amp 128 Column Decoder 16 Data Output 16 Buffer B IO8 UB A3 A4 CE IO0 C IO9 IO10 A5 A6 IO1 IO2 CE WE OE UB LB Control 14 Address Input Buffer D VSS IO11 NC A7 IO3 VCC E VCC IO12 NC NC IO4 VSS A11 A9 A3 A2 A1 A0 A10 F IO14 IO13 A14 A15 IO5 IO6 Vcc Gnd G IO15 NC A12 A13 WE IO7 H NC A8 A9 A10 A11 NC Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616LV1012 1 Revision 1.0 Apr. 2004 BSI PIN DESCRIPTIONS BS616LV1012 Name A0-A15 Address Input CE Chip Enable Input Function These 16 address inputs select one of the 65,536 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read CE H L L WE X H H OE X H L LB X X L H L L Write L L X H L UB X X L L H L L H DQ0~DQ7 High Z High Z Dout High Z Dout Din X Din DQ8~DQ15 High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC R0201-BS616LV1012 2 Revision 1.0 Apr. 2004 BSI ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM V cc T BIAS T STG PT I OUT PARAMETER Terminal Voltage with Respect to GND Power Supply Voltage Temperature Under Bias Storage Temperature Power Dissipation DC Output Current BS616LV1012 OPERATING RANGE UNITS V V O RATING -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 C to +70 C -40 C to +85 C O O O O Vcc 2.4V ~ 3.6V 2.4V ~ 3.6V C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS M AX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC (6) PARAMETER Guaranteed Input Low (2) Voltage Guaranteed Input High (3) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL TEST CONDITIONS Vcc=3.0V MIN. TYP. -0.5 2.0 ---------0.4 (1) MAX. 0.8 Vcc+0.3 1 1 0.4 -23 18 1 2.5 UNITS V V uA uA V V mA mA uA Vcc=3.0V Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = V , or OE = V , VI/O = 0V to Vcc IH IH -Vcc=3.0V Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE = V , I IL DQ -2.4 ---- Vcc=3.0V = 0mA, 55ns 70ns F = Fmax (4) Vcc=3.0V ICCSB (5) CE = VIH, IDQ = 0mA CE ≧ Vcc -0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc=3.0V ICCSB1 Standby Current-CMOS Vcc=3.0V 1. Typical characteristics are at TA = 25oC. 3. Overshoot : Vcc+1.5V in case of pulse width ≦20ns. 5. IccsB1_Max. is 1.3uA at Vcc=3.0V and TA=70oC. 2. Undershoot : -1.5V in case of pulse width ≦20ns. 4. Fmax = 1/tRC . 6. Icc_Max. is 22mA(@55ns) / 17mA(@70ns) at Vcc=3.0V and TA=0~70oC. DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC ) SYMBOL VDR ICCDR tCDR tR (3) PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time O TEST CONDITIONS CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V See Retention Waveform MIN. 1.5 -0 TRC (2) TYP. (1) -0.15 --- MAX. -0.8 --- UNITS V uA ns ns 1. Vcc = 1.5V, TA = + 25 C 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.45uA at TA=70OC. R0201-BS616LV1012 3 Revision 1.0 Apr. 2004 BSI LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode BS616LV1012 Vcc VIH Vcc VDR ≥ 1.5V Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load , AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 55ns CYCLE TIME : 70ns (Vcc = 2.5~3.6V) DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change (Vcc = 2.8~3.6V) MIN. TYP. MAX. UNIT -ns ns ns ns ns ns ns ns ns ns ns ns MIN. TYP. MAX. tAVAX tAVQV tELQV tBA tGLQV t E1LQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX tRC tAA tACS tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH 55 --(LB,UB) --10 (LB,UB) 10 5 -(LB,UB) --10 ------------- -55 55 25 25 ---20 20 20 -- 70 ----10 10 5 ---10 ------------- 70 70 35 35 ---25 25 25 -- NOTE : 1. tBA is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle. R0201-BS616LV1012 4 Revision 1.0 Apr. 2004 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS616LV1012 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE D OUT t (5) CLZ t BDO t (5) CHZ READ CYCLE3 (1,4) t ADDRESS RC t OE AA t OE CE t OH t OLZ t CLZ (5) t ACS t OHZ (5) (1,5) t CHZ t BA LB,UB t BE D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. t BDO R0201-BS616LV1012 5 Revision 1.0 Apr. 2004 BSI AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 55ns BS616LV1012 DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (Vcc = 2.8~3.6V) CYCLE TIME : 70ns (Vcc = 2.5~3.6V) MIN. TYP. MAX. MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW 55 55 0 55 35 (CE,WE) (LB,UB) 0 35 -35 0 -5 ------------- -------25 --20 -- 70 70 0 70 45 0 45 -40 0 -5 ------------- -------30 --25 -- NOTE : 1. tBW is 35ns/45ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t WR OE (3) t CW CE (5) (11) t BW LB,UB t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t t DW DH D IN R0201-BS616LV1012 6 Revision 1.0 Apr. 2004 BSI WRITE CYCLE2 (1,6) BS616LV1012 t WC ADDRESS t CW CE (5) (11) t BW LB,UB t AW WE t WR t WP (2) (3) t AS (4,10) t WHZ D OUT t t DW t OW (7) (8) DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS616LV1012 7 Revision 1.0 Apr. 2004 BSI ORDERING INFORMATION BS616LV1012 BS616LV1012 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP2-44 R0201-BS616LV1012 8 Revision 1.0 Apr. 2004 BSI PACKAGE DIMENSIONS (continued) NOTES: BS616LV1012 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 48 mini-BGA (6 x 8) E1 R0201-BS616LV1012 9 Revision 1.0 Apr. 2004