74ACT16861DL

54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996 D D D D D D D D Members of the Texas Instruments Widebus  Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Shrink Plastic Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’ACT16861 are noninverting 20-bit transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. The ’ACT16861 can be used as two 10-bit transceivers or one 20-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. 54ACT16861 . . . WD PACKAGE 74ACT16861 . . . DL PACKAGE (TOP VIEW) 1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 1B7 GND 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2B9 2B10 2OEAB 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 1A10 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 2A10 2OEBA The 74ACT16861 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16861 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16861 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996 FUNCTION TABLE (each 10-bit section) INPUTS OEAB OEBA L L OPERATION Latch A and B (A = B) L H A to B H L B to A H H Isolation logic symbol† 56 1OEBA 1OEAB 1 29 2OEBA 2OEAB 1A1 28 55 EN1 EN2 EN3 EN4 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 3 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 15 1 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 POST OFFICE BOX 655303 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2B1 4 41 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1B1 2 54 1 2A2 2 1 • DALLAS, TEXAS 75265 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996 logic diagram (positive logic) 1OEBA 1OEAB 1A1 56 2OEBA 1 2OEAB 55 2 1B1 2A1 29 28 42 15 To Nine Other Channels 2B1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA Maximum power package dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. recommended operating conditions (see Note 3) 54ACT16861 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v Low-level output current High-level input voltage 74ACT16861 2 2 0.8 High-level output current VCC VCC 0 0 –24 24 Input transition rise or fall rate TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. UNIT V V 0.8 V VCC VCC V –24 mA V 24 mA 0 10 0 10 ns/V –55 125 –40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 µA VOH 24 mA IOH = –24 IOH = –75 mA† II IOZ‡ A or B ports ICC VO = VCC or GND VI = VCC or GND, Control inputs MIN IO = 0 VI = VCC or GND VO = VCC or GND MAX 74ACT16861 MIN 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 0.1 0.1 MAX UNIT V 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 µA 5.5 V One input at 3.4 V, Other inputs at VCC or GND ∆ICC§ Ci IOL = 75 mA† VI = VCC or GND 54ACT16861 4.4 4.5 V IOL = 24 mA Control inputs TA = 25°C TYP MAX 5.5 V IOL = 50 µA VOL MIN V 5.5 V ±0.1 5.5 V ±0.5 ±5 ±5 µA 5.5 V 8 80 80 µA 5.5 V 0.9 1 1 mA 5V 4.5 pF Cio A or B ports 5V 17 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OEBA or OEAB A or B tPHZ tPLZ OEBA or OEAB A or B MIN TA = 25°C TYP MAX 54ACT16861 74ACT16861 MIN MAX MIN MAX 3.1 6.5 9.2 3.1 10.4 3.1 10.4 2.9 7.5 10 2.9 11.1 2.9 11.1 2.4 6.6 9 2.4 10 2.4 10 3.7 8.5 11.5 3.7 12.7 3.7 12.7 4.9 7.4 9.8 4.9 10.7 4.9 10.7 4.5 6.9 9.3 4.5 10 4.5 10 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF CL = 50 pF, f = 1 MHz TYP 64 14 UNIT pF 54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS197B – JUNE 1990 – REVISED NOVEMBER 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V Input 1.5 V 1.5 V 0V tPHL tPLH In-Phase Output 50% VCC 50% VCC 0V tPZL VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note B) [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output VOH 50% VCC VOL 3V 1.5 V 1.5 V 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74ACT16861DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16861 Samples 74ACT16861DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16861 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of