SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
FEATURES
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), and Thin Very Small-Outline (DGV)
Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR, and the DGVR package is abbreviated
to VR.
DESCRIPTION
This 18-bit universal bus driver is designed for 1.65-V
to 3.6-V VCC operation.
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
high. When LE is low, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
SCES121F – JULY 1997 – REVISED OCTOBER 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC − No internal connection
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162835 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
FUNCTION TABLE
INPUTS
(1)
OE
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
L or H
X
Y0 (1)
Output level before the indicated steady-state input conditions were
established
xxx
xxx
LOGIC SYMBOL(1)
OE
CLK
LE
27
EN1
30
2C3
28
C3
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
3
5
1
1
3D
54
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
CLK
LE
A1
27
30
28
54
1D
3
C1
Y1
CLK
To 17 Other Channels
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
4.6
V
VI
Input voltage range (2)
-0.5
4.6
V
VO
Output voltage range (2) (3)
-0.5 VCC + 0.5
V
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Tstg
(1)
(2)
(3)
(4)
Package thermal impedance (4)
Storage temperature range
DGG package
81
DGV package
86
DL package
74
-65
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
3
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
4
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
-2
VCC = 2.3 V
-6
VCC = 2.7 V
-8
mA
-12
VCC = 1.65 V
2
VCC = 2.3 V
6
VCC = 2.7 V
8
VCC = 3 V
(1)
V
0.35 × VCC
VCC = 3 V
IOL
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
12
-40
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
VOH
1.65 V to 3.6 V
II(hold)
MAX
1.2
IOH = -4 mA
2.3 V
1.9
2.3 V
1.7
3V
2.4
IOH = -8 mA
2.7 V
2
IOH = -12 mA
3V
2
IOL = 100 µA
V
1.65 V to 3.6 V
0.2
IOL = 2 mA
1.65 V
0.45
IOL = 4 mA
2.3 V
0.4
2.3 V
0.55
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 2 V
UNIT
VCC - 0.2
1.65 V
IOL = 6 mA
II
MIN TYP (1)
IOH = -2 mA
IOH = -6 mA
VOL
VCC
V
µA
µA
VI = 0 to 3.6 V (2)
3.6 V
±500
IOZ
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
µA
One input at VCC - 0.6 V,
Other inputs at VCC or GND
750
µA
∆ICC
Ci
Co
(1)
(2)
Control inputs
Data inputs
Outputs
3 V to 3.6 V
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
3.5
6
7
pF
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
5
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 1.8 V
MIN MAX
fclock
tw
tsu
th
(1)
Setup time
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN MAX
150
MIN
150
(1)
3.3
3.3
3.3
CLK high or low
(1)
3.3
3.3
3.3
Data before CLK↑
(1)
2.2
2.1
1.7
CLK high
(1)
1.9
1.6
1.5
CLK low
(1)
1.3
1.1
1
(1)
0.6
0.6
0.7
(1)
1.4
1.7
1.4
Data after CLK↑
Data after LE↓
CLK high or low
UNIT
MAX
150
LE high
Data before LE↓
Hold time
MIN MAX
(1)
Clock frequency
Pulse duration
VCC = 2.5 V
± 0.2 V
MHz
ns
ns
ns
This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
FROM
(INPUT)
PARAMETER
VCC = 1.8 V
TO
(OUTPUT)
MIN
(1)
fmax
tpd
LE
tdis
OE
MIN
150
150
MAX
MIN
UNIT
MAX
150
MHz
5
5
1
4.2
(1)
1.3
5.9
5.8
1.3
5.1
(1)
1.4
6.3
6.1
1.4
5.4
Y
(1)
1.4
6.3
6.5
1.1
5.5
ns
Y
(1)
1
4.7
4.9
1.3
4.5
ns
Y
OE
MIN MAX
1
CLK
ten
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
(1)
A
(1)
TYP
VCC = 2.5 V
± 0.2 V
ns
This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
from 0°C to 65°C, CL = 50 pF
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
CLK
Y
VCC = 3.3 V
± 0.15 V
UNIT
MIN
MAX
1.9
5
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd Power dissipation capacitance
(1)
6
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
36
41
(1)
12.5
14
UNIT
pF
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
PARAMETER MEASURE INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
7
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
PARAMETER MEASURE INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
SN74ALVCH162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES121F – JULY 1997 – REVISED OCTOBER 2004
PARAMETER MEASURE INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0V
tPLZ
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
20
74ALVCH162835DLG4
ACTIVE
SSOP
DL
56
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(Requires Login)
74ALVCH162835GRE4
ACTIVE
TSSOP
DGG
56
TBD
Call TI
Call TI
ACTIVE
TSSOP
DGG
56
TBD
Call TI
Call TI
SN74ALVCH162835DGGR
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
SN74ALVCH162835DGVR
OBSOLETE
TVSOP
DGV
56
TBD
Call TI
Call TI
SN74ALVCH162835DL
ACTIVE
SSOP
DL
56
SN74ALVCH162835GR
ACTIVE
TSSOP
DGG
56
Green (RoHS
& no Sb/Br)
TBD
Samples
CU NIPDAU Level-1-260C-UNLIM
74ALVCH162835GRG4
20
(3)
CU NIPDAU Level-1-260C-UNLIM
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2011
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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