SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
AO Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Open-Drain Outputs
(100 mA)
LVTTL Outputs (–12 mA/12 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGG OR DGV PACKAGE
(TOP VIEW)
IMODE1
AI1
AO1
GND
AI2
AO2
VCC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
VCC
AO7
AI7
GND
AO8
AI8
OMODE0
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
IMODE0
BIAS VCC
B1
GND
OEAB
B2
ERC
OEAB
B3
GND
CLKAB/LEAB
B4
B5
CLKBA/LEBA
GND
B6
OEBA
VCC
B7
LOOPBACK
GND
B8
VREF
OMODE1
description
The SN74GTLP22034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP
and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of
data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and
diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP’s reduced output swing ( VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
recommended operating conditions (see Notes 4 through 7)
VCC,
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
High-level output current
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
B port
Except B port and VREF
B port
Except B port
VREF+0.05
2
B port
V
V
V
VREF–0.05
0.8
Except B port
V
V
–18
mA
AO
–12
mA
AO
12
B port
100
Outputs enabled
10
–40
ns/V
µs/V
20
Operating free-air temperature
mA
85
°C
NOTES: 4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable but, generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
AO
VCC = 3.15 V,
VCC = 3.15 V to 3.45 V,
II = –18 mA
IOH = –100 µA
VCC = 3
3.15
15 V
IOH = –6 mA
IOH = –12 mA
VCC = 3
3.15
15 V
II‡
IOZ‡
ICC
VCC = 3.15 V
MAX
UNIT
–1.2
V
VCC–0.2
2.4
V
2
0.2
0.55
IOL = 12 mA
IOL = 10 mA
VOL
B port
TYP†
IOL = 100 µA
IOL = 6 mA
VCC = 3.15 V to 3.45 V,
AO
MIN
0.8
0.2
IOL = 64 mA
IOL = 100 mA
0.55
0.4
AI and
control inputs
VCC = 3.45 V,
VI = 0 or 5.5 V
±10
AO
VCC = 3.45 V,
VO = 0 to 5.5 V
±10
B port
VCC = 3.45 V, VREF within 0.6 V of VTT,
±10
AO or B port
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
VI (B port) = VTT or GND
VO = 0 to 2.3 V
Outputs high
AI
µA
µA
40
Outputs low
40
Outputs disabled
40
VCC = 3.45 V, One AI or control input at VCC – 0.6 V,
Other AI or control inputs at VCC or GND
∆ICC§
V
1.5
mA
mA
3.5
4.5
3.5
5.5
5
6
pF
Cio
B port
8.5
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
10
pF
Ci
VI = 3.15
3 15 V or 0
Control inputs
Co
AO
VO = 3.15 V or 0
VO = 1.5 V or 0
pF
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 5.5 V
VO = 0.5 V to 3 V,
10
µA
OEBA = VCC
±30
µA
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OEBA = VCC
±30
µA
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC
10
µA
±30
µA
IOZPD
VCC = 1.5 V to 0,
VCC = 0 to 3.15 V
BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC
±30
µA
5
mA
10
µA
ICC
(BIAS VCC)
VO
IO
VCC = 3.15 V to 3.45 V
VCC = 0,
VCC = 0,
BIAS VCC = 3
3.15
15 V to 3
3.45
45 V
V,
VO (B port) = 0 to 1.5
15V
BIAS VCC = 3.3 V,
IO = 0
VO (B port) = 0.6 V
BIAS VCC = 3.15 V to 3.45 V,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.95
–1
1.05
V
µA
9
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN
fclock
tw
tsu
th
10
Clock frequency
Pulse duration
Setup time
Hold time
POST OFFICE BOX 655303
CLKAB/LEAB or CLKBA/LEBA
2.8
AI before CLKAB↑
1.1
AI before CLKBA↑
1.4
B before CLKBA↑
1.3
AI before LEAB↓
1.3
AI before LEBA↓
2.1
B before LEBA↓
2.2
AI after CLKAB↑
0.3
AI after CLKBA↑
0.2
B after CLKBA↑
0.2
AI after LEAB↓
0.3
AI after LEBA↓
0
B after LEBA↓
0
• DALLAS, TEXAS 75265
MAX
UNIT
175
MHz
ns
ns
ns
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
MIN
TYP‡
MAX
175
AI
(buffer)
B
Sl
Slow
AI
(buffer)
B
F t
Fast
B
(buffer)
AO
–
LEAB
(latch mode)
B
Slo
Slow
LEAB
(latch mode)
B
F t
Fast
LEAB
(latch mode)
AO
–
LEBA
(latch mode)
AO
–
OEAB
B
Sl
Slow
OEAB
B
Fast
OEAB
B
Sl
Slow
OEAB
B
F t
Fast
OEBA
AO
–
OEBA
AO
–
CLKAB
(flip-flop mode)
B
Sl
Slow
CLKAB
(flip-flop mode)
B
F t
Fast
CLKAB
(flip-flop mode)
AO
–
CLKBA
(flip-flop mode)
AO
–
OMODE
B
Sl
Slow
OMODE
B
F t
Fast
IMODE
AO
–
tPHL
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
3
7.1
3
7
2
5.6
2
5.7
1
5.8
1
5.2
4.2
8.5
3.2
7.3
3.2
7.1
2.8
6.3
2
6.9
1.8
6.1
1
5.6
1
5
3.8
7.5
3.1
7
2.5
6
2.5
6
3.5
7.5
3
7.2
2.5
6
2.5
6
1
5.3
1
4.2
1
5.5
1
5.2
4.4
8.6
3.6
8
3.2
7.1
3.1
6.8
2
7.5
1.8
7
1
6
1
5.6
3.8
8.7
3.2
8.2
2.7
7
2.7
7
1
6
1
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
LOOPBACK
AO
–
tPLH
tPHL
AI
(loopback high)
AO
–
tr
Rise time,
time B-port
B port outputs (20% to 80%)
MIN
MAX
2.5
6.1
2
5.1
1
5.7
1
5.4
Slow
2.8
Fast
1.5
Rise time, AO (10% to 90%)
tf
TYP‡
UNIT
ns
ns
ns
5.5
Fall time
time, B
B-port
port outputs (80% to 20%)
Slow
3
Fast
1.8
Fall time, AO (90% to 10%)
ns
4.5
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)§
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tsk(LH)¶
tsk(HL)¶
AI
B
Slow
tsk(LH)¶
tsk(HL)¶
AI
tsk(LH)¶
tsk(HL)¶
CLKAB/LEAB
tsk(LH)¶
tsk(HL)¶
CLKAB/LEAB
B
AI
B
B
B
tsk(t)
k(t)¶
CLKAB/LEAB
B
Fast
Slow
Fast
MIN
TYP‡
MAX
0.5
1
0.5
1
0.4
0.9
0.4
0.9
0.5
1
0.5
1
0.4
0.9
0.4
0.9
Slow
1.4
2
Fast
0.6
1.4
Slow
1.8
2.5
Fast
0.9
1.8
UNIT
ns
ns
ns
ns
ns
† Slow (ERC = L) and Fast (ERC = H)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
§ Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
¶ tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
12.5 Ω
S1
Open
6V
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
From Output
Under Test
Test
Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
LOAD CIRCUIT FOR A OUTPUTS
tw
3V
3V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu
th
VOH
Data
Input
VM
VM
0V
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOH
Output
1V
1V
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(AI to B port)
1V
1V
0V
tPLH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
1.5 V
Input
Output
Control
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(AO)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to AO)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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• DALLAS, TEXAS 75265
13
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
.25”
ZO = 50 Ω
1”
1”
.25”
22 Ω
22 Ω
1.5 V
11 Ω
Conn.
Conn.
Conn.
Conn.
From Output
Under Test
1”
1”
1”
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 19
Slot 20
LL = 14 nH
Test
Point
CL = 18 pF
Drvr
Slot 1
Figure 2. High-Drive Test Backplane
14
POST OFFICE BOX 655303
Figure 3. High-Drive RLC Network
• DALLAS, TEXAS 75265
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
AI
(buffer)
B
Sl
Slow
tPLH
tPHL
AI
(buffer)
B
F t
Fast
tPLH
tPHL
LEAB
(latch mode)
B
Sl
Slow
tPLH
tPHL
LEAB
(latch mode)
B
Fast
tPLH
tPHL
CLKAB
(flip-flop mode)
B
Sl
Slow
tPLH
tPHL
CLKAB
(flip-flop mode)
B
F t
Fast
tPLH
tPHL
OMODE
B
Sl
Slow
tPLH
tPHL
OMODE
B
F t
Fast
TYP‡
5.7
5.2
3.7
tr
time B-port
B port outputs (20% to 80%)
Rise time,
tf
Fall time
time, B
B-port
port outputs (80% to 20%)
4.1
5.9
5.7
4.8
4.8
5.7
6.4
4.7
5.2
5.4
6
4.5
4.9
Slow
2
Fast
1.1
Slow
3.3
Fast
2.3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
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15
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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