SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Inputs Meet JEDEC HSTL Standard
JESD8-6
All Outputs Have Equivalent 25-Ω Series
Resistors
Packaged in Plastic Thin Shrink
Small-Outline Package
1Q2
2Q1
1Q1
GND
D1
D2
D3
VCC
D4
D5
D6
GND
D7
1LE
VCC
VREF
GND
GND
2LE
D8
GND
D9
D10
D11
VCC
D12
D13
D14
GND
1Q14
2Q14
1Q13
description
This 14-bit to 28-bit D-type latch is designed for
3.15-V to 3.45-V VCC operation. HSTL levels are
expected on the inputs. LVTTL levels are driven
on the Q outputs.
All outputs are designed to sink up to 12 mA and
include 25-Ω series resistors to reduce overshoot
and undershoot.
The SN74HSTL162822 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of 14 outputs is controlled with its own
latch-enable (LE) input.
Each of the 14 data (D) inputs is tied to the inputs
of two D-type latches, which provide true data at
the outputs. While LE is low, the outputs (Q) of the
corresponding 14 latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
The SN74HSTL162822 is characterized for
operation from –40°C to 90°C.
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
2Q2
1Q3
GND
2Q3
1Q4
VCC
2Q4
1Q5
GND
2Q5
1Q6
VCC
2Q6
1Q7
GND
2Q7
2Q8
GND
1Q8
2Q9
VCC
1Q9
2Q10
GND
1Q10
2Q11
VCC
1Q11
2Q12
GND
1Q12
2Q13
FUNCTION TABLE
INPUTS
LE
D
OUTPUT
Q
L
H
H
L
L
H
X
L
Q0†
† Output level before the
indicated steady-state input
conditions were established
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
logic diagram (positive logic)
14
1LE
5
D1
1D
3
1Q1
C1
19
1D
2LE
2
2Q1
C1
To 13 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
3.45
V
0.9
V
1.5
V
VCC
VREF
Supply voltage
3.15
Reference voltage
0.68
VI
VIH
Input voltage
High-level input voltage
All pins
VIL
IOH
Low-level input voltage
All pins
High-level output current
VREF–100 mV
–12
IOL
TA
Low-level output current
12
0
Operating free-air temperature
–40
POST OFFICE BOX 655303
0.75
VREF+100 mV
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
2
NOM
• DALLAS, TEXAS 75265
V
90
V
mA
°C
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 3.15 V,
VCC = 3.15 V,
II = –18 mA
IOH = –12 mA
VOL
VCC = 3.15 V,
IOL = 12 mA
VI = 0 or 1.5 V
Control inputs
II
Data inputs
VCC = 3.45 V
Ci
Control inputs
Data inputs
TYP†
UNIT
–1.2
V
V
0.8
V
5
5
µA
90
VCC = 3.45 V,
VCC = 0 or 3.3 V,
VI = 0 or 1.5 V
VI = 0 or 3.3 V
50
VCC = 0 or 3.3 V,
VCC = 0,
VI = 0 or 3.3 V
VO = 0
2
Co
Outputs
† All typical values are at VCC = 3.3 V, TA = 25°C.
MAX
2.2
VI = 0 or 1.5 V
VREF = 0.68 V or 0.9 V
VREF
ICC
MIN
100
2
mA
pF
4
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE low
3
ns
Setup time, D before LE↑
2
ns
th
Hold time, D after LE↑
1
ns
switching characteristics over recommended operating free-air temperature range, VREF = 0.75 V
PARAMETER
tpd
d
FROM
(INPUT)
TO
(OUTPUT)
D
Q
LE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
1.6
5
1.7
5.7
ns
3
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
1.25 V
VREF
LE
From Output
Under Test
0.25 V
CL = 80 pF
(see Note A)
tsu
500 Ω
th
1.25 V
Data Input
VREF
VREF
0.25 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
(see Note B)
1.25 V
VREF
VREF
0.25 V
tPLH
tw
tPHL
1.25 V
Input
VREF
VREF
VOH
Output
1.5 V
0.25 V
VOL
VOLTAGE WAVEFORMS
PULSE DURATION
NOTES: A.
B.
C.
D.
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns.
The outputs are measured one at a time with one transition per measurement.
tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
1.5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74HSTL162822DGGRE4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74HSTL162822DGGRG4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HSTL162822DGGR
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74HSTL162822DGGR TSSOP
DGG
64
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.4
17.3
1.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HSTL162822DGGR
TSSOP
DGG
64
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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