74LVC1G374DCKRG4

SN74LVC1G374 www.ti.com SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 Single D-Type Flip-Flop With 3-State Output Check for Samples: SN74LVC1G374 FEATURES 1 • 2 • • • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Provides Down Translation to VCC Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Live Insertion, Partial-PowerDown Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION This single D-type latch is designed for 1.65-V to 5.5V VCC operation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. 1 6 On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flipflop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) CLK NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. OE GND 2 5 VCC D 3 4 Q CLK 1 6 YEP OR YZP PACKAGE (BOTTOM VIEW) OE GND 2 5 VCC D 3 4 Q D 3 4 Q GND 2 5 VCC CLK 1 6 OE See mechanical drawings for dimensions. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated SN74LVC1G374 SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table INPUTS D OUTPUT Q OE CLK L ↑ L L L ↑ H H L H or L X Q H X X Z Logic Diagram (Positive Logic) OE CLK 6 1 C1 D 3 4 Q D Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V –0.5 VCC + 0.5 (2) (3) UNIT VO Voltage range applied to any output in the high or low state IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) 2 Package thermal impedance (4) DBV package 165 DCK package 259 YEP/YZP package 123 Storage temperature range –65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 SN74LVC1G374 www.ti.com SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 UNIT 1.5 V 0.65 × VCC 1.7 V 2 0.7 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 4.5 V to 5.5 V 0.3 × VCC VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V Low-level output current Δt/Δv Input transition rise or fall rate –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V ± 0.5 V TA mA –24 VCC = 4.5 V IOL V ns/V 5 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 3 SN74LVC1G374 SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 1.2 1.2 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3.8 3.8 UNIT V 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.65 0.55 0.65 ±1 ±2 μA ±5 ±5 μA 0 ±10 ±10 μA 1.65 V to 5.5 V 10 10 μA 3 V to 5.5 V 500 500 μA 3V IOL= 32 mA (1) MAX IOH = –32 mA IOL= 24 mA 4.5 V VI = 5.5 V or GND IOZ VO = 0 to 5.5 V Ioff VI or VO = 5.5 V 0 to 5.5 V VI = 5.5 V or GND, IO = 0 ΔICC VCC – 0.1 1.65 V IOL = 16 mA ICC VCC – 0.1 3V TYP (1) MIN IOH = –8 mA IOH = –24 mA II MAX IOH = –4 mA IOH = –16 mA VOL –40°C to 125°C TYP (1) MIN 1.65 V to 5.5 V IOH = –100 μA VOH –40°C to 85°C VCC One input at VCC – 0.6 V, Other inputs at VCC or GND V Ci VI = VCC or GND 3.3 V 3 3 pF Co VO = VCC or GND 3.3 V 6 6 pF All typical values are at VCC = 3.3 V, TA = 25°C. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 ) SN74LVC1G374 –40°C to 85°C VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN VCC = 3.3 V ± 0.3 V MAX 100 MIN VCC = 5 V ± 0.5 V MAX 125 MIN 150 UNIT MAX fclock Clock frequency tw Pulse duration, CLK high or low 3.3 3 2.8 2.5 175 MHz ns tsu Setup time, data before CLK ↑ 3.5 2.5 2 1.5 ns th Hold time, data after CLK ↑ 3.4 1.6 1.5 1.5 ns Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 ) SN74LVC1G374 –40°C to 125°C VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN MAX MIN 125 VCC = 5 V ± 0.5 V MAX MIN MAX Clock frequency tw Pulse duration, CLK high or low 3.3 3 2.8 2.5 ns tsu Setup time, data before CLK ↑ 3.5 2.5 2 1.5 ns th Hold time, data after CLK ↑ 3.4 1.6 1.5 1.5 ns Submit Documentation Feedback 150 UNIT fclock 4 100 VCC = 3.3 V ± 0.3 V 175 MHz Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 SN74LVC1G374 www.ti.com SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) SN74LVC1G374 –40°C to 85°C FROM INPUT PARAMETER TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax VCC = 2.5 V ± 0.2 V MAX MIN 100 VCC = 3.3 V ± 0.3 V MAX MIN 125 VCC = 5 V ± 0.5 V MAX 150 MIN UNIT MAX 175 MHz tpd CLK Q 2.5 15 2 6 1.4 4 1 3 ns ten OE Q 2.2 12 2 4.8 1.3 3.8 1.1 2.5 ns tdis OE Q 2.2 11 2 4.8 1.6 4.5 1.2 3.1 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC1G374 –40°C to 85°C FROM INPUT PARAMETER TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax VCC = 2.5 V ± 0.2 V MAX MIN 100 VCC = 3.3 V ± 0.3 V MAX MIN 125 VCC = 5 V ± 0.5 V MAX 150 MIN UNIT MAX 175 MHz tpd CLK Q 2.7 18.3 1.8 8.2 1.6 6 1 4 ns ten OE Q 2 13 1.5 6.3 0.9 5 0.7 3.5 ns tdis OE Q 2 14 1.1 5.3 1.4 4.5 0.8 3.1 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC1G374 –40°C to 125°C FROM INPUT PARAMETER TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax VCC = 2.5 V ± 0.2 V MAX MIN 100 VCC = 3.3 V ± 0.3 V MAX MIN 125 VCC = 5 V ± 0.5 V MAX 150 MIN UNIT MAX 175 MHz tpd CLK Q 2.7 18.3 1.8 10.2 1.6 7 1 5 ns ten OE Q 2 14 1.5 8.3 0.9 6.5 0.7 5.5 ns tdis OE Q 2 16 1.1 7.3 1.4 6 0.8 5.1 ns Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 24 24 25 27 8 8 9 11 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 UNIT pF 5 SN74LVC1G374 SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 SN74LVC1G374 www.ti.com SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 7 SN74LVC1G374 SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision B (September 2006) to Revision C Page • Updated document to new TI data sheet format. ................................................................................................................. 1 • Removed Ordering Information table. ................................................................................................................................... 2 • Added ESD warning. ............................................................................................................................................................ 2 • Updated operating temperature range. ................................................................................................................................. 3 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74LVC1G374DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D45 SN74LVC1G374DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (CA45, CA4R) SN74LVC1G374DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (D45, D4J, D4R) SN74LVC1G374YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 D4N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of