74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
•
FEATURES
1
• Member of the Texas Instruments
Widebus+™ Family
• Pinout Optimizes DDR2 DIMM PCB Layout
• 1-to-2 Outputs Support Stacked DDR2 DIMMs
• One Device Per DIMM Required
• Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption
• Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
• Supports SSTL_18 Data Inputs
• Differential Clock (CLK and CLK) Inputs
23
•
•
•
Supports LVCMOS Switching Levels on the
Chip-Select Gate-Enable, Control, and RESET
Inputs
Checks Parity on DIMM-Independent Data
Inputs
Supports industrial temperature range
(-40°C to 85°C)
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low, Except QERR
APPLICATIONS
•
Heavily loaded DDR2 registered DIMM
DESCRIPTION
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM
is required to drive up to 18 stacked SDRAM loads or two devices per DIMM are required to drive up to 36
stacked SDRAM loads.
All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs,
which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error (QERR) output.
The 74SSTUB32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The 74SSTUB32868A accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares
it with the data received on the DIMM-independent D-inputs (D1−D5, D7, D9−D12, D17−D28 when C = 0; or
D1−D12, D17−D20, D22, D24−D28 when C = 1) and indicates whether a parity error has occurred on the
open-drain QERR pin (active low). The convention is even parity; that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,
all DIMM-independent D-inputs must be tied to a known logic state.
The 74SSTUB32868A includes a parity checking function. Parity, which arrives one cycle after the data input to
which it applies, is checked on the PAR_IN input of the device. Two clock cycles after the data are registered,
the corresponding QERR signal is generated.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
-40°C to +85°C
(1)
(2)
TFBGA-ZRH
Tape and Reel
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
74SSTUB32868AZRHR
SB868A
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and
latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error
occurs on the clock cycle before the device enters the low−power mode (LPM) and the QERR output is driven
low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity
check computation.
The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration
(when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low
or high level to configure the register in the desired mode.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers.
However, when coming out of reset, the register becomes active quickly, relative to the time to enable the
differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the
low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32868A
must ensure that the outputs remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C
inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1)
and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs
are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs function normally. Also, if both DCS0 and DCS1
inputs are high, the device will gate the QERR output from changing states. If either DCS0 or DCS1 is low, the
QERR output functions normally. The RESET input has priority over the DCS0 and DCS1 control and when
driven low forces the Qn outputs low, and the QERR output high. If the chip-select control functionality is not
desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0
and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and
DCS1 only, then the CSGEN input should be pulled up to VCC through a pullup resistor.
The two VREF pins (A5 and AB5) are connected together internally by approximately 150 Ω. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range
VI
Input voltage range (see notes
(2)
and
(2)
(3)
and
)
(3)
)
VALUE
UNIT
–0.5 to 2.5
V
–0.5 to VCC + 0.5
V
VO
Output voltage range (see notes
–0.5 to VCC + 0.5
V
IIK
Input clamp current (VI < 0, VI > VCC)
±50
mA
IOK
Output clamp current (VI < 0, VO > VCC)
±50
mA
IO
Continuous output current (VO = 0 to VCC)
±50
mA
ICC
Continuous current through each VCC or GND
±100
mA
RθJA
Thermal resistance, junction−to−ambient (see note
RθJC
Thermal resistance, junction−to−case (see note
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(4)
)
(4)
)
No airflow
46.8
Airflow 200 ft/min
42.9
No airflow
17.9
k/W
–65 to +150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 2.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
1.9
V
0.49 x VCC
0.5 x VCC
0.51 x VCC
V
VREF - 40 mV
VREF
VREF + 40 mV
V
VCC
V
SUPPLY VOLTAGES, CURRENTS AND TEMPERATURE RANGE
VCC
Supply voltage
VREF
Reference voltage
VTT
Termination voltage
VI
Input voltage
VIH
AC high-level input voltage
Data inputs, DCSn, PAR_IN
VIL
AC low-level input voltage
Data inputs, DCSn, PAR_IN
VIH
DC high-level input voltage
Data inputs, DCSn, PAR_IN
VIL
DC low-level input voltage
Data inputs, DCSn, PAR_IN
VIH
High-level input voltage
RESET, CSGEN, C
VIL
Low-level input voltage
RESET, CSGEN, C
VICR
Common-mode input voltage
range
CLK, CLK
0.675
VI(PP)
Peak-to-peak input voltage
CLK, CLK
0.6
IOH
High-level output current
Q outputs
-12
IOL
Low-level output current
Q outputs
12
TA
Operating free-air temperature
(1)
1.7
0
VREF + 250 mV
V
VREF - 250 mV
VREF + 125 mV
V
VREF - 125 mV
0.65 × VCC
QERR output
V
V
0.35 × VCC
V
1.125
V
V
30
-40
V
85
mA
mA
°C
The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. See the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004 (available for download at www.ti.com.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
3
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
Q outputs
Q outputs
VOL
QERR
PAR_IN
II
IOZ
ICC
TEST CONDITION
VCC
IOH = –100 µA
MIN
1.7 V to 1.9 V
IOH = –8 mA
1.7 V
IOL = 100 µA
ICC(DLP)
CI
(1)
(2)
(3)
4
MAX
VCC – 0.2
1.7 V to 1.9 V
0.2
IOL = 8 mA
1.7 V
0.5
IOL = 25 mA
1.7 V
0.5
VI = GND
1.9 V
–5
VI = VCC
25
All other inputs (2)
VI = VCC or GND
±5
QERR outputs
VO = VCC or GND
Static standby (3)
RESET = GND
Static operating
RESET = VCC, VI = VIH(AC) or
VIL(AC)
1.9 V
IO = 0
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
Dynamic operating −
50% duty cycle, One data input
per each data input
switching at one half clock
frequency, 50% duty cycle
Chip-select-enabled
low-power active
mode − clock only
RESET = VCC, VI = VIH(AC) or
VIL(AC),CLK and CLK switching
50% duty cycle
Chip-select-enabled
low-power active
mode
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
50% duty cycle, One data input
switching at one half clock
frequency, 50% duty cycle
Data inputs, DCSn,
PAR_IN, CSGEN
VI = VREF ±250 mV
CLK, CLK
VICR = 0.9 V, VI(PP) = 600 mV
RESET
VI = VCC or GND
IO = 0
IO = 0
1.9 V
µA
±10
µA
µA
80
mA
64
µA/MHz
37
µA/clock
MHz/
D inputs
68
µA/MHz
2.7
µA/clock
MHz/
D inputs
1.8 V
2
V
200 (3)
1.8 V
1.8 V
UNIT
V
1.2
RESET = VCC, VI = VIH(AC) or
Dynamic operating −
VIL(AC),CLK and CLK switching
clock only
50% duty cycle
ICC(D)
TYP (1)
2.5
2
3
3
pF
4
All typical values are at VCC = 1.8 V, TA = +25°C.
Each VREF pin (A5 or AB5) should be tested independently, with the other (untested) pin open.
The maximum static standby current ICC is 100µA if the device is exposed to commercial temperature range (0°C to 70°C) only. For
industrial temperature range (-40°C to 85°C) static ICC is 200µA.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
PACKAGE
(TOP VIEW)
1
2
3
4
5
6
Terminal Assignment for Register-A (C = 0)
7
8
A
A
3
4
5
6
7
8
D1
C
GND
VREF
GND
Q1A
Q1B
VCC
VCC
VCC
Q2A
Q2B
1
2
D2
B
D4
D3
VCC
C
D6
(DCKE1)
D5
GND
GND
GND
GND
Q3A
Q3B
D
D8
(DCKE0)
D7
VCC
VCC
VCC
VCC
Q4A
Q4B
E
D9
Q6A
(QCKE1A)
GND
GND
GND
GND
Q5A
Q5B
F
D10
Q8A
(QCKE0A)
VCC
VCC
VCC
VCC
Q7A
Q6B
(QCKE1B)
J
G
D11
Q10A
GND
GND
GND
GND
Q9A
Q7B
K
H
D12
Q12A
VCC
VCC
VCC
VCC
Q11A
Q8B
(QCKE0B)
J
D13
(DCS1)
Q13A
(QCS1A)
GND
GND
GND
GND
Q10B
Q9B
K
D14
(DCS0)
Q14A
(QCS0A)
VCC
VCC
VCC
VCC
Q12B
Q11B
L
CLK
CSGEN
PAR_IN
GND
GND
GND
Q14B
(QCS0B)
Q13B
(QCS1B)
M
CLK
RESET
QERR
VCC
VCC
VCC
N
D15
(DODT0)
Q15A
(QODT0A)
GND
GND
GND
GND
Q17B
Q18B
P
D16
(DODT1)
Q16A
(QODT1A)
VCC
VCC
VCC
VCC
Q19B
Q20B
AA
R
D17
Q17A
GND
GND
GND
GND
Q18A
Q21B
AB
T
D18
Q19A
VCC
VCC
VCC
VCC
Q20A
Q22B
U
D19
Q21A
GND
GND
GND
GND
Q22A
Q23B
V
D20
Q23A
VCC
VCC
VCC
VCC
Q24A
Q24B
B
C
D
E
F
G
H
L
M
N
P
R
T
U
V
W
Y
Q16B
Q15B
(QODT0B) (QODT1B)
W
D21
D22
GND
GND
GND
GND
Q25A
Q25B
Y
D23
D24
VCC
VCC
VCC
VCC
Q26A
Q26B
AA
D25
D26
GND
GND
GND
GND
Q27A
Q27B
AB
D27
D28
NC
VCC
VREF
VCC
Q28A
Q28B
A.
Each pin name in parentheses indicates the DDR2 DIMM signal name.
B.
NC - No internal connection.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
5
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
Logic Diagram for Register-A Configuration (Positive Logic); C = 0
RESET
CLK
CLK
VREF
DCKE0,
DCKE1
M2
L1
M1
A5, AB5
D1, C1
2
2
F2, E2
D
CLK
Q
2
2
H8, F8
R
2
DODT0,
DODT1
N1, P1
2
2
N2, P2
D
CLK
Q
2
2
R
M7, M8
2
DCS0
K1
K2
D
CLK
DCS1
QCKE0B,
QCKE1B
QODT0A,
QODT1A
QODT0B,
QODT1B
QCS0A
Q
R
CSGEN
QCKE0A,
QCKE1A
L7
QCS0B
L2
J1
J2
D
CLK
QCS1A
Q
R
L8
QCS1B
One of 22 Channels
D1
A2
D
A7
CE
CLK
Q
A8
R
Q1A
Q1B
To 21 Other Channels
(D2−D5, D7, D9−D12, D17−D28)
6
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
Parity Logic Diagram for Register-A Configuration (Positive Logic); C = 0
RESET
M2
L1
CLK
M1
CLK
D1−D5,
D7,
D9−D12,
22
D17−D28
A5, AB5
VREF
D1−D5, D7,
D9−D12,
D17−D28
22
D1−D5, D7,
D9−D12,
D17−D28
D
CLK
R
Q
22
D1−D5, D7,
D9−D12,
D17−D28
CLK
R
CE
Q
Parity Generator
and
Error Check
M3
K1
K2
D
CLK
DCS1
QERR
QCS0A
Q
R
CSGEN
Q1B−Q5B,
Q7B,
Q9B−Q12B,
Q17B−Q28B
L3
D
DCS0
22
CE
22
PAR_IN
22
Q1A−Q5A,
Q7A,
Q9A−Q12A,
Q17A−Q28A
L7
QCS0B
L2
J1
J2
D
CLK
R
QCS1A
Q
L8
QCS1B
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
7
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
PACKAGE
(TOP VIEW)
1
2
3
4
5
6
Terminal Assignment for Register-B (C = 1)
7
8
A
A
1
2
3
4
5
6
7
D2
D1
C
GND
VREF
GND
Q1A
Q1B
VCC
VCC
VCC
Q2A
Q2B
B
D4
D3
VCC
C
C
D6
D5
GND
GND
GND
GND
Q3A
Q3B
D
D
D8
D7
VCC
VCC
VCC
VCC
Q4A
Q4B
E
E
D9
Q6A
GND
GND
GND
GND
Q5A
Q5B
VCC
VCC
VCC
Q7A
Q6B
B
F
F
D10
Q8A
VCC
G
G
D11
Q10A
GND
GND
GND
GND
Q9A
Q7B
H
D12
Q12A
VCC
VCC
VCC
VCC
Q11A
Q8B
J
D13
(DODT1)
Q13A
(DODT1A)
GND
GND
GND
GND
Q10B
Q9B
K
D14
Q14A
(DODT0) (QODT0A)
VCC
VCC
VCC
VCC
Q12B
Q11B
H
J
K
L
M
N
R
T
CLK
CSGEN
PAR_IN
GND
GND
GND
M
CLK
RESET
QERR
VCC
VCC
VCC
Q15B
(QCS0B)
Q16B
(QCS1B)
N
D15
(DCS0)
Q15A
(QCS0A)
GND
GND
GND
GND
Q17B
Q18B
P
D16
(DCS1)
Q16A
(QCS1A)
VCC
VCC
VCC
VCC
Q19B
Q20B
R
D17
Q17A
GND
GND
GND
GND
Q18A
Q21B
(QCKE0B)
T
D18
Q19A
VCC
VCC
VCC
VCC
Q20A
Q22B
U
D19
Q21A
(QCKE0A)
GND
GND
GND
GND
Q22A
Q23B
(QCKE1B)
V
D20
Q23A
(QCKE1A)
VCC
VCC
VCC
VCC
Q24A
Q24B
W
D21
(DCKE0)
D22
GND
GND
GND
GND
Q25A
Q25B
Y
D23
(DCKE1)
D24
VCC
VCC
VCC
VCC
Q26A
Q26B
D25
D26
GND
GND
GND
GND
Q27A
Q27B
NC
VCC
VREF
VCC
Q28A
Q28B
U
V
Q13B
Q14B
(QODT0B) (QODT1B)
L
P
W
Y
AA
AB
AA
AB
8
8
D27
D28
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
Logic Diagram for Register-B Configuration (Positive Logic); C = 1
RESET
CLK
CLK
VREF
DCKE0,
DCKE1
M2
L1
M1
A5, AB5
W1, Y1
2
2
U2, V2
D
CLK
Q
2
2
R8, U8
R
2
DODT0,
DODT1
K1, J1
2
2
K2, J2
D
CLK
Q
2
2
R
L7, L8
2
DCS0
N1
N2
D
CLK
DCS1
QCKE0B,
QCKE1B
QODT0A,
QODT1A
QODT0B,
QODT1B
QCS0A
Q
R
CSGEN
QCKE0A,
QCKE1A
M7
QCS0B
L2
P1
P2
D
CLK
QCS1A
Q
R
M8
QCS1B
One of 22 Channels
D1
A2
D
A7
CE
CLK
A8
R
Q1A
Q
Q1B
To 21 Other Channels
(D2−D12, D17−D20, D22, D24−D28)
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
9
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
Parity Logic Diagram for Register-B Configuration (Positive Logic); C = 1
RESET
M2
L1
CLK
M1
CLK
D1−D12,
D17−D20,
D22,
22
D24−D28
A5, AB5
VREF
D1−D12,
D17−D20, D22,
D24−D28
22
D1−D12,
D17−D20, D22,
D24−D28
D
CLK Q
R
22
D1−D12,
D17−D20, D22,
D24−D28
Q1B−Q12B,
Q17B−Q20B,
Q22B,
Q24B−Q28B
L3
D
CLK Q
R
DCS0
22
CE
22
PAR_IN
22
Q1A−Q12A,
Q17A−Q20A,
Q22A,
Q24A−Q28A
CE
Parity Generator
and
Error Check
M3
N1
N2
D
QERR
QCS0A
CLK Q
R
CSGEN
DCS1
M7
QCS0B
L2
P1
P2
D
QCS1A
CLK Q
R
10
Submit Documentation Feedback
M8
QCS1B
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
Timing Diagram for 74SSTUB32868A During Start-Up (RESET Switches From L to H)
RESET
CSGEN
DCS0
DCS1
n
n+1
n+2
n+3
n+4
CLK
CLK
tact
tsu
th
Dn, DODTn,
DCKEn
(see Note A)
tpdm, tpdmss
CLK to Q
Qn, QODTn,
QCKEn
tsu
th
PAR_IN
(see Note A)
tPHL
CLK to QERR
QERR
(see Note B)
tPHL, tPLH
CLK to QERR
Data to QERR Latency
H, L, or X
H or L
A.
After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum
time of tact max, to avoid a false error.
B.
If the data is clocked in on the n-clock pulse, the QERR output signal is generated on the n + 2 clock pulse, and it is
valid on the n + 3 clock pulse.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
11
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
Timing Diagram for 74SSTUB32868A During Normal Operation (RESET = H)
RESET
CSGEN
DCS0
DCS1
n
n+1
n+2
n+3
n+4
CLK
CLK
tsu
th
Dn, DODTn,
DCKEn
tpdm’ tpdmss
CLK to Q
Qn, QODTn,
QCKEn
tsu
th
PAR_IN
tPHL’ tPLH
CLK to QERR
QERR
(see Note A)
Data to QERR Latency
Unknown input
event
A.
12
Output signal is dependent on
the prior unknown input event
H or L
If the data is clocked in on the n-clock pulse, the QERR output signal is generated on the n + 2 clock pulse, and it is
valid on the n + 3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a
minimum of two clock cycles or until RESET is driven low.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
Timing Diagram for 74SSTUB32868A During Shut-Down (RESET Switches From H to L)
RESET
tinact
CSGEN
(see Note A)
DCS0
(see Note A)
DCS1
(see Note A)
CLK
(see Note A)
CLK
(see Note A)
Dn, DODTn,
DCKEn
(see Note A)
tRPHL
RESET to Q
Qn, QODTn,
QCKEn
PAR_IN
(see Note A)
QERR
tRPHL
RESET to QERR
H, L, or X
A.
H or L
After RESET is switched from high to low, all data and clock input signals must be held at logic levels (not floating) for
a minimum time of tinact max, to avoid a false error.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
13
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
TERMINAL FUNCTIONS
TERMINAL NAME
ELECTRICAL
CHARACTERISTICS
DESCRIPTION
GND
Ground
Ground input
VCC
Power supply voltage
1.8 V nominal
VREF
Input reference voltage
0.9 V nominal
CLK
Positive master clock input
Differential input
CLK
Negative master clock input
Differential input
C
Configuration control input - Register A or Register B
LVCMOS input
RESET
Asynchronous reset input − resets registers and disables VREF, data and clock
differential-input receivers. When RESET is low, all the Q outputs are forced low and
the QERR output is forced high.
LVCMOS input
CSGEN
Chip select gate enable. When high, D1−D28 (1) inputs are latched only when at least
one chip select input is low during the rising edge of the clock. When low, the
D1−D28 (1) inputs are latched and redriven on every rising edge of the clock.
LVCMOS input
D1-D28
Data input. Data are clocked in on the crossing of the rising edge of CLK and the
falling edge of CLK
SSTL_18 input
DCS0, DCS1
Chip select inputs. These pins initiate DRAM address/command decodes, and as such
at least one will be low when a valid address/command is present. The Register can
be programmed to redrive all D inputs (CSGEN high) only when at least one chip
select input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1−D28 (2) inputs will
be disabled.
SSTL_18 input
DODT0, DODT1
The outputs of this register bit will not be suspended by the DCS0 and DCS1 control.
SSTL_18 input
DCKE0, DEKE1
The outputs of this register bit will not be suspended by the DCS0 and DCS1 control.
SSTL_18 input
PAR_IN
Parity input. The parity input arrives one clock cycle after the corresponding data
input. Pulldown resistor of typical 150kΩ to GND.
SSTL_18 input with
pulldown
Q1-Q28 (3)
Data outputs that are suspended by the DCS0 and DCS1 control.
1.8 V CMOS output
QCS0, QCS1
Data output that will not be suspended by the DCS0 and DCS1 control.
1.8 V CMOS output
QODT0, QODT1
Data output that will not be suspended by the DCS0 and DCS1 control.
1.8 V CMOS output
QCKE0, QEKE1
Data output that will not be suspended by the DCS0 and DCS1 control.
1.8 V CMOS output
QERR
Output error bit. This bit is generated two clock cycles after the corresponding data is
registered.
NC
No internal connection
(1)
(2)
(3)
14
Open-drain output
Data inputs = D1−D5, D7, D9−D12, D17−D28 when C = 0.
Data inputs = D1−D12, D17−D20, D22, D24−D28 when C = 1.
Data inputs = D1−D5, D7, D9−D12, D17−D28 when C = 0.
Data inputs = D1−D12, D17−D20, D22, D24−D28 when C = 1.
Data outputs = Q1−Q5, Q7, Q9−Q12, Q17−Q28 when C = 0.
Data outputs = Q1−Q12, Q17−Q20, Q22, Q24−Q28 when C = 1.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
FUNCTION TABLE
INPUTS
OUTPUTS
RESET
DCS0
DCS1
CSGEN
CLK
CLK
dn,
DODTn,
DCKEn
Qn
QCS0
QCS1
QODT,
QCKE
H
L
L
X
↑
↓
L
L
L
L
L
H
L
L
X
↑
↓
H
H
L
L
H
H
L
L
X
L or H
L or H
X
Q0
Q0
Q0
Q0
H
L
H
X
↑
↓
L
L
L
H
L
H
L
H
X
↑
↓
H
H
L
H
H
H
L
H
X
L or H
L or H
X
Q0
Q0
Q0
Q0
H
H
L
X
↑
↓
L
L
H
L
L
H
H
L
X
↑
↓
H
H
H
L
H
H
H
L
X
L or H
L or H
X
Q0
Q0
Q0
Q0
H
H
H
L
↑
↓
L
L
H
H
L
H
H
H
L
↑
↓
H
H
H
H
H
H
H
H
L
L or H
L or H
X
Q0
Q0
Q0
Q0
H
H
H
H
↑
↓
L
Q0
H
H
L
H
H
H
H
↑
↓
H
Q0
H
H
H
H
H
H
H
L or H
L or H
X
Q0
Q0
Q0
Q0
L
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
L
L
L
L
L
PARITY AND STANDBY FUNCTION
INPUTS
(1)
(2)
(3)
OUTPUTS
RESET
CLK
CLK
DCS0
DCS1
Σ OF INPUTS = H
D1 - D22
H
↑
↓
L
X
Even
H
↑
L
X
H
↑
↓
L
X
H
↑
↓
L
X
H
↑
↓
X
L
H
↑
↓
X
L
H
↑
↓
X
L
H
↑
↓
X
L
H
↑
↓
H
PAR_IN
(1)
QERR
L
H
Odd
L
L
Even
H
L
Odd
H
H
Even
L
H
Odd
L
L
Even
H
L
Odd
H
H
H
X
X
QERR 0
(2)
(3)
H
L or H
L or H
X
X
X
X
QERR 0
L
X or floating
X or floating
X or floating
X or floating
X
X or floating
H
PAR_IN arrives one clock cycle after the data to which it applies.
This transition assumes that QERR is high at the crossing of CLK going high and CLK going low. If QERR goes low, it stays latched low
for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive errors occur, the QERR output is driven low
and latched low for a clock duration equal to the parity error duration or until RESET is driven low. For QERR computation, CSGEN is a
do not care.
If DCS0, DCS1 and CSGEN are driven high, the device is placed in a low−power mode (LPM). If a parity error occurs on the clock cycle
before the device enters the LPM and the QERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or
until RESET is driven low.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
15
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
TIMING REQUIREMENTS
(1)
Over recommended ranges of supply voltage, load, and operating free-air temperature (see Figure 1 and Note
)
VCC = 1.8 V ±0.1 V
MIN
f(clock)
Clock frequency
tw
Pulse duration, CLK, CLK high or low
tact
Differential inputs active time (see Note
tinact
Differential inputs inactive time (see Note
tsu
Setup time
th
(1)
(2)
(3)
Hold time
MAX
UNIT
410
MHz
1
ns
(2)
)
(3)
)
DCSn before CLK↑, CLK↓, CSGEN high
600
DCSn before CLK↑, CLK↓, CSGEN low
500
DODTn, DCKEn, and Data before CLK↑, CLK↓
500
PAR_IN before CLK↑, CLK↓
500
DCSn, DODTn, DCKEn, and Data after CLK↑, CLK↓
400
PAR_IN after CLK↑, CLK↓
400
10
ns
15
ns
ps
ps
All inputs slew rate is 1 V/ns ±20%
VREF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low.
SWITCHING CHARACTERISTICS
Over recommended ranges of supply voltage, load, and operating free-air temperature (unless otherwise noted)
VCC = 1.8 V ±0.1 V
PARAMETER
FROM (INPUT)
TO (OUTPUT)
fmax (see Figure 2)
tpdm
(1)
MIN
MAX
410
(production test, see Figure 1)
CLK and CLK
tPLH (see Figure 4)
Q
CLK and CLK
tPHL (see Figure 4)
QERR
UNIT
MHz
0.5
1.0
ns
1.2
3
ns
1
2.4
tRPHL (2) (see Figure 2)
RESET
Q
3
ns
tRPLH (see Figure 4)
RESET
QERR
3
ns
(1)
(2)
The typical difference between min and max does not exceed 400 ps.
Includes 350-ps test-load transmission line delay.
OUTPUT SLEW RATES
over operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V ±0.1 V
(1)
16
PARAMETER
FROM
TO (OUTPUT)
MIN
MAX
UNIT
dV/dt_r
20%
80%
1
5
V/ns
1
5
V/ns
1
V/ns
dV/dt_f
80%
20%
dV/dt_Δ (1)
20% to 80%
20% to 80%
The difference between dV/dr_r (rising edge rate) and dV/dt_f (falling edge).
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
PARAMETER MEASUREMENT INFORMATION
VCC/2
ZO = 50 W
Test
Point
DUT
Clock Inputs
RL = 50 W
Test
Point
CLK
Out
ZO = 50 W
CLK
ZO = 50 W
Test
Point
LOAD CIRCUIT
VI(PP)
Timing
V /2
Inputs CC
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Figure 1. Output Load Circuit for Production Test
Table 1. Propagation Delay (Design Goal as per JEDEC Specification)
VCC = 1.8 V ±0.1 V
PARAMETER
FROM (INPUT)
TO (OUTPUT)
MIN
MAX
tpdm (1)
CLK and CLK
Q
1.1
1.5
ns
CLK and CLK
Q
1.6
ns
tpdmss
(1)
(1)
UNIT
Includes 350-ps test-load transmission line delay.
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
17
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
VCC
ZO = 50 W,
tD = 350 ps
Test
Point
DUT
RL = 1 kW
CLK
Clock Inputs
CL = 30 pF
(see Note A)
ZO = 50 W,
tD = 350 ps
CLK
ZO = 50 W,
tD = 350 ps
Output
Test Point
Out
RL = 100 W
Test
Point
RL = 1 kW
LOAD CIRCUIT
tw
VIH
VREF
Input
LVCMOS
RESET
Input
VCC/2
VCC
VCC/2
VIL
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tinact
VREF
VI(PP)
tact
ICC
(see Note B)
90%
10%
ICC (operating)
Timing
Inputs
ICC (standby)
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
tPHL
VOH
VCC/2
VOL
VCC/2
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VIH
LVCMOS
RESET
Input
VICR
tsu
VICR
tPLH
VI(PP)
Timing
Inputs
VICR
VCC/2
VIL
tPHL
th
VOH
VIH
Input
VREF
VCC/2
Output
VREF
VOL
VIL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
A.
CL includes probe and jig capacitance.
B.
ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew
rate = 1 V/ns ±20% (unless otherwise noted).
D.
The outputs are measured one at a time with one transition per measurement.
E.
VREF = VCC/2
F.
VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G.
VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H.
VI(PP) = 600 mV.
I.
tPLH and tPHL are the same as tpd.
Figure 2. Data Output Load Circuit and Voltage Waveforms
18
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C – JULY 2007 – REVISED MARCH 2009
VCC
DUT
RL = 50 W
VOH
Output
Test Point
Out
80%
CL = 10 pF
(see Note A)
20%
VOL
dV_f
dt_f
LOAD CIRCUIT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
dt_r
dV_r
Test Point
Out
80%
CL = 10 pF
(see Note A)
RL = 50 W
20%
Output
LOAD CIRCUIT
LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOH
VOL
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
A.
CL includes probe and jig capacitance.
B.
All
input
pulses
are
supplied
by
generators
having
the
PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
following
characteristics:
Figure 3. Data Output Slew-Rate Measurement Information
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
19
74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
VCC
DUT
VI(PP)
Timing
Inputs
RL= 1 kW
VICR
tPHL
Test Point
Out
VICR
Output
Waveform 1
CL = 10 pF
(see Note A)
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(HIGH-TO-LOW)
LOAD CIRCUIT
VI(PP)
LVCMOS
RESET
Input
VCC
VCC/2
0V
Timing
Inputs
tPLH
Output
Waveform 2
0V
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(LOW-TO-HIGH)
VICR
tPHL
VOH
0.15 V
VICR
VOH
Output
Waveform 2
0.15 V
0V
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(LOW-TO-HIGH)
A.
CL includes probe and jig capacitance.
B.
All
input
pulses
are
supplied
by
generators
having
the
PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
C.
tPLH and tPHL are the same as tpd.
following
characteristics:
Figure 4. Error Output Load Circuit and Voltage Waveforms
20
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): 74SSTUB32868A
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
74SSTUB32868AZRHR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
NFBGA
ZRH
176
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
SB868A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74SSTUB32868AZRHR
Package Package Pins
Type Drawing
NFBGA
ZRH
176
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
6.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.3
1.65
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74SSTUB32868AZRHR
NFBGA
ZRH
176
1000
336.6
336.6
31.8
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
