ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter
Check for Samples: ADC08DL500
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
1
2
Single +1.9V ±0.1V Operation
Duty Cycle Corrected Sample Clock
Satellite Modems
Digital Oscilloscopes
Direct RF Down Conversion
Communications Systems
Test Instrumentation
DESCRIPTION
The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500
digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in
demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing
codes over the full operating temperature range. The unique folding and interpolating architecture, the fully
differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration
schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective
Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 10−18 Code
Error Rate (C.E.R.)
The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead
LQFP and operates over the modified Industrial (-40°C ≤ TA ≤ +70°C) temperature range.
Table 1. Key Specifications
VALUE
Resolution
Max Conversion Rate
Code Error Rate
ENOB @ 125 MHz Input
DNL
Power Consumption
UNIT
8
Bits
500
MSPS
10−18
(typ)
7.2
Bits (typ)
±0.15
LSB (typ)
Operating in 1:2 Demux Output
1.25
W (typ)
Power Down Mode
3.3
mW (typ)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Block Diagram
VINI+
+
VINI-
-
S/H
8-BIT
8
ADC1
Selectable
DEMUX
DI
LATCH
DId
VINQ+
+
VINQ-
-
Data Bus Output
16 LVDS Pairs
S/H
8-BIT
ADC2
8
DQ
Selectable
DEMUX
DQd
VREF
VBG
CLK+
2
Output
Clock
Generator
CLK/2
CLKDEMUX
Control
Inputs
Serial
Interface
2
Data Bus Output
16 LVDS Pairs
LATCH
Control
Logic
DCLK+
DCLK-
OR/DCLK2
CalRun
3
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
NC
NC
VA
CalDly/SCS
CalRun
DId0+
DId0DId1+
DId1VDR
DNC
DR GND
DId2+
DId2DId3+
DId3DId4+
DId4DId5+
DId5VDR
DNC
DR GND
DId6+
DId6DId7+
DId7DI0+
DI0DI1+
DI1VDR
DNC
DR GND
NC
NC
Pin Configuration
NC
GND
GND
VA
OutV/SCLK
OutEdge/DDR/SDATA
VA
GND
VCMO
VA
GND
VINIVINI+
GND
VA
FSR/ALT_ECE/DCLK_RSTDCLK_RST/DCLK_RST+
VA
VA
CLK+
CLKVA
GND
VINQ+
VINQGND
VA
PD
GND
VA
PDQ
CAL
VBG
REXT
ADC08DL500
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC
DR GND
DI2+
DI2DI3+
DI3DI4+
DI4DI5+
DI5VDR
DR GND
DI6+
DI6DI7+
DI7DCLK+
DCLKOR-/DCLK2OR+/DCLK2+
DQ7DQ7+
DQ6DQ6+
DR GND
VDR
DQ5DQ5+
DQ4DQ4+
DQ3DQ3+
DQ2DQ2+
DR GND
NC
ECE
DR GND
DQd2+
DQd2DQd3+
DQd3DQd4+
DQd4DQd5+
DQd5VDR
DRST_SEL
DR GND
DQd6+
DQd6DQd7+
DQd7DQ0+
DQ0DQ1+
DQ1VDR
NC
DR GND
NC
NC
NC
NC
VA
Tdiode_p
Tdiode_n
DQd0+
DQd0DQd1+
DQd1VDR
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
VA
5
OutV / SCLK
50k
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. When the extended control
mode is enabled, this pin functions as the SCLK input which
clocks in the serial data. OutV functionality: (1)
A logic high on the PDQ pin puts only the "Q" ADC into the
Power Down mode. PDQ functionality: (1)
31
PDQ
GND
(1)
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
3
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
VA
50k
200k
50k
DDR
8 pF
GND
SDATA
VA
OutEdge / DDR /
SDATA
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. When this pin is floating or connected
to 1/2 the supply voltage, DDR clocking is enabled. When the
extended control mode is enabled, this pin functions as the
SDATA input. OutEdge functionality: (2)
17
DCLK_RST /
DCLK_RST+
DCLK Reset. When single-ended DCLK_RST is selected by
floating or setting pin 58 logic high, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. When differential DCLK_RST is selected
by setting pin 58 logic low, this pin receives the positive
polarity of a differential pulse signal used to reset and
synchronize the DCLK outputs of multiple converters.
DCLK_RST, DCLK_RST+ functionality: (3)
28
PD
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode. PD functionality: (3)
32
CAL
6
VA
GND
VA
16
50k
FSR/ALT_ECE/DC
LK_RST-
50k
GND
(2)
(3)
4
200k
8 pF
Calibration Cycle Initiate. A minimum tCAL_L input clock cycles
logic low followed by a minimum of tCAL_H input clock cycles
high on this pin initiates the calibration sequence.
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has three functions. It can
conditionally control the ADC full-scale voltage, enable the
extended control mode, or become the negative polarity
signal of a differential pair in differential DCLK_RST mode. If
pin 58 and pin 47 are floating or at logic high, this pin can be
used to set the full-scale-range or can be used as an
alternate extended control enable pin . When used as the
FSR pin, a logic low on this pin sets the full-scale differential
input range to a reduced VIN input level. A logic high on this
pin sets the full-scale differential input range to a higher VIN
input level. To enable the extended control mode, whereby
the serial interface and control registers are employed, allow
this pin to float or connect it to a voltage equal to VA/2. Note
that pin 47 overrides the extended control enable of this pin.
When pin 58 is held at logic low, this pin acts as the
DCLK_RST- pin. When in differential DCLK_RST mode, there
is no pin-controlled FSR and the full-scale-range is defaulted
to the higher VIN input level. FSR, ALT_ECE, DCLK_RSTfunctionality: (3)
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
VA
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 16, and a logic high on pin 47, this pin
functions as Calibration Delay and sets the number of input
clock cycles after power up before calibration begins With pin
16 floating, and a logic low on pin 47, this pin acts as the
enable pin for the serial interface input and the CalDly value
becomes "0" (short delay with no provision for a long powerup calibration delay). CalDly functionality: (3)
50k
141
CalDly / SCS
50k
GND
VA
20
21
CLK+
CLK−
50k
AGND
100
VA
VBIAS
50k
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+.
AGND
VINI+
VINI−
VA
50k
13
12
24
25
AGND
VCMO
150
VINQ+
VINQ−
Control from VCMO
VA
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
16 in normal mode and the Input Full-Scale Voltage Adjust
register in the extended control mode. Refer to the VIN
specification in the Converter Electrical Characteristics for the
full-scale input range in the normal mode.
50k
AGND
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
5
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
VA
VCMO
200k
Enable AC
Coupling
8 pF
GND
9
VCMO
33
VBG
140
CalRun
Common Mode Voltage. This pin is the common mode output
in d.c. coupling mode and also serves as the a.c. coupling
mode select pin. When d.c. coupling is used, the voltage
output at this pin is required to be the common mode input
voltage at VIN+ and VIN− when d.c. coupling is used. This pin
should be grounded when a.c. coupling is used at the analog
inputs. This pin is capable of sourcing or sinking 100 μA.
Bandgap output voltage capable of 100 μA source/sink and
can drive a load up to 80 pF. VBG functionality: (4)
VA
Calibration Running indication. This pin is at a logic high
when calibration is running. CalRun functionality: (4)
GND
VA
34
V
REXT
External bias resistor connection. Nominal value is 4.7 kΩ
(±0.1%) to ground.
GND
Tdiode_P
40
41
(4)
(5)
6
Tdiode_P
Tdiode_N
Tdiode_N
Temperature Diode Positive (Anode) and Negative (Cathode).
These pins may be used for die temperature measurements,
however no specified accuracy is implied or guaranteed.
Noise coupling from adjacent output data signals has been
shown to affect temperature measurements using this
feature. Tdiode_P, Tdiode_N functionality: (5)
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Pin Functions
Pin No.
Symbol
Equivalent Circuit
VA
47
ECE
GND
VA
58
FS (PIN 14)
10k
DRST_SEL
10k
GND
Description
Extended Control Enable. This pin always enables and
disables Extended Control Enable. When this pin is set logic
high, the extended control mode is inactive and all control of
the device must be through control pins only . When it is set
logic low, the extended control mode is active. This pin
overrides the Extended Control Enable signal set using pin
16.
DCLK_RST select. This pin selects whether the DCLK is
reset using a single-ended or differential signal. When this pin
is floating or logic high, the DCLK_RST operation is singleended and pin 16 functions as FSR/ALT_ECE. When this pin
is logic low, the DCLK_RST operation becomes differential
with functionality on pin 17 (DCLK_RST+) and pin 16
(DCLK_RST-). When in differential DCLK_RST mode, there
is no pin-controlled FSR and the full-scale-range is defaulted
to the higher VIN input level. When pin 47 is set logic low, the
extended control mode is active and the Full-Scale Voltage
Adjust registers can be programmed. DRST_SEL
functionality: (5)
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
7
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Pin Functions
Pin No.
Symbol
93 / 88
94 / 87
95 / 86
96 / 85
99 / 82
100 / 81
101 / 80
102 / 79
103 / 78
104 / 77
105 / 76
106 / 75
114 / 67
115 / 66
116 / 65
117 / 64
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
118 / 63
119 / 62
120 / 61
121 / 60
125 / 56
126 / 55
127 / 54
128 / 53
129 / 52
130 / 51
131 / 50
132 / 49
136 / 45
137 / 44
138 / 43
139 / 42
DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
89
90
OR+/DCLK2+
OR-/DCLK2-
Equivalent Circuit
Description
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100 Ω
differential resistor.
VDR
-
+
+
-
DR GND
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should be terminated with a 100 Ω
differential resistor when enabled. In non-demultiplexed
mode, these outputs are disabled and are high impedance
when enabled. When disabled, these outputs must be left
floating.
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range ±VIN/2 as programmed by the FSR pin in non-extended
control mode or the Input Full-Scale Voltage Adjust register
setting in the extended control mode). DCLK2 is the exact
mirror of DCLK and should output the same signal at the
same rate. DCLK2+/- functionality: (6)
Data Clock. Differential Clock outputs used to latch the output
data. Delayed and non-delayed data outputs are supplied
synchronous to this signal. In 1:2 demultiplexed mode, this
signal is at 1/2 the input clock rate in SDR mode and at 1/4
the input clock rate in the DDR mode. By default, the DCLK
outputs are not active during the termination resistor trim
section of the calibration cycle. If a system requires DCLK to
run continuously during a calibration cycle, the termination
resistor trim portion of the cycle can be disabled by setting
the Resistor Trim Disable (RTD) bit to logic high in the
Extended Configuration Register (address 9h). This disables
all subsequent termination resistor trims after the initial trim
which occurs during the power on calibration. Therefore, this
output is not recommended as a system clock unless the
resistor trim is disabled. When the device is in the nondemultiplexed mode, DCLK can only be in DDR mode and
the signal is at 1/2 the input clock rate.
92
91
DCLK+
DCLK-
4, 7, 10, 15,
18, 19, 22,
27, 30, 39,
142
VA
NONE
Analog power supply pins. Bypass these pins to ground.
46, 57, 68,
83, 98, 113,
124, 135
VDR
NONE
Output Driver power supply pins. Bypass these pins to DR
GND.
(6)
8
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
2, 3, 8, 11,
14, 23, 26,
29, 35
GND
NONE
Ground return for VA.
48, 59, 70,
74, 84, 97,
107, 111,
122, 133
DR GND
NONE
Ground return for VDR.
1, 36, 37,
38, 69, 71,
72, 73, 108,
109, 110,
143, 144
NC
NONE
Not Connected. These pins are not bonded and may be left
floating or connected to any potential.
112, 123,
134
DNC
NONE
Do Not Connect. These pins are used for internal purposes
and should not be connected, i.e. left floating. Do not ground.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage (VA, VDR)
2.2V
Supply Difference
VDR - VA
0V to 100 mV
Voltage on Any Input Pin
(Except VIN+, VIN- )
−0.15V to (VA +0.15V)
Voltage on VIN+, VIN(Maintaining Common Mode)
-0.15 to 2.5V
Ground Difference
|GND - DR GND|
0V to 100 mV
Input Current at Any Pin
Package Input Current
(3)
±25 mA
(3)
±50 mA
TJ ≤ 145°C
Junction Temperature
ESD Susceptibility (4)
Human Body Model
Machine Model
Charged Device Model
2500V
250V
1000V
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the
Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific
performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications
apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin
should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the
power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms. Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated
assembler) then rapidly being discharged.
Operating Ratings
(1)
(2)
(1) (2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the
Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific
performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications
apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
9
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Operating Ratings (1) (2) (continued)
Ambient Temperature Range
(3)
−40°C ≤ TA ≤ +70°C
Supply Voltage (VA)
+1.8V to +2.0V
Driver Supply Voltage (VDR)
+1.8V to VA
Common Mode Input Voltage
VCMO ± 50 mV
VIN+, VIN− Voltage Range (Maintaining Common Mode)
0V to 2.15V
(100% duty cycle)
0V to 2.5V
(10% duty cycle)
Ground Difference
(|GND − DR GND|)
0V
CLK Pins Voltage Range
0V to VA
Differential CLK Amplitude
0.4VP-P to 2.0VP-P
Common Mode Input Voltage
(3)
VCMO - 50mV < VCMI < VCMO + 50mV
The 4-layer standard JEDEC thermal test board or 4LJEDEC is 4"x3" in size. The board has two embedded copper layers which cover
roughly the same size as the board. The copper thickness for the four layers, starting from the top one, is 2 oz., 1 oz., 1 oz., 2 oz.
Detailed description of the board can be found in the JESD 51-7 standard.
Package Thermal Resistance (1) (2)
(1)
(2)
10
Package
θJA
θJC
psiJB
144-Lead,
LQFP
43.6°C / W
12.5°C / W
39.0°C / W
Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to
www.national.com/packaging.
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Converter Electrical Characteristics Static Converter Characteristics
The following specifications apply after calibration for VA = VDR = 1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 840
mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 500 MHz at 0.5 VP-P with 50% duty cycle; VBG =
Floating; Extended Control Mode default values; DDR 0° Mode; REXT = 4700 Ω ±0.1%; 1:2 Output Demultiplex; Duty Cycle
Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (1) (2).
Symbol
Parameter
Conditions
Typ (3)
Lim
Resolution with No Missing Codes
Units
(Limits)
8
Bits
INL
Integral Non-Linearity
(Best fit)
DC Coupled, 1 MHz Sine Wave
Overanged, SDR, Non-ECM, FSR
= High
±0.3
±0.9
LSB (max)
DNL
Differential Non-Linearity
DC Coupled, 1 MHz Sine Wave
Overanged, SDR, Non-ECM, FSR
= High
±0.15
±0.75
LSB (max)
VOFF
Offset Error
SDR, Non-ECM Mode
−0.45
LSB
VOFF_ADJ
Input Offset Adjustment Range
±45
mV
(4)
Extended Control Mode
PFSE
Positive Full-Scale Error
(5)
NFSE
Negative Full-Scale Error
(5)
Out of Range Output Code
(1)
±25
mV (max)
±25
mV (max)
(VIN+) − (VIN−) > + Full Scale
255
(VIN+) − (VIN−) < − Full Scale
0
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I/O
GND
(2)
(3)
(4)
(5)
To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded.
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average
Outgoing Quality Level).
Only the end points of the range, not the full sweep, are tested in production test.
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. For relationship between Gain Error and FullScale Error, see Specification Definitions for Gain Error.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
11
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Converter Electrical Characteristics Dynamic Converter Characteristics
Symbol
Parameter
FPBW
Full Power Bandwidth
Gain Flatness
Conditions
d.c. to 248 MHz
d.c. to 500 MHz
C.E.R.
Code Error Rate
NPR
Noise Power Ratio
IMD3
3rd order Intermodulation Distortion fIN1 =111.47 MHz @ −7dBFS
fIN2 =121.47 MHz @ −7dBFS
Noise Floor
(2)
(3)
Typ (1)
Lim
2.0
GHz
±0.8
dBFS
±1.0
dBFS
10−18
Error/Sam
ple
38.4
dB
71.4
dBFS
64.4
dBc
-135.4
dBm/Hz
-133.3
ENOB
Effective Number of Bits
AIN = 125 MHz @ -0.5dBFS
7.2
AIN = 248 MHz @ -0.5dBFS
7.2
Signal-to-Noise Plus Distortion
Ratio
AIN = 125 MHz @ -0.5dBFS
45.1
AIN = 248 MHz @ -0.5dBFS
45.1
SNR
Signal-to-Noise Ratio
AIN = 125 MHz @ -0.5dBFS
46
THD
Total Harmonic Distortion
SINAD
2nd Harm
Second Harmonic Distortion
3rd Harm
Third Harmonic Distortion
SFDR
(1)
(2)
(3)
12
Spurious-Free dynamic Range
Units
(Limits)
dBFS/Hz
6.8
bits
bits (min)
42.4
dB
dB (min)
43.5
dB
AIN = 248 MHz @ -0.5dBFS
46
AIN = 125 MHz @ -0.5dBFS
−52
dB (min)
AIN = 248 MHz @ -0.5dBFS
-52
dB (max)
AIN = 125 MHz @ -0.5dBFS
−63
dB
AIN = 248 MHz @ -0.5dBFS
-63
dB
AIN = 125 MHz @ -0.5dBFS
−65
dB
AIN = 248 MHz @ -0.5dBFS
-65
dB
AIN = 125 MHz @ -0.5dBFS
55
AIN = 248 MHz @ -0.5dBFS
55
-49
49
dB
dB
dB (min)
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average
Outgoing Quality Level).
The NPR was measured using an Agilent N6030A Arbitrary Waveform Generator (ARB) to generate the input signal. The "noise" portion
of the signal was created by tones spaced at 500 kHz and the "notch" was a 12.5 MHz absence of tones centered at 175 MHz.
For the case where the inputs are shorted or terminted with 50Ω, the LSB of the ADC never transitions because the Noise Floor is
limited by quantization noise, not thermal noise. Therefore, the Noise Floor was measured with a low-level wideband input from 10 MHz
to 30 MHz; the noise floor was measured in the band from 126 MHz to 175 MHz.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Converter Electrical Characteristics Analog Input/Output and Reference Characteristics
Symbol
Typ (1)
Lim
Units
(Limits)
FSR Pin High, SDR
840
900
mVP-P
FSR Pin Low, SDR
650
mVP-P
FS_ADJ(15:7) = 1111 1111 1b
840
mVP-P
FS_ADJ(15:7) = 1000 0000 0b (default)
700
mVP-P
FS_ADJ(15:7) = 0000 0000 0b
560
mVP-P
Differential
Parameter
Conditions
Analog Inputs
VIN_FSR
Analog Differential Input Full Scale
Range
Non-Extended Control Mode (2)
Extended Control Mode
CIN
Analog Input Capacitance
RIN
(4) (5) (6)
Differential Input Resistance
(3)
0.02
pF
Each input pin to ground
1.6
pF
Measured at D.C.
140
Ω
ICMO = ±100 µA
1.26
Common Mode Output
VCMO
Common Mode Output Voltage
0.9
V (min)
1.6
V (max)
Bandgap Reference
VBG
Bandgap Reference Output Voltage
IBG = ±100 µA
TC_VBG
Bandgap Reference Voltage
Temperature Coefficient
TA = −40°C to +70°C, 182456
IBG = ±100 µA
CLOAD VBG
Maximum Bandgap Reference load
Capacitance
(1)
(2)
(3)
(4)
(5)
(6)
1.26
V
28
ppm/°C
80
pF
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average
Outgoing Quality Level).
This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only.
Only the end points of the range, not the full sweep, are tested in production test.
The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
This parameter is guaranteed by design and is not tested in production.
The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: ADC08DL500
13
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Converter Electrical Characteristics I-Channel to Q-Channel Characteristics
Symbol
Parameter
Conditions
Offset Match
X-TALK
(1)
14
Typ (1)
Lim
Units
(Limits)
1
LSB
Positive Full-Scale Match
Zero offset selected in Control
Register
1
LSB
Negative Full-Scale Match
Zero offset selected in Control
Register
1
LSB
Phase Matching (I, Q)
fIN = 500 MHz
工商网监
湘ICP备2023018690号
