ADC121S705EB/NOPB

National Semiconductor January 18, 2007 Rev – 1.1/CS RoHS Compliant Evaluation Board User's Guide ADC121S705 12-Bit, 500 kSPS to 1 MSPS, Differential Input, Micro-Power Sampling A/D Converter Table of Contents 1.0 Introduction 3 2.0 Board Assembly 3 3.0 Quick Start 4 3.1 Stand Alone Mode 4 3.2 Computer Mode 4 4.0 Functional Description 5 4.1 Analog Input Signal 5 4.2 ADC Reference Circuitry 5 4.3 SPI Interface 5 4.4 Power Supply Connections 6 5.0 Software Operation and Settings 6 6.0 Evaluation Board Specifications 7 7.0 Tables of Test Points, Jumpers and Connectors 7 8.0 Hardware Schematic 8 9.0 ADC121S705 Evaluation Board Bill of Materials 9 2 http://www.national.com 1.0 Introduction The ADC121S705EB/RoHS Design Kit (consisting of the ADC121S705 Evaluation Board and this User's Guide) is designed to ease evaluation and design-in of the National Semiconductor ADC121S705 12-bit Analog-to-Digital Converter, which can operate at speeds up to 1 MSPS. is digitized, captured, and displayed on a PC monitor in the time and frequency domain. The evaluation board can be used in either of two modes. In the Stand-Alone or Manual mode, suitable test equipment, such as a logic analyzer, can be used with the board to evaluate the ADC121S705’s performance. The differential signal at analog inputs J2 (accoupled) or J3 (dc-coupled) is digitized by U1, the ADC121S705. In the Computer or Automatic mode, data capture and evaluation is simplified by connecting this board to National Semiconductor's Data Capture Board (order number WAVEVSN BRD 4.1) which is connected to a personal computer through a USB port and is running WaveVision4 software. The WaveVision4 program can be downloaded from the web at http://www.national.com/adc. The software will perform an FFT on the captured data upon command. This FFT plot shows dynamic performance in the form of SNR, SINAD, THD, SFDR and ENOB. A histogram of the captured data is also available. The ADC121S705 uses an oscillator that is provided on this board by Y2 or is supplied at J6. 2.0 Board Assembly The ADC121S705 evaluation board comes fully assembled and ready for use. Refer to the Bill of Materials for a description of components, to Figure 1 for major component placement and to Figure 2 for the Evaluation Board schematic. The WaveVision4 software operates under Microsoft Windows. The signal at the Analog Input U1 DUT VREF select WV4 connector J2 VIN JP5 CLK select 5V remote Y2 CLK OSC J6 EXT CLK input Figure 1 Component and Test Point Locations 3 http://www.national.com 3.0 Quick Start The ADC121S705 evaluation board may be used in the Stand-Alone mode to capture data with a logic analyzer or third party equipment, or it may be used in the Computer Mode with a WaveVision4.1 Data Capture (WV) Board. In both cases, the data may be analyzed with the WaveVision4 software. 3.1 Stand Alone Mode Refer to Figure 1 for locations of test points and major components. 1. Remove the jumper from JP5 and the oscillator Y2 from its socket. The SPI interface signals (CSB and SCLK) will be driven directly at J4 (step 10). DOUT will also be monitored at J4. Frequently a Logic Analyzer with a built in pattern generator is used to drive CSB and SCLK while monitoring DOUT. It is necessary to remove Y2 because the presence of a second clock source could add noise to the conversion process. 2. Connect a clean analog (non-switching) +5V power source to Power Connector J5. 3. Short pins 1 & 2 of JP3 and turn on the power supply. 4. Dynamic differential signal sources centered around ground (ac-coupled) should be connected across pins 1 & 3 of J2. Pin 2 of J2 is ground. If the source has a 50 ohm output impedance, install a 51 ohm resistor at R4. Otherwise, the signal level will be twice as large as expected. To accurately evaluate the performance of the ADC121S705, the source must be better than 90dB THD. 5. Short pins 1 & 2 and pins 3 & 4 of JP2 to bias the input of the ADC121S705 at VREF. It is necessary to bias the inputs when driving the ADC from J2. 6. Differential DC sources or dynamic differential signal sources centered at a DC bias point should be connected across pins 1 & 3 of J3. Pin 2 of J3 is ground. Refer to the datasheet for acceptable common mode input voltages. 7. Remove the shorts across pins 1 & 2 and pins 3 & 4 of JP2 when driving the ADC input from J3. An external bias voltage for the ADC121S705 is not required under this circumstance. 8. Select the 2.5V shunt voltage reference as VREF by shorting pins 2 & 3 of JP1. This accomplishes two things at the same time. It provides a reference voltage of 2.5V for the 4 ADC121S705 and it biases the input stage at 2.5V (sets the input’s common mode voltage). 9. If it is desirable to provide an external reference voltage, the jumper must be removed from JP1 and pin 2 may be driven directly. Refer to the datasheet for acceptable common mode voltages ranges for specific reference voltages. Ideally the ADC121S705 is biased at half of the supply voltage, VA. 10. Apply the signals to control the SPI interface at J4. 3.2 Computer Mode Refer to Figure 1 for locations of test points and major components. 1. Run the WaveVision4 program. Version 4.3 or higher is required to interface the WaveVision4.1 Data Capture (WV) board with the ADC121S705 evaluation board. While the program is loading, continue below. 2. Connect an analog +5V power source to power connector J1 on the WV board and turn on the power. 3. Connect a USB cable between the WV Board and the PC running the WaveVision4 program. 4. Connect J1 of the ADC121S705 board to J7 of the WV board. 5. Connect a separate, clean analog (nonswitching) +5V power source to Power Connector J5 of the . 6. Short pins 1 & 2 of JP3 and turn on the power supply. See Section 4.5 for detailed Power Supply Information. 7. Install an appropriate crystal oscillator into socket Y2 and short pins 1 & 2 of JP5 (See Table 1). Alternatively, connect a signal generator with CMOS logic levels to BNC connector J6 and short pins 2 & 3 of JP5. 8. Perform steps 4 & 5 or 6 & 7 of section 3.1 to drive the analog inputs. 9. Perform step 8 or 9 of section 3.1 to select the reference voltage. 10. Refer to section 5.0 on Software Operation and Settings. http://www.national.com 4.0 Functional Description Table 1 describes the function of the various jumpers on the ADC121S705 evaluation board. The Evaluation Board schematic is shown in Figure 2. Jumper Pins 1 & 2 Pins 2 & 3 JP1 Select VA as VREF Select 2.5V reg. as VREF JP2 Short pins 1 & 2 and pins 3 & 4 to bias input pins at VREF JP3 JP4 JP5 Select 5P0V_REMOTE from J5 Select 5P0V from J1 (WV) Enable OSC (not required) Select on-board clock OSC Y2 Select clock OSC at BNC J6 Table 1 Jumper Functions 4.1 Analog Input Signal The input signal to be digitized should be applied across pins 1 & 3 of J2 or J3. For input signals centered around ground, J2 should be utilized. Pin 2 of J2 is ground. Resistor R4 is a terminating resistor for the input source. Since all sources do not have the same output impedance, R4 is not stuffed. However, it is recommended that it is stuffed by the end user with the appropriate value that matches the source. The DC biasing for inputs applied to J2 is supplied through JP2. Short pins 1 & 2 and 3 & 4 of JP2 to properly bias the input to VREF. If it is desired to digitize a differential DC voltage or a dynamic signal that is already properly biased for the ADC121S705, apply the signal to be digitized across pins 1 & 3 of J3. Pin 2 of J3 is ground. When applying the input at J3, all shorts on JP2 need to be removed. If VA is selected as the reference voltage, the input signal must be applied at J3 and thus requires proper dc-biasing. Under this circumstance, JP2 is no longer capable of providing a proper dc-bias voltage for the input to the ADC121S705 since it is directly connected to VA through R2 and R3. If the input signal is not properly biased, the side of R2 and R3 that connects to VREF would need to be lifted and driven with a voltage of VA / 2. This allows the maximum voltage swing at +IN and –IN. 5 Dynamic input signals should be applied through a bandpass filter to eliminate the noise and harmonics commonly associated with signal sources. To accurately evaluate the performance of the ADC121S705, the source must be better than -90dBc THD 4.2 ADC Reference Circuitry This evaluation board includes the option of selecting a fixed 2.5V shunt voltage reference or VA as the reference voltage. Select the 2.5V reference as VREF by shorting pins 2 & 3 of JP1 or select VA as VREF by shorting pins 1 & 2 of JP1. If it is desirable to provide an external reference voltage, the jumper must be removed from JP1 and pin 2 may be driven directly. If it is desirable to change the LM4040DIM3-2.5 to an LM4040 with a different voltage, carefully change it and adjust the value of R1 to limit the current through the LM4040. 4.3 SPI Interface 4.3.1 ADC Clock (SCLK) The crystal-based oscillator provided on the evaluation board is selected by shorting pins 1 & 2 of JP5. It is best to remove any external signal generator from J6 when using this oscillator to reduce any unnecessary noise. This board will also accept a clock signal from an external source by connecting that source to BNC J6 and shorting pins 2 & 3 of JP5. The input applied at J6 is 51 ohm terminated by R14. The external clock signal must meet CMOS input requirements. If the external source is an acsource that is centered around ground, the short across C15 can be cut and C15 should be populated with a 0.1uF capacitor. It is also necessary to populate R15 and R16 with 5.1k ohm resistors. To reduce any unnecessary noise, it is best to remove the oscillator at Y2 when using an external clock source. Regardless of the clock source selected by JP5, the clock signal is designed to be routed off the ADC121S705 evaluation board to the WV board. This assumes a “computer mode” operation of the evaluation board. For applications utilizing the evaluation board in manual mode, the clock is applied directly at J4. 4.3.2 Digital Data Output (DOUT) The DOUT pin from this board may be monitored at J1 or J4. In “computer mode” DOUT is monitored by the WV board. In “manual mode” DOUT should be monitored directly at J4. The http://www.national.com signal level for DOUT is CMOS compatible. See the ADC121S705 datasheet for logic output levels. 4.3.3 Chip Select Bar (CSB) The CSB pin may be monitored at J1 or J4. In “computer mode” CSB is provided by the WV board. In “manual mode” CSB should be driven directly at J4. The signal level for CSB needs to be CMOS compatible. See the ADC121S705 datasheet for logic threshold limits. 4.4 Power Supply Connections In “computer and manual mode”, the remote 5P0V voltage needs to be set between +4.5V and +5.5V. When operating in “computer mode”, the supply voltage for VA can be applied remotely at J5 or is supplied directly by the WV board through J1. The remote 5P0V voltage is selected by shorting pins 1 & 2 on JP3. While the 5P0V from the WV board is selected by shorting pins 2 & 3 on JP3. For best performance from the ADC121S705, a remote supply voltage should be applied to J5. The 3P3V voltage is always obtained through J1 from the WV board/ 5. After the steps outlined in Section 3.2 are completed, click on ‘Acquire’ then ‘Samples’ from the Main Menu (you can also press the F1 shortcut key). If a dialog box opens, select ‘Discard’ or press the Escape key to start collecting new, updated samples. A plot of the selected number of samples will be displayed. Make sure there is no clipping of data samples. The samples may be further analyzed by clicking on the magnifying glass icon, then clicking and dragging across a specific area of the plot for better data inspection. See the WaveVision4 Board User's Guide for details. To view an FFT of the data captured, click on the ‘FFT’ tab. This plot may be zoomed in on like the data plot. A display of dynamic performance parameters in the form of SINAD, SNR, THD, SFDR and ENOB will be displayed at the top right hand corner of the FFT plot. Acquired data may be saved to a file. Plots may also be exported as graphics. See the Data Capture Board User's Guide for details. When operating in “manual mode”, only voltage 5P0V needs to be applied to J5 and pins 1 & 2 on JP3 need to be shorted. 5.0 Software Operation and Settings The WaveVision4 software is included with the WV board and the latest version can be downloaded for free from National's web site at http://www.national.com/adc. To install this software, follow the procedure in the WaveVision4.1 Board User's Guide. Once the software is installed, run it and set it up as follows: 1. Connect the WV board to the host computer with a USB cable. 2. From the WaveVision main menu, go to Settings, then Board Settings and do the following: Select the following from the WaveVision4 main menu: • WaveVision 4.0 (USB) • # of Samples: 2K to 32K, as desired 3. Apply power as specified in Section 4.5, click on the "Test" button and await the firmware to download. 4. Click on the "Accept" button. 6 http://www.national.com 6.0 Evaluation Board Specifications Board Size: Power Requirements Clock Frequency Range: Analog Input 3.0" x 3.0" (7.6 cm x 7.6 cm) Min: +4.5V, Max: +5.5V, 100mA 100 mA 800 kHz to 4.0 MHz 0V to 2VREF 7.0 Test Points, Connectors, and Jumpers Test Points on the ADC121S705 Evaluation Board TP1: AGND Ground. Located at the bottom right area of the board. TP2: AGND Ground. Located at the center of the board. TP3: AGND Ground. Located at the top left area of the board. TP4: VA VA test point. Located at the center of the board. TP5: 3P3V 3.3V test point. Located at the middle right area of the board. TP6: AGND Ground. Located at the top right corner of the board. TP7: AGND Ground. Located in the middle right area of the board. Connectors on the ADC121S705 Evaluation Board J1: WV4S 14 pin dual row right angle male header: Connects to WV4.1 board. J2: VIN_AC Three pin male header: Differential AC input. J3: VIN_DC Three pin male header: Differential DC input. J4: WV4 14 pin dual row male header: Connects to WV4.0 board. J5: 5P0V_REMOTE Terminal Block: Power connector for 5P0V. J6: CLK_IN BNC Connector: External clock input. Selection Jumpers on the ADC121S705 Evaluation Board (Refer to Table 1 in Section 4.0 for configuration details) 7 JP1: VREF SELECT Selects reference source for VREF. JP2: VBIAS Provides DC bias for analog inputs. JP3: VA Selection Selects source of voltage for VA. JP4: OSC ENABLE Not required for OSC provided with evaluation board. JP5: CLK_SELECT Selects clock source (on-board oscillator or external source). http://www.national.com A B C 5 J2 VIN_AC 1 2 3 TP4 VA C6 D3 1N4001 2 1 J5 5P0V_REMOTE VA R4 NS C5 1 1 1.0uF C14 2 5P0V_REMOTE 4 5P0V_REMOTE RED LED D1 R7 510 J3 VIN_DC 1.0uF VA JP2 HEADER 2X2 3 1 1.0uF R3 5.1K TP7 AGND JP3 VA SELECTION L2 100uH 5P0V 1 VREF 3 2 R2 5.1K VA C1 R15 C2 0.1uF OUT J6 CLK NS 8 C8 OUT 2 NS C15 R16 VA R11 51 R14 51 NS C3 Y1 NS 1 1.0uF C10 VA JP4 OSC ENABLE 3P3V R5 NS R6 0 14 5 7 4 6 8 SCLK DOUT 13 14 R9 NS 1.0uF TP6 AGND C12 0.1uF C11 3P3V 11 12 SDA 3P3V 9 10 CLKSEND 3 2 CSB 1 12 13 3P3V 11 SDA 10 9 CLKSEND SCL SCL 5P0V R10 NS 3P3V 3 If the external source applied at J6 is an ac-source that is centered around ground, the short across C15 can be cut and C15 should be populated with a 0.1uF capacitor. It is also necessary to populate R15 and R16 with 5.1k ohm resistors. CLKSEND 1 2 L1 100uH 8 CLKSEND 6 7 4 5 6 5 DOUT 2 3 SCLK 7 J4 WV4 J1 WV4S 1 1.0uF C4 TP1 AGND CSB 0.1uF VA 8 Y2 OSC (THROUGH-HOLE) 1 OE CSB DOUT SCLK TP3 AGND JP5 CLK SELECT OE 3 NS GND -IN +IN VREF U1 ADC121S705CIMM C9 4 3 2 1 1 2 3 470pF 470pF C7 0.1uF C13 1.0uF 2K U2 LM4040/SOT23 R1 3 1 VREF SELECT JP1 1 2 TP2 AGND 2 4 VA 1 1 2 3 1 14 VDD GND 7 3 1 1 4 VDD GND 2 8 4 1 7 VCC 1 A0 6 WP A1 2 SCL 5 SDA A2 3 GND 4 D 5 U3 24C02 2 3P3V 2 RED LED D2 R8 200 TP5 3P3V 1 Date: Size C Title ADC121S705 Evaluation Board 1 Tuesday, November 29, 2005 Document Number 870012728-100A 1 Sheet 1 of 1 Rev 1.0 A B C D ADC121S705 Evaluation Board Revised: Thursday, January 17, 2007 870012728-100A Revision: 1.0 Bill Of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Quantity Reference Description Value Rating Pacakage Critical Source Source Part # 7 C1,C4,C5,C6,C10,C11,C14 CAP 1.0uF 50V sm/c_1206 4 C2,C3,C12,C13 CAP 0.1uF 50V sm/c_0805 2 C8,C7 CAP 470pF 50V sm/c_0805 2 C15,C9 CAP NS 50V sm/c_0805 2 D2,D1 LED RED LED sm/led_21 Digikey 516-1440-1-ND 1 D3 DIO 1N4001 or IN4003 DAX2/DO41 Digikey 1N4001GICT-ND 1 JP1 HEAD VREF SELECT header Digikey A26513-40-ND 1 JP2 HEAD HEADER 2X2 header Digikey A26529-40-ND 1 JP3 HEAD VA SELECTION header Digikey A26513-40-ND 1 JP4 HEAD OSC ENABLE header Digikey A26513-40-ND 1 JP5 HEAD CLK SELECT header Digikey A26513-40-ND 1 J1 HEAD WV4S rt angle header Digikey S2200-07-ND 1 J2 HEAD VIN_AC header Digikey A26513-40-ND 1 J3 HEAD VIN_DC header Digikey A26513-40-ND 1 J4 HEAD WV4 header Digikey A26529-40-ND 1 J5 TERM 5P0V_REMOTE term_block Digikey ED1609-ND 1 J6 BNC CLK BNC Digikey ARF1177-ND 2 L1,L2 IND 100uH sm/l_1210 Digikey 445-1155-1-ND 1 R1 RES 2K sm/r_0805 2 R3,R2 RES 5.1K sm/r_0805 6 R4,R5,R9,R10,R15,R16 RES NS sm/r_0805 1 R6 RES 0 sm/r_0805 1 R7 RES 510 sm/r_0805 1 R8 RES 200 sm/r_0805 2 R14,R11 RES 51 sm/r_0805 5 TP1,TP2,TP3,TP6,TP7 TP AGND header Digikey A26513-40-ND 1 TP4 TP VA header Digikey A26513-40-ND 1 TP5 TP 3P3V header Digikey A26513-40-ND 1 U1 IC ADC121S705CIMM MSOP8 1 U2 REF LM4040/SOT23 sm/SOT23 Digikey LM4040DIM3-2.5CT-ND 1 U3 EEPROM 24C02 EEPROM 1 Y2A OSC 16.0MHz OSC OSC 1 Y2B SOCK SOCKET OSC_socket Digikey A462-ND 1 PCB PCB ADC121S725 Eval Board Adv Cir 121S725_r1 5 2-pin jumpers SHUNT 4 Rubber Feet BUMP BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF NATIONAL SEMICONDUCTOR'S END USER LICENSE AGREEMENT. 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