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ADC12D2000RFIUT

ADC12D2000RFIUT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    BBGA292

  • 描述:

    IC ADC 12BIT FOLD INTERP 292BGA

  • 数据手册
  • 价格&库存
ADC12D2000RFIUT 数据手册
ADC12D2000RF 12-Bit, Single 4.0 GSPS RF Sampling ADC 1.0 General Description 3.0 Features The 12-bit 2.0 GSPS ADC12D2000RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D2000RF augments the very large Nyquist zone of Texas Instruments’ GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone. The ADC12D2000RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C. To achieve the full rated performance for Fclk > 1.6 GHz, it is necessary to write the max power settings once to Register 6h via the Serial Interface; see Section 19.0 Register Definitions for more information. ■ Excellent noise and linearity up to and above fIN = 2.7 GHz ■ Configurable to either 4.0 GSPS interleaved or 2.0 GSPS 2.0 Applications ■ 3G/4G Wireless Basestation ■ ■ ■ ■ ■ ■ ■ ■ — Receive Path — DPD Path Wideband Microwave Backhaul RF Sampling Software Defined Radio Military Communications SIGINT RADAR / LIDAR Wideband Communications Consumer RF Test and Measurement dual ADC ■ New DESCLKIQ Mode for high bandwidth, high sampling ■ ■ ■ ■ ■ ■ ■ rate apps Pin-compatible with ADC1xD1x00, ADC12Dx00RF Internally terminated, buffered, differential analog inputs Interleaved timing automatic and manual skew adjust Test patterns at output for system debug Time Stamp feature to capture external trigger Programmable gain, offset, and tAD adjust feature 1:1 non-demuxed or 1:2 demuxed LVDS outputs 4.0 Key Specifications ■ Resolution 12 Bits Interleaved 4.0 GSPS ADC ■ IMD3 (Fin = 2.7GHz @ -13dBFS) ■ IMD3 (Fin = 2.7GHz @ -16dBFS) ■ Noise Floor Density ■ Power -60.6 dBc (typ) -64.7 dBc (typ) -154 dBm/Hz (typ) 4.6 W (typ) Dual 2.0 GSPS ADC, Fin = 498 MHz ■ ENOB ■ SNR ■ SFDR ■ Power per Channel 8.7 Bits (typ) 54.8 dB (typ) 64.6 dBc (typ) 2.3 W (typ) 5.0 Block Diagram 30173711 © 2012 Texas Instruments Incorporated 301737 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC June 26, 2012 -40 -7 dBFS -10 dBFS -13 dBFS -16 dBFS IMD3 (dBFS) -50 -60 -70 -80 -90 -100 0 1 2 3 INPUT FREQUENCY (GHz) 4 30173798 ADC12D2000RF Non-DES Mode IMD3 0 AMPLITUDE (dBFS) ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC 6.0 RF Performance Fin = 2.7 GHz -30 -60 -90 -120 1300 1310 1320 1330 FREQUENCY (MHz) 1340 30173714 ADC12D2000RF DES Mode FFT CW Blocker: Fin = 2675 MHz; Total Power = -13 dBFS WCDMA Blocker: Fc = 2685 MHz; Bandwidth = 3.84 MHz; Total Power = -13 dBFS IMD3 Product Power = -74 dBFS www.ti.com 2 ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC 7.0 Connection Diagram 30173701 FIGURE 1. ADC12D2000RF Connection Diagram The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Section 18.5 SUPPLY / GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS for more information. 8.0 Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) NS Package ADC12D2000RFIUT/NOPB Lead-free 292-Ball BGA Thermally Enhanced Package ADC12D2000RFIUT Leaded 292-Ball BGA Thermally Enhanced Package ADC12D2000RFRB Reference Board 3 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Table of Contents 1.0 General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Features ........................................................................................................................................ 1 4.0 Key Specifications ........................................................................................................................... 1 5.0 Block Diagram ................................................................................................................................ 1 6.0 RF Performance .............................................................................................................................. 2 7.0 Connection Diagram ........................................................................................................................ 3 8.0 Ordering Information ....................................................................................................................... 3 9.0 Ball Descriptions and Equivalent Circuits ............................................................................................ 7 10.0 Absolute Maximum Ratings ........................................................................................................... 16 11.0 Operating Ratings ....................................................................................................................... 16 12.0 Converter Electrical Characteristics ................................................................................................ 17 13.0 Specification Definitions ................................................................................................................ 28 14.0 Transfer Characteristic ................................................................................................................. 30 15.0 Timing Diagrams ......................................................................................................................... 31 16.0 Typical Performance Plots ............................................................................................................ 34 17.0 Functional Description .................................................................................................................. 39 17.1 OVERVIEW ......................................................................................................................... 39 17.2 CONTROL MODES .............................................................................................................. 39 17.2.1 Non-Extended Control Mode ........................................................................................ 39 17.2.1.1 Dual Edge Sampling Pin (DES) ........................................................................... 39 17.2.1.2 Non-Demultiplexed Mode Pin (NDM) ................................................................... 39 17.2.1.3 Dual Data Rate Phase Pin (DDRPh) .................................................................... 40 17.2.1.4 Calibration Pin (CAL) ......................................................................................... 40 17.2.1.5 Calibration Delay Pin (CalDly) ............................................................................ 40 17.2.1.6 Power Down I-channel Pin (PDI) ......................................................................... 40 17.2.1.7 Power Down Q-channel Pin (PDQ) ...................................................................... 40 17.2.1.8 Test Pattern Mode Pin (TPM) ............................................................................. 40 17.2.1.9 Full-Scale Input Range Pin (FSR) ....................................................................... 40 17.2.1.10 AC / DC-Coupled Mode Pin (VCMO) ................................................................... 40 17.2.1.11 LVDS Output Common-mode Pin (VBG) ............................................................. 40 17.2.2 Extended Control Mode ............................................................................................... 41 17.2.2.1 The Serial Interface ........................................................................................... 41 17.3 FEATURES ......................................................................................................................... 42 17.3.1 Input Control and Adjust .............................................................................................. 43 17.3.1.1 AC/DC-coupled Mode ........................................................................................ 43 17.3.1.2 Input Full-Scale Range Adjust ............................................................................ 43 17.3.1.3 Input Offset Adjust ............................................................................................ 43 17.3.1.4 DES/Non-DES Mode ......................................................................................... 43 17.3.1.5 DES Timing Adjust ............................................................................................ 44 17.3.1.6 Sampling Clock Phase Adjust ............................................................................. 44 17.3.2 Output Control and Adjust ............................................................................................ 44 17.3.2.1 SDR / DDR Clock ............................................................................................. 44 17.3.2.2 LVDS Output Differential Voltage ........................................................................ 45 17.3.2.3 LVDS Output Common-Mode Voltage ................................................................. 45 17.3.2.4 Output Formatting ............................................................................................. 45 17.3.2.5 Demux/Non-demux Mode .................................................................................. 45 17.3.2.6 Test Pattern Mode ............................................................................................ 45 17.3.2.7 Time Stamp ..................................................................................................... 45 17.3.3 Calibration Feature ..................................................................................................... 45 17.3.3.1 Calibration Control Pins and Bits ......................................................................... 46 17.3.3.2 How to Execute a Calibration .............................................................................. 46 17.3.3.3 Power-on Calibration ......................................................................................... 46 17.3.3.4 On-command Calibration ................................................................................... 46 17.3.3.5 Calibration Adjust .............................................................................................. 46 17.3.3.6 Read / Write Calibration Settings ........................................................................ 46 17.3.3.7 Calibration and Power-Down .............................................................................. 47 17.3.3.8 Calibration and the Digital Outputs ...................................................................... 47 17.3.4 Power Down .............................................................................................................. 47 18.0 Applications Information ............................................................................................................... 48 18.1 THE ANALOG INPUTS ......................................................................................................... 48 18.1.1 Acquiring the Input ...................................................................................................... 48 18.1.2 Driving the ADC in DES Mode ...................................................................................... 48 18.1.3 FSR and the Reference Voltage ................................................................................... 48 www.ti.com 4 48 49 49 49 49 49 49 50 50 50 50 50 50 50 50 50 51 51 51 51 51 51 51 53 53 53 55 55 55 56 56 56 57 64 List of Figures FIGURE 1. ADC12D2000RF Connection Diagram ............................................................................................ 3 FIGURE 2. LVDS Output Signal Levels ......................................................................................................... 28 FIGURE 3. Input / Output Transfer Characteristic ............................................................................................ 30 FIGURE 4. Clocking in 1:2 Demux Non-DES Mode* ......................................................................................... 31 FIGURE 5. Clocking in Non-Demux Non-DES Mode* ........................................................................................ 31 FIGURE 6. Clocking in 1:4 Demux DES Mode* ............................................................................................... 32 FIGURE 7. Clocking in Non-Demux Mode DES Mode* ...................................................................................... 32 FIGURE 8. Data Clock Reset Timing (Demux Mode) ........................................................................................ 33 FIGURE 9. Power-on and On-Command Calibration Timing ................................................................................ 33 FIGURE 10. Serial Interface Timing ............................................................................................................. 33 FIGURE 11. Serial Data Protocol - Read Operation .......................................................................................... 41 FIGURE 12. Serial Data Protocol - Write Operation .......................................................................................... 42 FIGURE 13. DDR DCLK-to-Data Phase Relationship ........................................................................................ 44 FIGURE 14. SDR DCLK-to-Data Phase Relationship ........................................................................................ 44 FIGURE 15. Driving DESIQ Mode ............................................................................................................... 48 FIGURE 16. AC-coupled Differential Input ..................................................................................................... 49 FIGURE 17. Single-Ended to Differential Conversion Using a Balun ...................................................................... 49 FIGURE 18. Differential Input Clock Connection .............................................................................................. 49 FIGURE 19. Power and Grounding Example .................................................................................................. 52 FIGURE 20. HSBGA Conceptual Drawing ..................................................................................................... 53 FIGURE 21. Power-on with Control Pins set by Pull-up / down Resistors ................................................................ 54 FIGURE 22. Power-on with Control Pins set by FPGA pre Power-on Cal ................................................................ 54 FIGURE 23. Power-on with Control Pins set by FPGA post Power-on Cal ............................................................... 55 FIGURE 24. Supply and DCLK Ramping ....................................................................................................... 55 FIGURE 25. Typical Temperature Sensor Application ....................................................................................... 56 List of Tables TABLE 1. Analog Front-End and Clock Balls ................................................................................................... 7 TABLE 2. Control and Status Balls .............................................................................................................. 10 TABLE 3. Power and Ground Balls .............................................................................................................. 13 5 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC 18.1.4 Out-Of-Range Indication .............................................................................................. 18.1.5 Maximum Input Range ................................................................................................ 18.1.6 AC-coupled Input Signals ............................................................................................ 18.1.7 DC-coupled Input Signals ............................................................................................ 18.1.8 Single-Ended Input Signals .......................................................................................... 18.2 THE CLOCK INPUTS ........................................................................................................... 18.2.1 CLK Coupling ............................................................................................................. 18.2.2 CLK Frequency .......................................................................................................... 18.2.3 CLK Level .................................................................................................................. 18.2.4 CLK Duty Cycle .......................................................................................................... 18.2.5 CLK Jitter .................................................................................................................. 18.2.6 CLK Layout ................................................................................................................ 18.3 THE LVDS OUTPUTS ........................................................................................................... 18.3.1 Common-mode and Differential Voltage ......................................................................... 18.3.2 Output Data Rate ........................................................................................................ 18.3.3 Terminating Unused LVDS Output Pins ......................................................................... 18.4 SYNCHRONIZING MULTIPLE ADC12D2000RFS IN A SYSTEM ................................................ 18.4.1 DCLK Reset Feature ................................................................................................... 18.5 SUPPLY / GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS ................................ 18.5.1 Power Planes ............................................................................................................. 18.5.2 Bypass Capacitors ...................................................................................................... 18.5.3 Ground Planes ........................................................................................................... 18.5.4 Power System Example ............................................................................................... 18.5.5 Thermal Management ................................................................................................. 18.6 SYSTEM POWER-ON CONSIDERATIONS ............................................................................. 18.6.1 Power-on, Configuration, and Calibration ....................................................................... 18.6.2 Power-on and Data Clock (DCLK) ................................................................................. 18.7 RECOMMENDED SYSTEM CHIPS ........................................................................................ 18.7.1 Temperature Sensor ................................................................................................... 18.7.2 Clocking Device ......................................................................................................... 18.7.3 Amplifiers for Analog Input ........................................................................................... 18.7.4 Balun Recommendations for Analog Input ...................................................................... 19.0 Register Definitions ...................................................................................................................... 20.0 Physical Dimensions .................................................................................................................... ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC TABLE 4. High-Speed Digital Outputs .......................................................................................................... TABLE 5. Package Thermal Resistance ........................................................................................................ TABLE 6. Static Converter Characteristics ..................................................................................................... TABLE 7. Dynamic Converter Characteristics ................................................................................................ TABLE 8. Analog Input / Output and Reference Characteristics ............................................................................ TABLE 9. I-Channel to Q-Channel Characteristics ............................................................................................ TABLE 10. Sampling Clock Characteristics ................................................................................................... TABLE 11. Digital Control and Output Pin Characteristics ................................................................................... TABLE 12. Power Supply Characteristics ...................................................................................................... TABLE 13. AC Electrical Characteristics ........................................................................................................ TABLE 14. Serial Port Interface ................................................................................................................. TABLE 15. Calibration ............................................................................................................................. TABLE 16. Non-ECM Pin Summary ............................................................................................................. TABLE 17. Serial Interface Pins .................................................................................................................. TABLE 18. Command and Data Field Definitions ............................................................................................. TABLE 19. Features and Modes ................................................................................................................ TABLE 20. Supported Demux, Data Rate Modes ............................................................................................. TABLE 21. Test Pattern by Output Port in Demux Mode .................................................................................... TABLE 22. Test Pattern by Output Port in Non-Demux Mode .............................................................................. TABLE 23. Calibration Pins ....................................................................................................................... TABLE 24. Unused Analog Input Recommended Termination ............................................................................. TABLE 25. Unused AutoSync and DCLK Reset Pin Recommendation ................................................................... TABLE 26. Temperature Sensor Recommendation .......................................................................................... TABLE 27. Amplifier Recommendation ......................................................................................................... TABLE 28. Balun Recommendations ............................................................................................................ TABLE 29. Register Addresses .................................................................................................................. www.ti.com 6 14 16 17 17 21 22 22 23 24 24 26 26 39 41 41 42 45 45 45 46 48 51 55 56 56 57 TABLE 1. Analog Front-End and Clock Balls Ball No. Name H1/J1 N1/M1 VinI+/VinQ+/- U2/V1 V2/W1 Equivalent Circuit Description Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input. In Extended Control Mode (ECM), the Qinput may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6). Each I- and Q-channel input has an internal common mode bias that is disabled when DC-coupled Mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO Pin. In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Qchannels have the same full-scale input range. In ECM, the full-scale input range of the I- and Qchannel inputs may be independently set via the Control Register (Addr: 3h and Addr: Bh). The input offset may also be adjusted in ECM. CLK+/- Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES Mode, the selected input is sampled on both transitions of this clock. This clock must be AC-coupled. DCLK_RST+/- Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D2000RFs in order to synchronize them with other ADC12D2000RFs in the system. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. 7 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC 9.0 Ball Descriptions and Equivalent Circuits ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Ball No. C2 B1 C3/D3 C1/D2 E2/F3 www.ti.com Name Equivalent Circuit Description VCMO Common Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be held at logic-low level. This pin is capable of sourcing/ sinking up to 100 µA. For DC-coupled operation, this pin should be left floating or terminated into high-impedance. In DC-coupled Mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. VBG Bandgap Voltage Output or LVDS Commonmode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing / sinking 100 uA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2V LVDS common-mode voltage is selected; 0.8V is the default. Rext+/- External Reference Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rext+/-. The Rext resistor is used as a reference to trim internal circuits which affect the linearity of the converter; the value and precision of this resistor should not be compromised. Rtrim+/- Input Termination Trim Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rtrim+/-. The Rtrim resistor is used to establish the calibrated 100Ω input impedance of VinI, VinQ and CLK. These impedances may be fine tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not guaranteed for such an alternate value. Tdiode+/- Temperature Sensor Diode Positive (Anode) and Negative (Cathode) Terminals. This set of pins is used for die temperature measurements. It has not been fully characterized. 8 Y4/W5 Y5/U6 V6/V7 Name Equivalent Circuit Description RCLK+/- Reference Clock Input. The AutoSync feature is not supported on the ADC12D2000RF. The pin structures are still shown in the event that a design is supporting multiple pin compatible devices in the family that supports AutoSync, such as the ADC1xD1x00 and ADC12Dx00RF families. See Table 25 for recommendations about terminating unused pins. RCOut1+/RCOut2+/- Reference Clock Output 1 and 2. The AutoSync feature is not supported on the ADC12D2000RF. The pin structures are still shown in the event that a design is supporting multiple pin compatible devices in the family that supports AutoSync, such as the ADC1xD1x00 and ADC12Dx00RF families. See Table 25 for recommendations about terminating unused pins. 9 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Ball No. ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC TABLE 2. Control and Status Balls Ball No. Name Equivalent Circuit Description DES Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, the DES Mode of operation is selected, meaning that the VinI input is sampled by both channels in a time-interleaved manner. The VinQ input is ignored. When this input is set to logic-low, the device is in Non-DES Mode, i.e. the I- and Q-channels operate independently. In the Extended Control Mode (ECM), this input is ignored and DES Mode selection is controlled through the Control Register by the DES Bit (Addr: 0h, Bit 7); default is Non-DES Mode operation. CalDly Calibration Delay select. By setting this input logic-high or logic-low, the user can select the device to wait a longer or shorter amount of time, respectively, before the automatic power-on selfcalibration is initiated. This feature is pincontrolled only and is always active during ECM and Non-ECM. D6 CAL Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. If this input is held high at the time of power-on, the automatic power-on calibration cycle is inhibited until this input is cycled low-then-high. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration. B5 CalRun V5 V4 www.ti.com Calibration Running indication. This output is logic-high while the calibration sequence is executing. This output is logic-low otherwise. 10 U3 V3 A4 A5 Y3 W4 Name Equivalent Circuit Description PDI PDQ Power Down I- and Q-channel. Setting either input to logic-high powers down the respective Ior Q-channel. Setting either input to logic-low brings the respective I- or Q-channel to an operational state after a finite time delay. This pin is active in both ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to powerdown the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively. TPM Test Pattern Mode select. With this input at logichigh, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the Test Pattern Mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12). NDM Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and NonECM. FSR Full-Scale input Range select. In Non-ECM, this input must be set to logic-high; the full-scale differential input range for both I- and Q-channel inputs is set by this pin. In the ECM, this input is ignored and the full-scale range of the I- and Qchannel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the logic-high FSR value in NonECM corresponds to the minimum allowed selection in ECM. DDRPh DDR Phase select. This input, when logic-low, selects the 0° Data-to-DCLK phase relationship. When logic-high, it selects the 90° Data-to-DCLK phase relationship, i.e. the DCLK transition indicates the middle of the valid data outputs. This pin only has an effect when the chip is in 1:2 Demuxed Mode, i.e. the NDM pin is set to logiclow. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS Bit (Addr: 0h, Bit 14); the default is 0° Mode. 11 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Ball No. ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Ball No. Name Equivalent Circuit Description ECE Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted (logic-low). In this case, most of the direct control pins have no effect. When this signal is de-asserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled via the control pins. SCS Serial Chip Select bar. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data which is present on SDI and to source serial data on SDO. When this signal is deasserted (logic-high), SDI is ignored and SDO is in TRI-STATE. C5 SCLK Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logiclow, as long as timing specifications are not violated when the clock is enabled or disabled. B4 SDI Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). A3 SDO Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is at TRI-STATE when SCS is de-asserted. D1, D7, E3, F4, W3, U7 DNC NONE Do Not Connect. These pins are used for internal purposes and should not be connected, i.e. left floating. Do not ground. C7 NC NONE Not Connected. This pin is not bonded and may be left floating or connected to any potential. B3 C4 www.ti.com 12 Ball No. Name Equivalent Circuit A2, A6, B6, C6, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 VA NONE Power Supply for the Analog circuitry. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply. G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 VTC NONE Power Supply for the Track-and-Hold and Clock circuitry. A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 VDR NONE Power Supply for the Output Drivers. A8, B9, C8, V8, W9, Y8 VE NONE Power Supply for the Digital Encoder. NONE Bias Voltage I-channel. This is an externally decoupled bias voltage for the I-channel. Each pin should individually be decoupled with a 100 nF capacitor via a low resistance, low inductance path to GND. J4, K2 VbiasI Description L2, M4 VbiasQ NONE Bias Voltage Q-channel. This is an externally decoupled bias voltage for the Q-channel. Each pin should individually be decoupled with a 100 nF capacitor via a low resistance, low inductance path to GND. A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13 GND NONE Ground Return for the Analog circuitry. F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 GNDTC NONE Ground Return for the Track-and-Hold and Clock circuitry. A13, A17, A20, D13, D16, E17, F17, F20, M17, M20, U13, U17, V18, Y13, Y17, Y20 GNDDR NONE Ground Return for the Output Drivers. A9, B8, C9, V9, W8, Y9 GNDE NONE Ground Return for the Digital Encoder. 13 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC TABLE 3. Power and Ground Balls ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC TABLE 4. High-Speed Digital Outputs Ball No. K19/K20 L19/L20 K17/K18 L17/L18 www.ti.com Name Equivalent Circuit Description DCLKI+/DCLKQ+/- Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode or Non-Demux Mode, this signal is at ¼ or ½ the sampling clock rate, respectively. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. ORI+/ORQ+/- Out-of-Range Output for the I- and Q-channel. This differential output is asserted logic-high while the over- or under-range condition exists, i.e. the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current Data, with which it is clocked out. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. ORQ (Note 19). 14 Name Equivalent Circuit J18/J19 H19/H20 H17/H18 G19/G20 G17/G18 F18/F19 E19/E20 D19/D20 D18/E18 C19/C20 B19/B20 B18/C17 · M18/M19 N19/N20 N17/N18 P19/P20 P17/P18 R18/R19 T19/T20 U19/U20 U18/T18 V19/V20 W19/W20 W18/V17 DI11+/DI10+/DI9+/DI8+/DI7+/DI6+/DI5+/DI4+/DI3+/DI2+/DI1+/DI0+/· DQ11+/DQ10+/DQ9+/DQ8+/DQ7+/DQ6+/DQ5+/DQ4+/DQ3+/DQ2+/DQ1+/DQ0+/- I- and Q-channel Digital Data Outputs. In NonDemux Mode, this LVDS data is transmitted at the sampling clock rate. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, i.e. the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. A18/A19 B17/C16 A16/B16 B15/C15 C14/D14 A14/B14 B13/C13 C12/D12 A12/B12 B11/C11 C10/D10 A10/B10 · Y18/Y19 W17/V16 Y16/W16 W15/V15 V14/U14 Y14/W14 W13/V13 V12/U12 Y12/W12 W11/V11 V10/U10 Y10/W10 DId11+/DId10+/DId9+/DId8+/DId7+/DId6+/DId5+/DId4+/DId3+/DId2+/DId1+/DId0+/· DQd11+/DQd10+/DQd9+/DQd8+/DQd7+/DQd6+/DQd5+/DQd4+/DQd3+/DQd2+/DQd1+/DQd0+/- Delayed I- and Q-channel Digital Data Outputs. In Non-Demux Mode, these outputs are at TRISTATE. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non-delayed data, i.e. the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. 15 Description www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Ball No. ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC 10.0 Absolute Maximum Ratings 11.0 Operating Ratings (Note 1, Note 2) (Note 1, Note 2) Supply Voltage (VA, VTC, VDR, VE) Supply Difference max(VA/TC/DR/E)min(VA/TC/DR/E) Voltage on Any Input Pin (except VIN+/-) 0V to 100 mV −0.15V to (VA + 0.15V) VIN+/- Voltage Range -0.5V to 2.5V Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) Input Current at Any Pin (Note 3) ADC12D2000RF Package Power Dissipation at TA ≤ 45°C (Note 3) ESD Susceptibility (Note 4) Human Body Model Charged Device Model Machine Model Storage Temperature Ambient Temperature Range ADC12D2000RF (Standard −40°C ≤ TA ≤ +45°C JEDEC thermal model) ADC12D2000RF (Enhanced −40°C ≤ TA ≤ +85°C thermal model / heatsink) Junction Temperature Range applies only to maximum operating TJ ≤ +120°C speed Supply Voltage (VA, VTC, VE) +1.9V to +2.1V Driver Supply Voltage (VDR) +1.9V to VA 2.2V 0V to 100 mV ±50 mA VIN+/- Voltage Range (Note 14) VIN+/- Differential Voltage Range (Note 15) 5.34 W   2500V 1000V 250V −65°C to +150°C VIN+/- Current Range (Note 14) VIN+/- Power -0.4V to 2.4V (d.c.-coupled) 1.0V (d.c.-coupled @100% duty cycle) 2.0V (d.c.-coupled @20% duty cycle) 2.8V (d.c.-coupled @10% duty cycle) ±50 mA peak (a.c.-coupled) 15.3 dBm (maintaining common mode voltage, a.c.coupled) 17.1 dBm (not maintaining common mode voltage, a.c.coupled) Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) 0V 0V to VA CLK+/- Voltage Range Differential CLK Amplitude 0.4VP-P to 2.0VP-P Common Mode Input Voltage VCMO - 150mV < VCMI < VCMO +150mV TABLE 5. Package Thermal Resistance Package θJA 292-Ball BGA Thermally 16°C/W Enhanced Package θJC1 θJC2 2.9°C/W 2.5°C/W Soldering process must comply with Texas Instruments’ Reflow Temperature Profile specifications. Refer to www.national.com/packaging. www.ti.com 16 Unless otherwise specified, the following apply after calibration for VA = VDR = VTC = VE = +2.0V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; Differential, AC coupled Sine Wave Sampling Clock, fCLK = 2.0 GHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Extended Control Mode with Register 6h written to 1C0Eh; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX and for TJ < 120°C. All other limits TA = 25°C, unless otherwise noted. (Note 5, Note 6, Note 7) TABLE 6. Static Converter Characteristics Symbol Parameter Conditions ADC12D2000RF Typ Resolution with No Missing Codes Lim Units (Limits) 12 bits INL Integral Non-Linearity (Best fit) 1 MHz DC-coupled over-ranged sine wave ±2.5 LSB DNL Differential Non-Linearity 1 MHz DC-coupled over-ranged sine wave ±0.5 LSB VOFF Offset Error 5 LSB VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV PFSE Positive Full-Scale Error (Note 8) ±25 mV (max) NFSE Negative Full-Scale Error (Note 8) ±25 mV (max) Out-of-Range Output Code (Note (VIN+) − (VIN−) > + Full Scale 9) (VIN+) − (VIN−) < − Full Scale 4095 0 TABLE 7. Dynamic Converter Characteristics (Note 10) Symbol Parameter Bandwidth Conditions ADC12D2000RF Typ Lim Units (Limits) Non-DES Mode, DESCLKIQ Mode -3 dB (Note 17) 2.7 GHz -6 dB 3.1 GHz -9 dB 3.5 GHz -12 dB 4.0 GHz -3 dB (Note 17) 1.2 GHz -6 dB 2.3 GHz -9 dB 2.7 GHz -12 dB 3.0 GHz -3 dB (Note 17) 1.75 GHz -6 dB 2.7 GHz DESI Mode, DESQ Mode DESIQ Mode 17 www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC 12.0 Converter Electrical Characteristics ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Symbol Parameter Gain Flatness Conditions ADC12D2000RF Typ Lim Units (Limits) Non-DES Mode D.C. to Fs/2 ±0.4 dB D.C. to Fs ±1.1 dB D.C. to 3Fs/2 ±1.7 dB D.C. to 2Fs ±5.7 dB D.C. to Fs/2 ±2.7 dB D.C. to Fs ±9.2 dB ±1.6 dB ±1.2 dB 10-18 Error/ Sample FIN = 2670 MHz ± 2.5MHz @ -13 dBFS -73.6 dBFS -60.6 dBc FIN = 2070 MHz ± 2.5MHz @ -13 dBFS -76.1 dBFS -60.1 dBc FIN = 2670 MHz ± 2.5MHz @ -16 dBFS -80.7 dBFS -64.7 dBc FIN = 2070 MHz ± 2.5MHz @ -16 dBFS -70.9 dBFS -54.9 dBc 50Ω single-ended termination, DES Mode -154 dBm/Hz -153 dBFS/Hz DESI, DESQ Mode DESIQ Mode D.C. to Fs/2 DESCLKIQ Mode D.C. to Fs/2 CER Code Error Rate IMD3 3rd order Intermodulation Distortion Noise Floor Density www.ti.com DES Mode 18 Parameter Conditions ADC12D2000RF Typ Lim Units (Limits) Non-DES Mode (Note 11, Note 13, Note 20) ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free Dynamic Range AIN = 125 MHz @ -0.5 dBFS 8.9 AIN = 248 MHz @ -0.5 dBFS 8.9 AIN = 498 MHz @ -0.5 dBFS 8.7 AIN = 1147 MHz @ -0.5 dBFS 8.3 bits AIN = 1448 MHz @ -0.5 dBFS 8.1 bits AIN = 125 MHz @ -0.5 dBFS 55.1 dB AIN = 248 MHz @ -0.5 dBFS 55.1 dB AIN = 498 MHz @ -0.5 dBFS 54.4 AIN = 1147 MHz @ -0.5 dBFS 51.5 dB AIN = 1448 MHz @ -0.5 dBFS 50.3 dB AIN = 125 MHz @ -0.5 dBFS 55.6 dB AIN = 248 MHz @ -0.5 dBFS 55.6 AIN = 498 MHz @ -0.5 dBFS 54.8 AIN = 1147 MHz @ -0.5 dBFS 51.9 dB AIN = 1448 MHz @ -0.5 dBFS 50.6 dB AIN = 125 MHz @ -0.5 dBFS -64.4 dB AIN = 248 MHz @ -0.5 dBFS -65.2 dB AIN = 498 MHz @ -0.5 dBFS -65.2 AIN = 1147 MHz @ -0.5 dBFS -63.0 AIN = 1448 MHz @ -0.5 dBFS -63.4 dB AIN = 125 MHz @ -0.5 dBFS -79.8 dBc AIN = 248 MHz @ -0.5 dBFS -75.5 dBc AIN = 498 MHz @ -0.5 dBFS -69.5 dBc AIN = 1147 MHz @ -0.5 dBFS -67.5 dBc AIN = 1448 MHz @ -0.5 dBFS -71.8 dBc AIN = 125 MHz @ -0.5 dBFS -67.8 dBc AIN = 248 MHz @ -0.5 dBFS -68.3 dBc AIN = 498 MHz @ -0.5 dBFS -71.1 dBc AIN = 1147 MHz @ -0.5 dBFS -66.1 dBc AIN = 1448 MHz @ -0.5 dBFS -67.5 dBc AIN = 125 MHz @ -0.5 dBFS 66.4 dBc AIN = 248 MHz @ -0.5 dBFS 67.8 AIN = 498 MHz @ -0.5 dBFS 64.6 AIN = 1147 MHz @ -0.5 dBFS 57.3 dBc AIN = 1448 MHz @ -0.5 dBFS 55.9 dBc 19 bits bits 8.0 49.7 bits (min) dB (min) dB 50.1 -60 dB (min) dB (max) dB dBc 50.4 dBc (min) www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Symbol ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC Symbol Parameter Conditions ADC12D2000RF Typ Lim Units (Limits) DES Mode (Note 11, Note 12, Note 13, Note 20) ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR www.ti.com Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free Dynamic Range AIN = 125 MHz @ -0.5 dBFS 8.9 bits AIN = 248 MHz @ -0.5 dBFS 8.9 bits AIN = 498 MHz @ -0.5 dBFS 8.6 bits AIN = 1147 MHz @ -0.5 dBFS 8.3 bits AIN = 1448 MHz @ -0.5 dBFS 8.1 bits AIN = 125 MHz @ -0.5 dBFS 55.1 dB AIN = 248 MHz @ -0.5 dBFS 55.1 dB AIN = 498 MHz @ -0.5 dBFS 53.7 dB AIN = 1147 MHz @ -0.5 dBFS 51.5 dB AIN = 1448 MHz @ -0.5 dBFS 50.2 dB AIN = 125 MHz @ -0.5 dBFS 55.6 dB AIN = 248 MHz @ -0.5 dBFS 55.6 dB AIN = 498 MHz @ -0.5 dBFS 54.1 dB AIN = 1147 MHz @ -0.5 dBFS 51.8 dB AIN = 1448 MHz @ -0.5 dBFS 50.6 dB AIN = 125 MHz @ -0.5 dBFS -63.5 dB AIN = 248 MHz @ -0.5 dBFS -64.6 dB AIN = 498 MHz @ -0.5 dBFS -64.2 dB AIN = 1147 MHz @ -0.5 dBFS -65.6 dB AIN = 1448 MHz @ -0.5 dBFS -60.7 dB AIN = 125 MHz @ -0.5 dBFS -75.5 dBc AIN = 248 MHz @ -0.5 dBFS -76.7 dBc AIN = 498 MHz @ -0.5 dBFS -79.5 dBc AIN = 1147 MHz @ -0.5 dBFS -79.5 dBc AIN = 1448 MHz @ -0.5 dBFS -64.9 dBc AIN = 125 MHz @ -0.5 dBFS -65.5 dBc AIN = 248 MHz @ -0.5 dBFS -65.4 dBc AIN = 498 MHz @ -0.5 dBFS -67.3 dBc AIN = 1147 MHz @ -0.5 dBFS -67.1 dBc AIN = 1448 MHz @ -0.5 dBFS -65.1 dBc AIN = 125 MHz @ -0.5 dBFS 65.0 dBc AIN = 248 MHz @ -0.5 dBFS 64.9 dBc AIN = 498 MHz @ -0.5 dBFS 64.2 dBc AIN = 1147 MHz @ -0.5 dBFS 61.9 dBc AIN = 1448 MHz @ -0.5 dBFS 62.3 dBc 20 Symbol Parameter Conditions ADC12D2000RF Typ Lim Units (Limits) Analog Inputs VIN_FSR Analog Differential Input Full Scale Non-Extended Control Mode Range FSR Pin High 740 mVP-P (min) 860 mVP-P (max) 800 Extended Control Mode CIN RIN FM(14:0) = 4000h (default) 800 mVP-P FM(14:0) = 7FFFh 1000 mVP-P Analog Input Capacitance, Differential Non-DES Mode (Note 9, Note 16) Each input pin to ground 0.02 pF 1.6 pF Analog Input Capacitance, DES Mode (Note 9, Note 16) Differential 0.08 pF Each input pin to ground 2.2 pF Differential Input Resistance 100 91 Ω (min) 109 Ω (max) Common Mode Output VCMO Common Mode Output Voltage ICMO = ±100 µA TC_VCMO Common Mode Output Voltage Temperature Coefficient ICMO = ±100 µA (Note 10) VCMO_LVL VCMO input threshold to set DC-coupling Mode (Note 10) CL_VCMO Maximum VCMO Load Capacitance (Note 9) 1.25 1.15 V (min) 1.35 V (max) 38 ppm/°C 0.63 V 80 pF Bandgap Reference VBG Bandgap Reference Output Voltage IBG = ±100 µA TC_VBG Bandgap Reference Voltage Temperature Coefficient IBG = ±100 µA (Note 10) CL_VBG Maximum Bandgap Reference load Capacitance (Note 9) 1.25 1.15 V (min) 1.35 V (max) 32 ppm/°C 80 21 pF www.ti.com ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC TABLE 8. Analog Input / Output and Reference Characteristics ADC12D2000RF 12-Bit 4.0 GSPS RF Sampling ADC TABLE 9. I-Channel to Q-Channel Characteristics Symbol X-TALK Parameter Conditions ADC12D2000RF Typ Lim Units (Limits) Offset Match (Note 10) 2 LSB Positive Full-Scale Match Zero offset selected in Control Register 2 LSB Negative Full-Scale Match Zero offset selected in Control Register 2 LSB Phase Matching (I, Q) fIN = 1.0 GHz (Note 10)
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