ADC12DC105LFEB/NOPB

User's Guide SNAU096A – July 2011 – Revised October 2013 ADC14DC105EB and ADC12DC105EB Evaluation Boards This User's guide applies to the ADC14DC105EB and ADC12DC105EB evaluation boards which are used to evaluate the ADC14DC105 and ADC12DC105 A/D Converters, respectively. These ADCs belong to a family of 12 and 14 bit converters that provide data at rates of up to 105MHz. Further reference in this manual to the ADC14DC105 is meant to also include the other listed parts unless otherwise specified. The evaluation board is designed to be used with the WaveVision5™ Data Capture Board which is connected to a personal computer through a USB port and running WaveVision5™ software, operating under Microsoft Windows. The software can perform an FFT on the captured data upon command and, in addition to a frequency domain plot, shows dynamic performance in the form of SNR, SINAD, THD SFDR and ENOB. The latest WaveVision 5 data capture board and WaveVision 5 Software is available through the Texas Instruments website. Contents Board Assembly ............................................................................................................. 1 Quick Start ................................................................................................................... 3 Functional Description ...................................................................................................... 3 3.1 Analog Input ........................................................................................................ 3 3.2 ADC Reference Circuitry .......................................................................................... 4 3.3 ADC Clock Circuit .................................................................................................. 4 3.4 Digital Data Output ................................................................................................. 4 3.5 Data Format/Duty Cycle Stabilizer ............................................................................... 4 3.6 Power Supply Connections ....................................................................................... 4 4 Installing the ADC14DC105 Evaluation Board .......................................................................... 5 5 Evaluation Board Layout ................................................................................................... 6 6 Hardware Schematic ...................................................................................................... 10 7 Evaluation Board Bill of Materials ....................................................................................... 13 Appendix A ....................................................................................................................... 15 1 2 3 List of Figures 8 ............................................................................... Test Set Up .................................................................................................................. Analog Input Network for FIN > 70MHz ................................................................................... Analog Input Network for FIN < 70MHz ................................................................................... Layer 1: Component Side .................................................................................................. Layer 2: Ground ............................................................................................................. Layer 3: Power .............................................................................................................. Layer 4: Circuit Side ........................................................................................................ 1 ADC12DC105/ADC14DC105 Evaluation Board BOM (rev 6) ....................................................... 1 2 3 4 5 6 7 Major Component and Jumper Locations 2 2 3 4 6 7 8 9 List of Tables 1 13 Board Assembly The ADC14DC105 Evaluation Board comes pre-assembled. Refer to the Bill of Materials in Section 7 for a description of components, to Figure 1 for major component placement and to Section 5 for the Evaluation Board schematic. SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 1 Board Assembly www.ti.com U3 ADC14DC105 JP14 PD_A J8 WV4 Conn. Input Signal Ch. A Input Signal Ch. B JP17 OF/DCS GND +5V JP16 PD_B J1 Ext.CLK JR1 POWER Figure 1. Major Component and Jumper Locations To PC EVALUATION BOARD USB Ch.A Input FutureBus Connector ADC14DC105 al Sign . Cond FutureBus Connector Sign al Cond . WaveVision5 Board Ch.B Input Ext. Clock Input JR1 GND 12V +5V Filter Power Supply Filter WaveVision 5 Power Supply Signal Generator +12V Signal Generator Figure 2. Test Set Up 2 ADC14DC105EB and ADC12DC105EB Evaluation Boards SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Quick Start www.ti.com 2 Quick Start Refer to Figure 1 for locations of jumpers, test points and major components. Refer to Figure 2 for the test set up. The board is configured by default to use a crystal clock source and internal reference. Refer to Section 3.0 and Appendix A for more information on jumper settings. The input network of this board is configured for input frequencies greater than 70MHz. Refer to the Analog Input section for more information about input networks. You must have version the WaveVision5™ data capture board and WaveVision 5 software to properly test this board. You can download the latest version from: http://www.ti.com/tool/wavevision5 http://www.ti.com/tool/wavevsn-brd-5.1 1. Apply power to the WaveVision5™ board and connect it to the computer using a USB cable. See the WaveVision5™ Board Manual for operation of that board. Connect the evaluation board to the WaveVision5™ Data Capture Board. NOTE: power to the WaveVision5 Data Capture Board should be applied before the power to the Evaluation Board to insure that the FPGA on the WaveVison5 Data Capture Board is not damaged. 2. Connect a clean +5V power supply to pin 2 of Power Connector JR1. Pin 1 is ground. 3. Connect a signal from a 50-Ω source to connector J9. Be sure to use a bandpass filter before the Evaluation Board to filter out noise and distortion from the clock signal generator. 4. Connect a signal from a 50-Ω source to connector J1. Set the amplitude to +14dBm and the frequency to the desired sampling rate. This signal power must result in >2Vpp signal at the SMA input to the EVM. Be sure to use a bandpass filter before the Evaluation Board to filter out noise and distortion from the clock signal generator. See Section 3.3 for more information on signal filtering and appropriate signal generators. 5. Adjust the input signal amplitude as needed to ensure that the signal does not over-range by examining a histogram of the output data with the WaveVision™ software. 3 Functional Description The Evaluation Board schematic is shown in the Hardware Schematic Section. A list of test points and jumper settings can be found in Appendix A. 3.1 Analog Input To obtain the best distortion results the analog input network must be optimized for the signal frequency being applied. The Evaluation Board comes configured for input frequencies greater than 70MHz as seen in Figure 3. The input network is intended to accept a low-noise sine wave signal of up to 2V peak-to-peak amplitude. To accurately evaluate the dynamic performance of this converter, the input test signal will have to be passed through a high-quality bandpass filter. For input frequencies below 70MHz the circuit of Figure 3 may be used. VIN 0.1uF MABACT0039 0.1uF 25Ω 10pF 0.1uF 0.1uF ADC Input 25Ω MABACT0039 0.1uF VCMO Figure 3. Analog Input Network for FIN > 70MHz For input frequencies below 70MHz the circuit of Figure 4 may be used. SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 3 Functional Description www.ti.com VIN 20Ω 0.1 µF ADT1-1WT 18 pF 50Ω ADC Input 0.1 µF 0.1 µF 20Ω VCMO Figure 4. Analog Input Network for FIN < 70MHz 3.2 ADC Reference Circuitry The ADC14C105 can use an internal or external 1.2V reference. This Evaluation Board is configured to use the internal reference. 3.3 ADC Clock Circuit Solder jumpers are used to select the path of the clock to the ADC. While not as convenient as pin-type jumpers, these introduce less noise into the clock signal. By default, the board requires an external signal generator to provide a low noise clock at connector J1. The clock signal must be filtered by a bandpass filter to remove noise and distortion. On the board, the signal is buffered by U11 (NC7WV125) and applied to the ADC’s clock input pin. This EVM requires a 2.0-3.3 Vpp signal swing at the clock SMA which translates to +10-14.4dBm signal power into the J1 (50-Ω) input. The chosen bandpass filter in the clock path attenuates the signal power from the signal generator, so the generator power must set to overcome the attenuation. Different filters have different attenuations (insertion losses). Setting +17dBm assumes a 4dB insertion loss and +13dBm at the SMA input. The recommendation of +14dBm assumes a filter attenuation of less than 4dB. As an option, a Pletronics SM7745 or Vectron VCC1 type device crystal clock may be placed on the board. For this option open the pins of solder jumper JP4 and short the pins of JP10 and place component L5. 3.4 Digital Data Output The digital output data for Channel A is available at pins B4 (MSB) through B17 of the WaveVision™ connector J8. The digital output data for Channel B is available at pins A4 (MSB) through A17 of the WaveVision™ connector J8. 3.5 Data Format/Duty Cycle Stabilizer Output data format and the duty cycle stabilizer (DCS) are controlled by jumper JP17. Shorting pins 1-2 of JP17 sets the output format to 2’s complement with DCS Off. Shorting pins 3-4 of JP17sets the output format to 2’s complement with DCS On. Shorting pins 5-6 of JP17 sets the output format to offset binary with DCS On. Shorting pins 7-8 of JP17 sets the output format to offset binary with DCS Off. This is the default setting. 3.6 Power Supply Connections Power to this board is supplied through power connector JR1. The only supply needed is +5V at pin 2 plus ground at pin 1. Voltage and current requirements for the ADC14DC105 Evaluation Board are: • +5.0V at 500 mA 4 ADC14DC105EB and ADC12DC105EB Evaluation Boards SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Installing the ADC14DC105 Evaluation Board www.ti.com 4 Installing the ADC14DC105 Evaluation Board The evaluation board requires a single power supply as described in Power Supply Connections. NOTE: power to the WaveVision4 Data Capture Board should be applied before the power to the ADC14DC105 Evaluation Board to insure that the FPGA on the WaveVison5 Data Capture Board is not damaged. An appropriate signal source should be connected to the Signal Input SMA connector J9 (Channel A) or J5 (Channel B). When evaluating dynamic performance, an appropriate signal generator (such as the HP8644B or the R&S SME-03) with 50 Ohm source impedance should be connected to the Analog Input connector through an appropriate bandpass filter as even the best signal generator available can not produce a signal pure enough to evaluate the dynamic performance of an ADC. An low noise signal generator should also be connected to the clock input J1 through a bandpass filter. If this board is used in conjunction with the the WaveVision5™ Data Capture Board and WaveVision5™ software, a USB cable must be connected between the Data Capture Board and the host. See the WaveVision5™ Data Capture Board manual for details. SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 5 Evaluation Board Layout 5 www.ti.com Evaluation Board Layout Figure 5. Layer 1: Component Side 6 ADC14DC105EB and ADC12DC105EB Evaluation Boards SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Evaluation Board Layout www.ti.com Figure 6. Layer 2: Ground SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 7 Evaluation Board Layout www.ti.com Figure 7. Layer 3: Power 8 ADC14DC105EB and ADC12DC105EB Evaluation Boards SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Evaluation Board Layout www.ti.com Figure 8. Layer 4: Circuit Side SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 9 Hardware Schematic 6 www.ti.com Hardware Schematic VA2 VA2 R3 1k U11 R5 1k 2 3 4 5 R8 JP4 jumper/sm SHORTED 5 7 49.9 OE1 VCC A1 Y1 A2 Y2 OE2 GND R7 22.1 6 CLK JP3 jumper/sm SHORTED 3 4 TP1 GND DNI TP2 GND DNI TP3 GND DNI TP4 GND DNI 1 2 .1uF 1 C2 1 8 1 1 1 J1 External Clock NC7WV125 VA JP14 VCLK DNI PD R17 40.2k C5 DNI .1uF 4 VA R14 VD 22.1 3 R125 C7 22.1 CLK C102 .1uF 1uF DNI JP12 jumper/sm OPEN VD U3 VA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input C8 .1uF Vin_AVin_A+ Vreft_A C12 1uF C10 .1uF Vreft_A Vrefb_A VCOM_A VCOM_B Vrefb_B Vreft_B Vrefb_A Vin_B+ Vin_B- C9 .1uF C11 .1uF Analog Input AGND VinAVinA+ AGND Vreft_A Vrefb_A Vcom_A VA Vcom_B Vrefb_B Vreft_B AGND VinB+ VinBAGND Vrefb_B C14 .1uF C23 .1uF VA C33 .1uF DA[0..13] 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 DA5 DA4 DA3 DA2 DA1 DA0 DRDY VDR ADC12DC105/ADC14DC105 DRGND DB13 DB12 DB11 DB10 DB9 DB8 Output DA5 DA4 DA3 DA2 DA1 DA0 DA[0..13] C DRDY DB13 DB12 DB11 DB10 DB9 DB8 DB[0..13] Output Measurement DB[0..13] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C13 1uF DA9 DA8 DA7 DA6 Oscillator/4smd DA13 DA12 DA11 DA10 GND OUT 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 2 VA Vref VA PD_A N/C DA13 DA12 DA11 DA10 DRGND VDR DA9 DA8 DA7 DA6 NC VDD VA VA CLK OF/DCC PD_B DB0 DB1 DB2 DB3 DRGND VDR DB4 DB5 DB6 DB7 Y1 1 PD_A 1 2 JP10 jumper/sm OPEN L5 D DB0 DB1 DB2 DB3 JP16 2 1 CLK DB4 DB5 DB6 DB7 Vreft_B C15 .1uF VA PD +5V VD PD_B U7 +2.5V +5V 410 Ohm @ 100MHz L1 JR1 +5V PWR GND VD C40 4.7uF VA 4 2 R127 51k R19 2 1 40.2k 1 C19 C20 22uF 10uF + + C16 10uF C21 .1uF + C17 10uF + C18 22uF 8 R20 1K + 2 4 6 8 C22 .1uF IN NC1 OUT NC2 BYPASS SHDN ADJ GND PWRPAD 5 7 6 3 9 R128 1.5k C41 10uF C111 1800pF C42 0.01uF C43 .1uF C39 0.01uF C44 .1uF C45 0.01uF C46 .1uF LP3878-ADJ 1 3 5 7 C57 0.01uF R21 1K JP17 OF/DCC SHUNT 7-8 R22 1K R126 1k B +5V VA2 VCLK L3 U13 50 Ohm @ 100MHz L4 C110 4.7uF 4 2 R129 51k 1 8 VA +5V C100 4.7uF U12 4 2 R133 51k 1 8 50 Ohm @ 100MHz L2 IN NC1 BYPASS SHDN OUT NC2 ADJ GND PWRPAD +3.3V BYPASS SHDN C115 0.01uF R120 2.32K C120 1200pF C101 10uF OUT NC2 ADJ GND PWRPAD 5 7 50 Ohm @ 100MHz 6 3 9 R124 2.32K C112 1200pF + C35 22uF C59 10uF C36 .1uF C37 0.01uF LP3878-ADJ ANALOG BYPASSING 5 7 6 3 9 IN NC1 R123 1k + C24 22uF C25 .1uF C26 0.01uF C27 0.01uF C28 .1uF C29 0.01uF C30 .1uF C31 0.01uF C32 .1uF C103 0.01uF C104 .1uF LP3878-ADJ C118 0.01uF R121 1k LATCH BYPASSING VD2 +3.3V +5V C47 4.7uF U6 R130 51k 4 2 1 8 C58 0.01uF IN NC1 BYPASS SHDN OUT NC2 ADJ GND PWRPAD LP3878-ADJ R131 2.32K 5 7 C85 0.01uF C86 .1uF C87 .1uF C88 0.01uF C89 0.01uF C90 .1uF C91 .1uF C84 0.01uF C49 0.01uF C50 .1uF C51 .1uF C52 0.01uF C53 0.01uF C54 .1uF C55 .1uF C56 0.01uF C48 10uF C116 1200pF 6 3 9 A R132 1k Title Size C Date: 5 10 4 3 ADC14DC105EB and ADC12DC105EB Evaluation Boards 2 ADC14DC105 Evaluation Board Document Number Rev 870012786-500A Wednesday, August 07, 2013 Sheet 1 6 of 3 1 SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Hardware Schematic www.ti.com 5 4 3 2 1 D D Vin_AR26 0 ADT1-1WT+ T1 1 6 2 3 4 5 R117 49.9 DNI 2 5 3 4 10pF R27 24.9 C65 DNI R29 24.9 C96 .1uF 1 Vin_A- C68 R30 0 C66 .1uF C105 100pF C67 10pF C106 .1uF Vin_A+ INPUT J9 Vin_A+ C69 10pF C C R28 49.9 VCOM_A VCOM_A Vin_B+ J5 INPUT B C75 .1uF 2 3 4 5 1 R119 49.9 DNI R35 0 ADT1-1WT+ T2 1 6 2 5 3 4 B 10pF C77 DNI R37 24.9 R38 0 Vin_B+ C70 R34 24.9 C107 100pF C79 10pF C108 .1uF C78 .1uF Vin_B- Vin_B- C71 10pF R32 49.9 VCOM_B A VCOM_B A Title Size B Date: 5 4 3 SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback 2 ADC14DC105 Evaluation Board Document Number Rev 870012786-500A Wednesday, August 07, 2013 Sheet 2 6 of 3 1 ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 11 Hardware Schematic www.ti.com 5 4 3 2 1 R71 22.1 DRDY VD2 D D 22 22 22 22 22 22 22 DAR13 DAR12 DAR11 DAR10 DAR9 DAR8 DAR7 RP2 1 2 3 4 5 6 7 8 DA6 DA5 DA4 DA3 DA2 DA1 DA0 16 15 14 13 12 11 10 9 DAR13 DAR12 DAR11 DAR10 DAR9 DAR8 DAR7 DAR6 DAR5 DAR4 DAR3 DAR2 DAR1 DAR0 DAR6 DAR5 DAR4 DAR3 DAR2 DAR1 DAR0 4A4 4A3 4A2 4A1 3A4 3A3 3A2 3A1 2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1 1 48 25 24 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 1OE 2OE 3OE 4OE 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 22.1 BUF_CLK R41 R47 R46 R42 R48 R49 R43 R50 R44 R52 R51 R53 R55 R54 22 22 22 22 22 22 22 22 22 22 22 22 22 22 DAB13 DAB12 DAB11 DAB10 DAB9 DAB8 DAB7 DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 DAB[0..13] 4 10 15 21 28 34 39 45 22 R45 GND GND GND GND GND GND GND GND R75 R77 R76 R79 R78 R81 R80 DAR[0..13] DA[0:13] DA13 DA12 DA11 DA10 DA9 DA8 DA7 VCC VCC VCC VCC 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 DA[0..13] 7 18 31 42 U8 SN74LVTH162244 VD2 C R100 R99 R102 R101 R103 R105 R104 22 22 22 22 22 22 22 DBR13 DBR12 DBR11 DBR10 DBR9 DBR8 DBR7 22 DBR6 DBR5 DBR4 DBR3 DBR2 DBR1 DBR0 DBR13 DBR12 DBR11 DBR10 DBR9 DBR8 DBR7 DBR6 DBR5 DBR4 DBR3 DBR2 DBR1 DBR0 1 48 25 24 4A4 4A3 4A2 4A1 3A4 3A3 3A2 3A1 2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 1OE 2OE 3OE 4OE 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 R57 R58 R59 R65 R60 R61 R63 R62 R64 R67 R66 R69 R68 R70 22 22 22 22 22 22 22 22 22 22 22 22 22 22 DBB13 DBB12 DBB11 DBB10 DBB9 DBB8 DBB7 DBB6 DBB5 DBB4 DBB3 DBB2 DBB1 DBB0 DBB[0..13] 4 10 15 21 28 34 39 45 DB6 DB5 DB4 DB3 DB2 DB1 DB0 16 15 14 13 12 11 10 9 DBR[0..13] DB[0:13] 1 2 3 4 5 6 7 8 VCC VCC VCC VCC 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 RP3 DB13 DB12 DB11 DB10 DB9 DB8 DB7 GND GND GND GND GND GND GND GND DB[0..13] C 7 18 31 42 U9 SN74LVTH162244 DAB13 DBB13 8 BUF_CLK 6 5 C83 VCC A0 A1 A2 .1uF WP SCL SDA D24 C24 B24 A24 D23 C23 B23 A23 D22 C22 B22 A22 D21 C21 B21 A21 D20 C20 B20 A20 D19 C19 B19 A19 D18 C18 B18 A18 D17 C17 B17 A17 D16 C16 B16 A16 D15 C15 B15 A15 D14 C14 B14 A14 D13 C13 B13 A13 D12 C12 B12 A12 D11 C11 B11 A11 D10 C10 B10 A10 D9 C9 B9 A9 D8 C8 B8 A8 D7 C7 B7 A7 D6 C6 B6 A6 D5 C5 B5 A5 D4 C4 B4 A4 D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D24 C24 B24 A24 D23 C23 B23 A23 D22 C22 B22 A22 D21 C21 B21 A21 D20 C20 B20 A20 D19 C19 B19 A19 D18 C18 B18 A18 D17 C17 B17 A17 D16 C16 B16 A16 D15 C15 B15 A15 D14 C14 B14 A14 D13 C13 B13 A13 D12 C12 B12 A12 D11 C11 B11 A11 D10 C10 B10 A10 D9 C9 B9 A9 D8 C8 B8 A8 D7 C7 B7 A7 D6 C6 B6 A6 D5 C5 B5 A5 D4 C4 B4 A4 D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 EEPROM 2KBIT 400KHZ M24C02-RMN6TP U10 7 GND 1 2 3 4 DAB11 DAB12 DBB12 DBB11 DAB9 DAB8 DAB7 DAB6 DAB10 DBB10 DBB9 DBB8 DBB7 DBB6 DAB5 DBB5 DAB3 DAB4 DBB4 DBB3 DAB2 DBB2 DBB1 DBB0 DAB1 B DAB0 B J8 FUTUREBUS_96 A A Title Size C Date: 5 12 4 3 ADC14DC105EB and ADC12DC105EB Evaluation Boards 2 ADC14DC105 Evaluation Board Document Number Rev 870012786-500A Wednesday, August 07, 2013 Sheet 3 6 of 3 1 SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Evaluation Board Bill of Materials www.ti.com 7 Evaluation Board Bill of Materials Table 1. ADC12DC105/ADC14DC105 Evaluation Board BOM (rev 6) Item QTY Part Part Number Manufacturer Foot Print 1 2 Reference C2, C5 Note 0.1uF C1608X7R1E104K080AA TDK c0603 2 1 C7 1uF C1608X5R1C105K080AA TDK c0603 10% 3 9 C8, C9, C11, C15, C23, C33, C66, C78, C102 0.1uF C1005X5R1A104K050BA TDK c0402_no_ss 10% 4 2 C10, C14 0.1uF C0603X5R0J104K030BC TDK c0201_no_ss 10% 5 2 C12, C13 1uF GRM155R60J105ME19D Murata c0402_no_ss 20% 6 2 C16, C17 10uF T491A106K006AT Kemet ct3216 10% 7 1 C18 22uF T491A226M010AT Kemet ct3216 20% 8 3 C19, C24, C35 22uF T491B226M016AT Kemet c3528 20% 9 1 C20 10uF T491T106K016AT Kemet c3528 10% 10 2 C21, C83 0.1uF C2012X7R1H104K085AA TDK c0805 10% 11 14 C22, C36, C50, C51, C54, C55, C75, C86, C87, C90, C91, C96, C106, C108 0.1uF C1608X7R1E104K080AA TDK c0603 10% 12 8 C25, C28, C30, C32, C43, C44, C46, C104 0.1uF 05083C104MAT2A AVX c0508_no_ss 20% 13 8 C26, C27, C29, C31, C39, C42, C45, C103 0.01uF C1005X7R1V103K050BB TDK c0402_no_ss 10% 14 13 C37, C49, C53, C56, C58, C84, C88, C89, C118 0.01uF C1608X7R1H103K080AA TDK c0603 10% 15 4 C40, C47, C100, C110 4.7uF CL21B475KPFNNNE Samsung c0805 10% 16 4 C41, C48, C59, C101 10uF CL21B106KOQNNNE Samsung c0805 10% 17 0 C65, C77 18 6 C67, C68, C69, C70, C71, C79 10pF C0603C0G1E100D030BA TDK c0201_no_ss 0.5pF 19 2 C105, C107 100pF C1608C0G2E101J080AA TDK c0603 5% 20 1 C111 1800pF GRM188R71H182KA01D Murata c0603 10% 21 3 C112, C116, C120 1200pF GRM188R71H122KA01D Murata c0603 10% 22 2 JP3, JP4 SHORTED with solder jumper/sm SMD PADS 22a 2 JP10, JP12 OPEN 23 1 JP14 PD_A PRPC001DAAN-RC Sullins blkcon_2x1 24 1 JP16 PD_B PRPC001DAAN-RC Sullins blkcon_2x1 25 1 JP17 OF/DCC PRPC004DAAN-RC Sullins blkcon_4x2 26 1 JR1 +5V 1755736 Phoenix Contact MSTBVA_p200 27 1 J1 External Clock 901-144-8RFX Amphenol-RF Division sma_v_clr 28 2 J5, J9 INPUT 142-0701-801 Emerson sma_v_clr 29 1 J8 FUTUREBUS_96 223514-1 30 1 L1 410 Ω @ 100MHz FB20020-4B-RC Bourns ferrite_choke 31 3 L2, L3, L4 50 Ω @ 100MHz BLM31PG500SN1L Murata l1206 32 0 L5 50 Ω @ 100MHz BLM31PG500SN1L Murata l1206 33 2 RP2, RP3 22 742C163220JP CTS soic16_p50m_wg63_l252 5% 34 9 R3, R5, R20, R21, R22, R121, R123, R126, R132 1k ERJ-3EKF1001V Panasonic r0603 1% 35 4 R7, R14, R45, R71 22.1 ERJ-3EKF22R1V Panasonic r0603 1% 36 3 R8, R28, R32 49.9 ERJ-3EKF49R9V Panasonic r0603 1% 37 2 R17, R19 40.2k ERJ-3EKF4022V Panasonic r0603 1% 38 4 R26, R30, R35, R38 0 RC0402JR-070RL Yageo r0402_no_ss 5% 39 4 R27, R29, R34, R37 24.9 ERJ-3EKF24R9V Panasonic r0402_no_ss 1% C52, C57, C85, C115, DNI SHUNT 7-8 (ITEM 54) supplied by TI DNI CAPACITOR NON-POL SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Tol c0402_no_ss sm_jumper fbus_rs_96_ecl ADC14DC105EB and ADC12DC105EB Evaluation Boards Copyright © 2011–2013, Texas Instruments Incorporated 13 Evaluation Board Bill of Materials www.ti.com Table 1. ADC12DC105/ADC14DC105 Evaluation Board BOM (rev 6) (continued) Item QTY 40 42 R41, R42, R43, R44, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R75, R76, R77, R78, R79, R80, R81, R99, R100, R101, R102, R103, R104, R105 41 0 R117, R119 42 3 R120, R124, R131 43 0 R125 44 4 R127, R129, R130, R133 45 1 R128 46 0 TP1, TP2, TP3, TP4 47 2 T1, T2 ADT1-1WT+ ADT1-1WT+ Mini Circuits soic6_100_wg280_l310 48 1 U3 ADC12DC105 or ADC14DC105 ADC12DC105CISQ/NOPB or ADC14DC105CISQ/NOPB Texas Instruments LLP60_P5M_9X9_EP 49 4 U6, U7, U12, U13 LP3878-ADJ LP3878SD-ADJ/NOPB Texas Instruments SON_NGT_8 50 2 U8, U9 SN74LVTH162244 SN74LVTH162244DLR Texas Instruments SSOP48_P025_WG420_L6 50 51 1 U10 EEPROM 2KBIT 400kHz M24C02-RMN6TP STMicroelectronics soic8_050_wg244_l200 52 1 U11 NC7WV125 NC7WV125K8X Fairchild Semi. soic8_50m_wg3p10_l2p0 53 0 Y1 54 1 SHN1 SHUNT, HEADER MJ-5.97-G or equivalent Keltron 55 4 BMP1, BMP2, BMP3, BMP4 BUMPON HEMISPHERE 0.44 x 0.20 BLACK SJ-5003 3M 14 Reference Note DNI DNI DNI DNI Legs for PCB Part Part Number Manufacturer Foot Print Tol 22 ERJ-2RKF22R0X Panasonic r0402_no_ss 1% 49.9 ERJ-3EKF49R9V Panasonic r0603 1% 2.32K ERJ-3EKF2321V Panasonic r0603 1% 22.1 ERJ-3EKF22R1V Panasonic r0603 1% 51k ERJ-3EKF5102V Panasonic r0603 1% 1.5k ERJ-3EKF1501V Panasonic r0603 1% GND tp40 Oscillator/4smd ADC14DC105EB and ADC12DC105EB Evaluation Boards SM_xtl_5X7 SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated www.ti.com Appendix A A.1 Operating in the Computer Mode The ADC14C105 Evaluation Board is compatible with the WaveVision5™ Data Capture Board and WaveVision5™ software. When connected to the WaveVision5™ Board, data capture is easily controlled from a personal computer operating in the Windows environment. The data samples that are captured can be observed on the PC video monitor in the time and frequency domains. The FFT analysis of the captured data yields insight into system noise and distortion sources and estimates of ADC dynamic performance such as SINAD, SNR, THD, SFDR and ENOB. A.2 Summary Tables of Test Points, Connectors, and Jumper Settings A.2.1 Test Points Test Points on the ADC14DC105 Evaluation Board TP1-4 Ground A.2.2 Connectors JR1 Connector - Power Supply Connections JR1-2 +5V +5V Power Supply JR1-1 GND Power Supply Ground A.2.3 Jumper Settings Note: Default settings are in bold JP14 : Power Down Channel A Connect 1-2 ADC Channel A is powered down 1-2 OPEN ADC Channel A is operating JP16 : Power Down Channel B Connect 1-2 ADC Channel A is powered down 1-2 OPEN ADC Channel A is operating JP17 : Data Format / Duty Cycle Stabilizer Connect 1-2 Select Output format of 2’s complement, Duty Cycle Stabilizer is OFF Connect 3-4 Select Output format of 2’s complement, Duty Cycle Stabilizer is ON Connect 5-6 Select Output format of Offset Binary, Duty Cycle Stabilizer is ON Connect 7-8 Select Output format of Offset Binary, Duty Cycle Stabilizer is OFF A.2.4 Solder Jumper Settings The default clock configuration is to use an external signal generator to supply the clock signal via the J1 CLOCK_IN SMA connector. For this configuration, JP4 and JP3 must be shorted while JP10 is open. Alternatively, a crystal clock source can be populated at Y1. For this crystal configuration, solder jumpers JP3 and JP10 must be shorted while JP4 is open. SNAU096A – July 2011 – Revised October 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated 15 EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or contact TI. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. REGULATORY COMPLIANCE INFORMATION As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal Communications Commission (FCC) and Industry Canada (IC) rules. For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. General Statement for EVMs including a radio User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization. For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant Caution This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. For EVMs annotated as IC – INDUSTRY CANADA Compliant This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Concerning EVMs including radio transmitters This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs including detachable antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. Concernant les EVMs avec appareils radio Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER 【Important Notice for Users of EVMs for RF Products in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 　　　上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・インスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル http://www.tij.co.jp SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product. Your Sole Responsibility and Risk. You acknowledge, represent and agree that: 1. 2. 3. 4. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates, contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. Since the EVM is not a completed product, it may not meet all applicable regulatory and safety compliance standards (such as UL, CSA, VDE, CE, RoHS and WEEE) which may normally be associated with similar items. You assume full responsibility to determine and/or assure compliance with any such standards and related certifications as may be applicable. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even if the EVM should fail to perform as described or expected. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials. Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in development environments should use these EVMs. Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected. Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated