ADC34J22IRGZR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface 1 Features 3 Description • • • • • The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analogto-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phaselocked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps. 1 • • • • • • • Quad Channel 12-Bit Resolution Single 1.8-V Supply Flexible Input Clock Buffer with Divide-by-1, -2, -4 SNR = 69.6 dBFS, SFDR = 86 dBc at fIN = 70 MHz Ultra-Low Power Consumption: – 203 mW/Ch at 160 MSPS Channel Isolation: 105 dB Internal Dither JESD204B Serial Interface: – Subclass 0, 1, 2 Compliant up to 3.2 Gbps – Supports One Lane per ADC up to 160 MSPS Support for Multi-Chip Synchronization Pin-to-Pin Compatible with 14-Bit Version Package: VQFN-48 (7 mm × 7 mm) 2 Applications • • • • • • • • • • Multi-Carrier, Multi-Mode Cellular Base Stations Radar and Smart Antenna Arrays Munitions Guidance Motor Control Feedback Network and Vector Analyzers Communications Test Equipment Nondestructive Testing Microwave Receivers Software Defined Radios (SDRs) Quadrature and Diversity Radio Receivers Device Information(1) PART NUMBER SAMPLING RATE (MSPS) PACKAGE ADC34J22 50 ADC34J23 80 VQFN (48) ADC34J24 125 ADC34J25 160 (1) For all available packages, see the orderable addendum at the end of the datasheet. FFT with Dither On (fS = 160 MSPS, fIN = 10 MHz, SNR = 70.3 dBFS, SFDR = 84 dBc) 0 Amplitude (dBFS) ±20 ±40 ±60 ±80 ±100 ±120 0 16 32 48 Frequency (MHz 64 80 C001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 1 1 1 2 3 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Summary of Special Mode Registers........................ 6 Thermal Information .................................................. 6 Electrical Characteristics: ADC34J24, ADC34J25.... 7 Electrical Characteristics: ADC34J22, ADC34J23 ... 7 Electrical Characteristics: General ............................ 8 AC Performance: ADC34J25 .................................... 9 AC Performance: ADC34J24 ................................ 11 AC Performance: ADC34J23 ................................ 13 AC Performance: ADC34J22 ............................... 15 Digital Characteristics ........................................... 16 Timing Characteristics........................................... 17 Typical Characteristics: ADC34J25 ...................... 18 Typical Characteristics: ADC34J24 ...................... 24 Typical Characteristics: ADC34J23 ...................... 30 Typical Characteristics: ADC34J22 ...................... 36 7.19 Typical Characteristics: Common Plots ................ 42 7.20 Typical Characteristics: Contour Plots .................. 43 8 Parameter Measurement Information ................ 45 9 Detailed Description ............................................ 47 8.1 Timing Diagrams ..................................................... 45 9.1 9.2 9.3 9.4 9.5 9.6 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Map........................................................... 47 47 48 55 55 59 10 Application and Implementation........................ 75 10.1 Application Information.......................................... 75 10.2 Typical Applications .............................................. 75 11 Power-Supply Recommendations ..................... 78 12 Layout................................................................... 79 12.1 Layout Guidelines ................................................. 79 12.2 Layout Example .................................................... 79 13 Device and Documentation Support ................. 80 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 80 80 80 80 14 Mechanical, Packaging, and Orderable Information ........................................................... 80 4 Revision History Changes from Original (May 2014) to Revision A • 2 Page Changed document status from product preview to production data..................................................................................... 1 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 5 Device Comparison Table INTERFACE Serial LVDS JESD204B RESOLUTION (Bits) 25 MSPS 50 MSPS 80 MSPS 125 MSPS 160 MSPS 12 ADC3421 ADC3422 ADC3423 ADC3424 — 14 ADC3441 ADC3442 ADC3443 ADC3444 — 12 — ADC34J22 ADC34J23 ADC34J24 ADC34J25 14 — ADC34J42 ADC34J43 ADC34J44 ADC34J45 6 Pin Configuration and Functions DAM DAP AVDD DBM DBP SYNCP~ SYNCM~ DCM DCP AVDD DDM DDP RGZ Package VQFN-48 (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 OVRB 1 36 OVRC OVRA 2 35 OVRD DVDD 3 34 DVDD AVDD 4 33 PDN AVDD 5 32 AVDD INAM 6 31 INDM INAP 7 30 INDP AVDD 8 29 AVDD AVDD 9 28 AVDD INBP 10 27 INCP INBM 11 26 INCM AVDD 12 25 AVDD 13 14 15 16 17 18 19 20 21 22 23 24 SCLK SDATA SEN SDOUT AVDD CLKM CLKP AVDD RESET SYSREFP SYSREFM VCM GND Pad (Back Side) Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 3 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME NO. AVDD 4, 5, 8, 9, 12, 17, 20, 25, 28, 29, 32, 39, 46 I Analog 1.8-V power supply CLKM 18 I Negative differential clock input for the ADC CLKP 19 I Positive differential clock input for the ADC DAM 48 O Negative serial JESD204B output for channel A DAP 47 O Positive serial JESD204B output for channel A DBM 45 O Negative serial JESD204B output for channel B DBP 44 O Positive serial JESD204B output for channel B DCM 41 O Negative serial JESD204B output for channel C DCP 40 O Positive serial JESD204B output for channel C DDM 38 O Negative serial JESD204B output for channel D DDP 37 O Positive serial JESD204B output for channel D DVDD 3, 34 I Digital 1.8-V power supply GND PowerPAD™ I Ground, 0 V INAM 6 I Negative differential analog input for channel A INAP 7 I Positive differential analog input for channel A INBM 11 I Negative differential analog input for channel B INBP 10 I Positive differential analog input for channel B INCM 26 I Negative differential analog input for channel C INCP 27 I Positive differential analog input for channel C INDM 31 I Negative differential analog input for channel D INDP 30 I Positive differential analog input for channel D OVRA 2 O Overrange indicator for channel A OVRB 1 O Overrange indicator for channel B OVRC 36 O Overrange indicator for channel C OVRD 35 O Overrange indicator for channel D PDN 33 I Power-down control. This pin has an internal 150-kΩ pull-down resistor. RESET 21 I Hardware reset; active high. This pin has an internal 150-kΩ, pull-down resistor. SCLK 13 I Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor. SDATA 14 I Serial interface data input. This pin has an internal 150-kΩ pull-down resistor. SDOUT 16 O Serial interface data output SEN 15 I Serial interface enable. Active low. This pin has an internal 150-kΩ pull-up resistor to AVDD. SYNCM~ 42 I Negative JESD204B synch input SYNCP~ 43 I Positive JESD204B synch input SYSREFM 23 I Negative external SYSREF input SYSREFP 22 I Positive external SYSREF input VCM 24 O Common-mode voltage output for the analog inputs 4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage range, AVDD –0.3 2.1 V Supply voltage range, DVDD –0.3 2.1 V INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 Minimum (AVDD + 0.3, 2.1) V CLKP, CLKM (2) –0.3 Minimum (AVDD + 0.3, 2.1) V SYSREFP, SYSREFM, SYNCP~, SYNCM~ –0.3 Minimum (AVDD + 0.3, 2.1) V SCLK, SEN, SDATA, RESET, PDN –0.3 3.6 V Operating free-air, TA –40 85 °C 125 °C 150 °C Voltage applied to input pins: Temperature Operating junction, TJ Storage, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on. 7.2 ESD Ratings V(ESD) (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT VID Differential input voltage VIC Input common-mode voltage For input frequencies < 450 MHz For input frequencies < 600 MHz 2 VPP 1 VPP VCM ± 0.025 V CLOCK INPUT Input clock frequency Input clock amplitude (differential) Sampling clock frequency 25 Sine wave, ac-coupled 0.2 LPECL, ac-coupled LVDS, ac-coupled Input clock duty cycle 160 (2) MSPS 1.5 V 1.6 V 0.7 35 Input clock common-mode voltage 50 V 65 % 0.95 V DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Single-ended load resistance 100 Ω (1) (2) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section. With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 5 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.4 Summary of Special Mode Registers Table 1 lists the location, value, and functions of special mode registers in the device. Table 1. Special Modes Summary MODE Dither mode Special mode 1 Special mode 2 LOCATION DIS DITH CHA 01h [7:6], 134h[5,3] DIS DITH CHB 01h [5:4], 434h[5,3] DIS DITH CHC 01h [3:2], 534h[5,3] DIS DITH CHD 01h [1:0], 234h[5,3] SPECIAL MODE 1 CHA 06h[4:2] SPECIAL MODE 1 CHB 07h[4:2] SPECIAL MODE 1 CHC 08h[4:2] SPECIAL MODE 1 CHD 09h[4:2] SPECIAL MODE 2 CHA 122h[1:0] SPECIAL MODE 2 CHB 422h[1:0] SPECIAL MODE 2 CHC 522h[1:0] SPECIAL MODE 2 CHD 222h[1:0] VALUE AND FUNCTION Creates a noise floor cleaner and improves SFDR; see the Internal Dither Algorithm section. 0000 = Dither disabled 1111 = Dither enabled Use for better HD3. 000 = Default after reset 010 = Use for frequency < 120 MHz 111 = Use for frequency > 120 MHz Helps improve HD2. 00 = Default after reset 11 = Improves HD2 7.5 Thermal Information ADC34J2x THERMAL METRIC (1) RGZ (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 25.7 RθJC(top) Junction-to-case (top) thermal resistance 18.9 RθJB Junction-to-board thermal resistance 3.0 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 3 RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 (1) 6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.6 Electrical Characteristics: ADC34J24, ADC34J25 Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J24 PARAMETER MIN TYP ADC clock frequency ADC34J25 MAX MIN TYP 125 Resolution 12 MAX UNIT 160 MSPS 12 1.8-V analog supply (AVDD) current 1.8-V digital supply current Total power dissipation 490 354 490 mA 79 150 97 150 mA 715 1010 812 1010 mW Global power-down dissipation 22 Wake-up time from global power-down 85 Standby power-down dissipation 22 100 85 177 Wake-up time from standby power-down Bits 318 35 mW 100 µs 185 300 35 mW 300 µs 7.7 Electrical Characteristics: ADC34J22, ADC34J23 Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J22 PARAMETER MIN TYP ADC clock frequency ADC34J23 MAX MIN TYP 50 Resolution 12 1.8-V analog supply current 1.8-V digital supply current Total power dissipation Global power-down dissipation Wake-up time from global power-down Standby power-down dissipation Wake-up time from standby power-down Copyright © 2014–2015, Texas Instruments Incorporated MAX UNIT 80 MSPS 12 233 490 Bits 269 490 mA 39 150 56 150 mA 491 1010 584 1010 mW 22 85 22 100 85 155 35 mW 100 166 300 35 300 Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 µs mW µs 7 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.8 Electrical Characteristics: General Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT 2.0 VPP ri Differential input full-scale Input resistance Differential at dc 6.5 kΩ ci Input capacitance Differential at dc 5.2 pF VOC(VCM) VCM common-mode voltage output 0.95 V VCM output current capability 10 mA Input common-mode current Per analog input pin 1.5 µA/MSPS Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 450 MHz DC ACCURACY EO Offset error EG(REF) Gain error as a result of internal reference inaccuracy alone EG(CHAN) Gain error of channel alone –20 20 mV –3 3 %FS ±1 %FS Near channel 105 dB Far channel 105 dB 95 dB 105 dB 94 dB 105 dB 93 dB 105 dB 85 dB 105 dB CHANNEL-TO-CHANNEL ISOLATION fIN = 10 MHz fIN = 100 MHz Crosstalk (1) fIN = 200 MHz fIN = 230 MHz fIN = 300 MHz (1) 8 Near channel Far channel Near channel Far channel Near channel Far channel Near channel Far channel Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.9 AC Performance: ADC34J25 Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J25 (fS = 160 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 70.2 70.4 69.6 69.9 fIN = 100 MHz 69.3 69.6 fIN = 170 MHz 68.4 68.9 fIN = 230 MHz 67.5 68.1 149.2 149.4 148.6 148.9 fIN = 100 MHz 148.3 148.6 fIN = 170 MHz 147.4 147.9 fIN = 230 MHz 146.5 147.1 fIN = 10 MHz 70.1 70.3 69.5 69.7 Signal-to-noise and distortion ratio fIN = 100 MHz 69.2 69.4 fIN = 170 MHz 68.2 68.6 fIN = 230 MHz 67.2 67.5 11.4 11.4 11.3 11.3 fIN = 100 MHz 11.2 11.3 fIN = 170 MHz 11.1 11.1 fIN = 230 MHz 10.9 10.9 85 86 86 85 fIN = 100 MHz 86 87 fIN = 170 MHz 85 84 fIN = 230 MHz 81 80 91 92 94 93 fIN = 100 MHz 93 91 fIN = 170 MHz 83 83 fIN = 230 MHz 81 79 fIN = 10 MHz 85 86 85 85 fIN = 100 MHz 86 87 fIN = 170 MHz 93 87 fIN = 230 MHz 85 82 98 94 97 94 fIN = 100 MHz 96 93 fIN = 170 MHz 92 92 fIN = 230 MHz 90 89 fIN = 70 MHz SNR Signal-to-noise ratio 68.5 fIN = 10 MHz fIN = 70 MHz NSD Noise spectral density (averaged across Nyquist zone) fIN = 70 MHz SINAD 147.5 67.6 fIN = 10 MHz fIN = 70 MHz ENOB Effective number of bits 10.9 fIN = 10 MHz fIN = 70 MHz SFDR Spurious-free dynamic range 81 fIN = 10 MHz fIN = 70 MHz HD2 Second harmonic distortion fIN = 70 MHz HD3 Third harmonic distortion 81 81 fIN = 10 MHz fIN = 70 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) Copyright © 2014–2015, Texas Instruments Incorporated 87 dBFS dBFS/Hz dBFS Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 Bits dBc dBc dBc dBc 9 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com AC Performance: ADC34J25 (continued) Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J25 (fS = 160 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz IMD3 10 Total harmonic distortion Third-order intermodulation distortion Submit Documentation Feedback MAX MIN TYP 84 83 84 83 fIN = 100 MHz 84 84 fIN = 170 MHz 82 80 fIN = 230 MHz 78 76 fIN1 = 45 MHz, fIN2 = 50 MHz 92 92 fIN1 = 185 MHz, fIN2 = 190 MHz 87 87 fIN = 70 MHz THD TYP DITHER OFF 76.5 MAX UNIT dBc dBFS Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.10 AC Performance: ADC34J24 Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J24 (fS = 125 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 70.3 70.6 70.1 70.4 fIN = 100 MHz 69.9 70.2 fIN = 170 MHz 69.1 69.7 fIN = 230 MHz 68.6 69.1 148.3 148.6 148.1 148.4 fIN = 100 MHz 147.9 148.2 fIN = 170 MHz 147.1 147.7 fIN = 230 MHz 146.6 147.1 fIN = 10 MHz 70.3 70.5 70 70.3 Signal-to-noise and distortion ratio fIN = 100 MHz 69.8 70.1 fIN = 170 MHz 68.9 69.3 fIN = 230 MHz 68.4 68.8 11.4 11.4 11.4 11.4 fIN = 100 MHz 11.3 11.4 fIN = 170 MHz 11.2 11.3 fIN = 230 MHz 11.1 11.1 94 92 93 91 fIN = 100 MHz 93 92 fIN = 170 MHz 85 83 fIN = 230 MHz 83 82 93 93 94 94 fIN = 100 MHz 92 92 fIN = 170 MHz 83 83 fIN = 230 MHz 82 82 fIN = 10 MHz 96 93 94 91 fIN = 100 MHz 95 93 fIN = 170 MHz 88 86 fIN = 230 MHz 87 88 99 95 98 95 fIN = 100 MHz 97 95 fIN = 170 MHz 97 92 fIN = 230 MHz 95 92 fIN = 70 MHz SNR Signal-to-noise ratio 68.8 fIN = 10 MHz fIN = 70 MHz NSD Noise spectral density (averaged across Nyquist zone) fIN = 70 MHz SINAD 146.8 67.6 fIN = 10 MHz fIN = 70 MHz ENOB Effective number of bits 10.9 fIN = 10 MHz fIN = 70 MHz SFDR Spurious-free dynamic range 81 fIN = 10 MHz fIN = 70 MHz HD2 Second harmonic distortion fIN = 70 MHz HD3 Third harmonic distortion 81 83 fIN = 10 MHz fIN = 70 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) Copyright © 2014–2015, Texas Instruments Incorporated 87 dBFS dBFS/Hz dBFS Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 Bits dBc dBc dBc dBc 11 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com AC Performance: ADC34J24 (continued) Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J24 (fS = 125 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz IMD3 12 Total harmonic distortion Third-order intermodulation distortion Submit Documentation Feedback MAX MIN TYP 89 87 89 87 fIN = 100 MHz 89 87 fIN = 170 MHz 82 80 fIN = 230 MHz 81 80 fIN1 = 45 MHz, fIN2 = 50 MHz 97 97 fIN1 = 185 MHz, fIN2 = 190 MHz 89 89 fIN = 70 MHz THD TYP DITHER OFF 76.5 MAX UNIT dBc dBFS Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.11 AC Performance: ADC34J23 Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J23 (fS = 80 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 70.2 70.4 70 70.3 fIN = 100 MHz 69.9 70.1 fIN = 170 MHz 69.3 69.6 fIN = 230 MHz 68.7 68.9 146.1 146.3 145.9 146.2 fIN = 100 MHz 145.8 146.0 fIN = 170 MHz 145.2 145.5 fIN = 230 MHz 144.6 144.8 fIN = 10 MHz 70.2 70.3 70 70.2 Signal-to-noise and distortion ratio fIN = 100 MHz 69.8 69.9 fIN = 170 MHz 69.1 69.3 fIN = 230 MHz 68.2 68.4 11.4 11.4 11.4 11.4 fIN = 100 MHz 11.3 11.3 fIN = 170 MHz 11.2 11.3 fIN = 230 MHz 11.1 11.1 95 91 95 90 fIN = 100 MHz 90 89 fIN = 170 MHz 87 84 fIN = 230 MHz 80 80 95 95 95 94 fIN = 100 MHz 91 92 fIN = 170 MHz 83 83 fIN = 230 MHz 81 82 fIN = 10 MHz 99 94 101 94 fIN = 100 MHz 91 90 fIN = 170 MHz 92 90 fIN = 230 MHz 80 80 98 92 98 92 fIN = 100 MHz 97 91 fIN = 170 MHz 96 91 fIN = 230 MHz 93 91 fIN = 70 MHz SNR Signal-to-noise ratio 68.7 fIN = 10 MHz fIN = 70 MHz NSD Noise spectral density (averaged across Nyquist zone) fIN = 70 MHz SINAD 144.8 67.6 fIN = 10 MHz fIN = 70 MHz ENOB Effective number of bits 10.9 fIN= 10 MHz fIN = 70 MHz SFDR Spurious-free dynamic range 82 fIN = 10 MHz fIN = 70 MHz HD2 Second harmonic distortion fIN = 70 MHz HD3 Third harmonic distortion 82 83 fIN = 10 MHz fIN = 70 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) Copyright © 2014–2015, Texas Instruments Incorporated 87 dBFS dBFS/Hz dBFS Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 Bits dBc dBc dBc dBc 13 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com AC Performance: ADC34J23 (continued) Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J23 (fS = 80 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz IMD3 14 Total harmonic distortion Third-order intermodulation distortion Submit Documentation Feedback MAX MIN TYP 91 86 91 86 fIN = 100 MHz 87 84 fIN = 170 MHz 82 81 fIN = 230 MHz 77 77 fIN1 = 45 MHz, fIN2 = 50 MHz 95 95 fIN1 = 185 MHz, fIN2 = 190 MHz 88 88 fIN = 70 MHz THD TYP DITHER OFF 76.5 MAX UNIT dBc dBFS Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.12 AC Performance: ADC34J22 Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J22 (fS = 50 MSPS) DITHER ON PARAMETER TEST CONDITIONS DITHER OFF MIN TYP MAX MIN TYP 69.3 70.2 70.5 70 70.3 fIN = 100 MHz 69.9 70.2 fIN = 170 MHz 69.3 69.5 fIN = 230 MHz 67.9 68 144.2 144.5 144 144.3 fIN = 100 MHz 143.9 144.2 fIN = 170 MHz 143.3 143.5 fIN = 230 MHz 141.9 142 70.2 70.4 69.9 70.1 MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz fIN = 70 MHz SNR Signal-to-noise ratio fIN = 10 MHz 143.3 fIN = 70 MHz NSD Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz 67.6 fIN = 70 MHz SINAD Signal-to-noise and distortion ratio fIN = 100 MHz 69.8 70 fIN = 170 MHz 69.1 69.3 fIN = 230 MHz 67.5 67.6 fIN = 10 MHz ENOB Effective number of bits 11.4 11.4 fIN = 70 MHz 11.3 11.3 fIN = 100 MHz 11.3 11.3 fIN = 170 MHz 11.2 11.2 fIN = 230 MHz 10.9 10.9 95 91 fIN = 70 MHz 93 90 fIN = 100 MHz 90 89 fIN = 170 MHz 85 84 fIN = 230 MHz 80 80 fIN = 10 MHz SFDR Spurious-free dynamic range fIN = 10 MHz HD2 Second harmonic distortion Third harmonic distortion 94 93 93 93 fIN = 100 MHz 90 90 fIN = 170 MHz 83 83 fIN = 230 MHz 81 81 102 96 fIN = 70 MHz 94 92 fIN = 100 MHz 90 89 fIN = 170 MHz 91 90 fIN = 230 MHz 80 80 fIN = 10 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) Copyright © 2014–2015, Texas Instruments Incorporated 84.5 fIN = 70 MHz fIN = 10 MHz HD3 10.9 84.5 84.5 98 92 fIN = 70 MHz 87 97 92 fIN = 100 MHz 96 92 fIN = 170 MHz 95 91 fIN = 230 MHz 93 91 dBFS dBFS/Hz dBFS Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 Bits dBc dBc dBc dBc 15 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com AC Performance: ADC34J22 (continued) Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC34J22 (fS = 50 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP 76.5 91 86 fIN = 70 MHz 89 85 fIN = 100 MHz 86 84 fIN = 170 MHz 82 81 fIN = 230 MHz 77 77 fIN1 = 45 MHz, fIN2 = 50 MHz 93 93 fIN1 = 185 MHz, fIN2 = 190 MHz 86 86 fIN = 10 MHz THD Total harmonic distortion Third-order intermodulation distortion IMD3 DITHER OFF MAX MIN TYP MAX UNIT dBc dBFS 7.13 Digital Characteristics The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN 1.2 TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN) (1) VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels IIH High-level input current IIL SEN Low-level input current V 0.4 V 0 µA RESET, SCLK, SDATA, PDN 10 µA SEN 10 µA 0 µA RESET, SCLK, SDATA, PDN DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V V(CM_DIG) Common-mode voltage for SYNC~ and SYSREF 0.9 V DVDD V DIGITAL OUTPUTS (SDOUT, OVRA, OVRB, OVRC, OVRD) VOH High-level output voltage VOL Low-level output voltage DVDD – 0.1 0.1 V DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM) (2) VOH High-level output voltage DVDD V VOL Low-level output voltage DVDD – 0.4 V VOD Output differential voltage 0.4 V VOC Output common-mode voltage DVDD – 0.2 V Transmitter short-circuit current zos (2) 16 –100 Single-ended output impedance Output capacitance inside the device, from either output to ground Output capacitance (1) Transmitter pins shorted to any voltage between –0.25 V and 1.45 V 100 mA 50 Ω 2 pF RESET, SCLK, SDATA, and PDN pins have 150-kΩ (typical) internal pull-down resistor to ground, while SEN pin has 150-kΩ (typical) pull-up resistor to AVDD. 50-Ω, single-ended external termination to 1.8 V. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.14 Timing Characteristics Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. See Figure 143. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.85 1.25 1.65 ns SAMPLE TIMING CHARACTERISTICS Aperture delay Between two channels on the same device Aperture delay matching Between two devices at the same temperature and supply voltage Aperture jitter ±70 ps ±150 ps 200 Wake-up time fS rms Time to valid data after coming out of STANDBY mode 35 100 µs Time to valid data after coming out of global power-down 85 300 µs tSU_SYNC~ Setup time for SYNC~ Referenced to input clock rising edge 1 ns tH_SYNC~ Hold time for SYNC~ Referenced to input clock rising edge 100 ps tSU_SYSREF Setup time for SYSREF Referenced to input clock rising edge 1 ns tH_SYSREF Hold time for SYSREF Referenced to input clock rising edge 100 ps CML OUTPUT TIMING CHARACTERISTICS Unit interval 312.5 1667 Serial output data rate tR, tF 3.2 ps Gbps Total jitter 3.125 Gbps (20x mode, fS = 156.25 MSPS) 0.3 P-PUI Data rise time, data fall time Rise and fall times measured from 20% to 80%, differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps 105 ps Table 2. Latency in Different Modes (1) (2) MODE 20x 40x LATENCY (N Cycles) TYPICAL DATA DELAY (tD, ns) ADC latency PARAMETER 17 0.29 × tS + 3 Normal OVR latency 9 0.5 × tS + 2 Fast OVR latency 7 0.5 × tS + 2 From SYNC~ falling edge to CGS phase (3) 15 0.3 × tS + 4 From SYNC~ rising edge to ILA sequence (4) 17 0.3 × tS + 4 ADC latency 16 0.85 × tS + 3.9 Normal OVR latency 9 0.5 × tS + 2 Fast OVR latency 7 0.5 × tS + 2 From SYNC~ falling edge to CGS phase (3) 14 0.9 × tS + 4 12 0.9 × tS + 4 From SYNC~ rising edge to ILA sequence (1) (2) (3) (4) (4) Overall latency = latency + tD. tS is the time period of the ADC conversion clock. Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15 clock cycles in 20x mode. Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and 11 clock cycles in 20x mode. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 17 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.15 Typical Characteristics: ADC34J25 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 0 16 32 48 64 Frequency (MHz ±120 80 0 64 80 C002 Figure 2. FFT for 10-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 48 fS = 160 MSPS, SNR = 70.7 dBFS, fIN = 10 MHz, SFDR = 81.1 dBc Figure 1. FFT for 10-MHz Input Signal (Dither On) ±40 ±60 ±80 ±40 ±60 ±80 ±100 ±100 ±120 ±120 0 16 32 48 64 Frequency (MHz) 0 80 16 32 48 64 Frequency (MHz) C003 80 C004 fS = 160 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 87.5 dBc fS = 160 MSPS, SNR = 69.7 dBFS, fIN = 70 MHz, SFDR = 86 dBc Figure 4. FFT for 70-MHz Input Signal (Dither Off) Figure 3. FFT for 70-MHz Input Signal (Dither On) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 32 Frequency (MHz) fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 84 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 16 32 48 64 Frequency (MHz) fS = 160 MSPS, SNR = 67.9 dBFS, fIN = 170 MHz, SFDR = 84.1 dBc Figure 5. FFT for 170-MHz Input Signal (Dither On) 18 16 C001 Submit Documentation Feedback 80 C005 0 16 32 48 64 Frequency (MHz) 80 C006 fS = 160 MSPS, SNR = 68.1 dBFS, fIN = 70 MHz, SFDR = 82.7 dBc Figure 6. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J25 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 16 32 48 64 80 Frequency (MHz) 0 48 64 80 C008 fS = 160 MSPS, SNR = 67.5 dBFS, fIN = 270 MHz, SFDR = 75.9 dBc Figure 7. FFT for 270-MHz Input Signal (Dither On) Figure 8. FFT for 270-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 32 Frequency (MHz) fS = 160 MSPS, SNR = 67.0 dBFS, fIN = 270 MHz, SFDR = 76.2 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 16 32 48 64 80 Frequency (MHz) 0 16 32 48 64 80 Frequency (MHz) C009 fS = 160 MSPS, SNR = 62.9 dBFS, fIN = 450 MHz, SFDR = 67.8 dBc C010 fS = 160 MSPS, SNR = 63.6 dBFS, fIN = 450 MHz, SFDR = 67.6 dBc Figure 9. FFT for 450-MHz Input Signal (Dither On) Figure 10. FFT for 450-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 16 C007 ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 16 32 48 64 80 Frequency (MHz) fS = 160 MSPS, IMD = 92 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 96 dBFS Figure 11. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated C011 0 16 32 48 64 80 Frequency (MHz) C012 fS = 160 MSPS, IMD = 98 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 102 dBFS Figure 12. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 19 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J25 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. ±40 ±60 ±80 ±40 ±60 ±80 ±100 ±100 ±120 ±120 0 16 32 48 64 0 80 Frequency (MHz) 16 fS = 160 MSPS, IMD = 87 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 90 dBFS 48 64 80 C014 fS = 160 MSPS, IMD = 98 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 102 dBFS Figure 13. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 14. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) ±85 ±85 ±90 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) 32 Frequency (MHz) C013 ±95 ±100 ±105 ±110 ±90 ±95 ±100 ±105 ±35 ±31 ±27 ±23 ±19 ±15 ±11 ±7 Each Tone Amplitude (dBFS) Figure 15. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) 72 ±35 ±31 ±27 ±23 ±19 ±15 ±11 ±7 Each Tone Amplitude (dBFS) C015 C016 Figure 16. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 95 Dither_EN Dither_DIS Dither_EN Dither_DIS 90 SFDR (dBc) SNR (dBFS) 70 68 85 80 75 66 70 64 65 0 50 100 150 200 250 Frequency (MHz) 300 350 400 C017 Figure 17. Signal-to-Noise Ratio vs Input Frequency 20 Submit Documentation Feedback 0 50 100 150 200 250 300 350 Frequency (MHz) 400 C018 Figure 18. Spurious-Free Dynamic Range vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J25 (continued) Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. 77.5 10 MHz 100 MHz 230 MHz 400 MHz 75 10 MHz 100 MHz 230 MHz 400 MHz 105 100 SFDR (dBc) SNR (dBFS) 72.5 110 70 MHz 170 MHz 270 MHz 70 67.5 70 MHz 170 MHz 270 MHz 95 90 85 80 65 75 62.5 70 65 60 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Digital Gain (dB) 0 6 100 72 80 71 60 70 -40 -30 Amplitude (dBFS) -20 -10 60 40 69 40 20 68 -70 20 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 0 C022 Figure 22. Performance vs Input Amplitude (170 MHz) 70 87.5 SNR (dBFS) SFDR (dBc) 92.5 SNR (dBFS) 69.5 SFDR (dBc) SNR (dBFS) 6 85 69 82.5 68.5 80 85 69.5 69 0.85 5.5 C020 70 87.5 70 5 80 90 70.5 4.5 71 95 71 4 100 Figure 21. Performance vs Input Amplitude (30 MHz) 71.5 3.5 72 C021 SNR (dBFS) SFDR (dBc) 3 73 0 72 2.5 140 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 120 SNR (dBFS) 73 -50 2 74 SFDR (dBc,dBFS) SNR (dBFS) 74 -60 1.5 Figure 20. Spurious-Free Dynamic Range vs Digital Gain and Input Frequency 140 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 120 69 -70 1 Digital Gain (dB) Figure 19. Signal-to-Noise Ratio vs Digital Gain and Input Frequency 75 0.5 C019 SFDR (dBc,dBFS) 0.5 SFDR (dBc) 0 82.5 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 80 1.1 C023 Figure 23. Performance vs Input Common-Mode Voltage (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 68 67.5 0.85 77.5 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 75 1.1 C024 Figure 24. Performance vs Input Common-Mode Voltage (170 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 21 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J25 (continued) Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. 94 70.5 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 92 AVDD = 1.85 V AVDD = 1.9 V 90 86 84 69 68.5 68 82 67.5 80 78 -40 -15 10 35 Temperature (°C) 60 67 -40 85 -15 85 C026 70.5 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 92 DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 70 90 DVDD = 1.85 V DVDD = 1.9 V 69.5 88 SNR (dBFS) 86 84 69 68.5 68 82 67.5 80 78 -40 -15 10 35 Temperature (°C) 60 67 -40 85 -15 Figure 27. Spurious-Free Dynamic Range vs DVDD Supply and Temperature 100 71 90 70 80 69 70 68 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) Figure 29. Performance vs Clock Amplitude (40 MHz) Submit Documentation Feedback 90 71 85 69 80 67 75 65 70 63 60 0.4 95 SNR SFDR 73 SNR (dBFS) 72 85 C028 75 110 SNR SFDR 60 Figure 28. Signal-to-Noise Ratio vs DVDD Supply and Temperature SFDR (dBc) 73 0.2 10 35 Temperature (°C) C027 65 0.2 C029 SFDR (dBc) SFDR (dBc) 60 Figure 26. Signal-to-Noise Ratio vs AVDD Supply and Temperature 94 SNR (dBFS) 10 35 Temperature (°C) C025 Figure 25. Spurious-Free Dynamic Range vs AVDD Supply and Temperature 22 AVDD = 1.85 V AVDD = 1.9 V 69.5 88 SNR (dBFS) SFDR (dBc) AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 70 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) C030 Figure 30. Performance vs Clock Amplitude (150 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J25 (continued) Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted. 70.6 95 70.4 90 70.2 85 70 80 69.8 40 50 60 70 95 69.5 90 69 85 68.5 80 68 75 30 75 30 70 Input Clock Duty Cycle (%) 100 SNR SFDR SFDR (dBc) 100 SNR (dBFS) SNR (dBFS) 70.8 70.5 105 SNR SFDR SFDR (dBc) 71 40 50 60 70 Input Clock Duty Cycle (%) C031 Figure 31. Performance vs Clock Duty Cycle (40 MHz) C032 Figure 32. Performance vs Clock Duty Cycle (150 MHz) 70 56.21 Code Occurrence (%) 60 50 43.03 40 30 20 10 0.61 Output Code (LSB) 2044 2045 2046 2047 0.15 0 C033 RMS noise = 1.3 LSBs Figure 33. Idle Channel Histogram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 23 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.16 Typical Characteristics: ADC34J24 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 12.5 25 37.5 50 Frequency (MHz) 62.5 0 50 62.5 C002 Figure 35. FFT for 10-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 37.5 fS = 125 MSPS, SNR = 70.5 dBFS, fIN = 10 MHz, SFDR = 90.9 dBc Figure 34. FFT for 10-MHz Input Signal (Dither On) ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0.0 12.5 25.0 37.5 50.0 Frequency (MHz) 62.5 0 12.5 25 37.5 50 Frequency (MHz) C003 fS = 125 MSPS, SNR = 70 dBFS, fIN = 70 MHz, SFDR = 93.5 dBc 62.5 C004 fS = 125 MSPS, SNR = 70.3 dBFS, fIN = 70 MHz, SFDR = 94.3 dBc Figure 37. FFT for 70-MHz Input Signal (Dither Off) Figure 36. FFT for 70-MHz Input Signal (Dither On) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 25 Frequency (MHz) fS = 125 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 91.3 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 12.5 25 37.5 50 Frequency (MHz) 24 12.5 C001 62.5 C005 0 12.5 25 37.5 50 Frequency (MHz) fS = 125 MSPS, SNR = 69 dBFS, fIN = 170 MHz, SFDR = 85.9 dBc fS = 125 MSPS, SNR = 69.6 dBFS, fIN = 70 MHz, SFDR = 86.5 dBc Figure 38. FFT for 170-MHz Input Signal (Dither On) Figure 39. FFT for 170-MHz Input Signal (Dither Off) Submit Documentation Feedback 62.5 C006 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J24 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 12.5 25 37.5 50 62.5 Frequency (MHz) 0 37.5 50 62.5 C008 fS = 125 MSPS, SNR = 68.8 dBFS, fIN = 270 MHz, SFDR = 79.6 dBc Figure 40. FFT for 270-MHz Input Signal (Dither On) Figure 41. FFT for 270-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 25 Frequency (MHz) fS = 125 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz, SFDR = 79.8 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 12.5 25 37.5 50 62.5 Frequency (MHz) 0 12.5 25 37.5 50 Frequency (MHz) C009 fS = 125 MSPS, SNR = 66.1 dBFS, fIN = 450 MHz, SFDR = 63.1 dBc Figure 42. FFT for 450-MHz Input Signal (Dither On) Figure 43. FFT for 450-MHz Input Signal (Dither Off) 0 0 ±20 ±20 ±40 ±60 ±80 ±100 62.5 C010 fS = 125 MSPS, SNR = 65.2 dBFS, fIN = 450 MHz, SFDR = 62.9 dBc Amplitude (dBFS) Amplitude (dBFS) 12.5 C007 ±40 ±60 ±80 ±100 ±120 ±120 0 12.5 25 37.5 50 62.5 Frequency (MHz) fS = 125 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 97 dBFS Figure 44. FFT for Two-Tone Input Signal (–7dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated C011 0 12.5 25 37.5 50 Frequency (MHz) 62.5 C012 fS = 125 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 106 dBFS Figure 45. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J24 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 12.5 25 37.5 50 62.5 Frequency (MHz) 0 fS = 125 MSPS, IMD = 89 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 92 dBFS 37.5 50 62.5 C014 fS = 125 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 103 dBFS Figure 47. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) ±85 ±85 ±90 ±90 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) 25 Frequency (MHz) Figure 46. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) ±95 ±100 ±105 ±110 ±95 ±100 ±105 ±110 ±35 ±31 ±27 ±23 ±19 ±15 ±11 ±7 Each Tone Amplitude (dBFS) ±35 ±31 ±27 ±23 ±19 ±15 ±11 ±7 Each Tone Amplitude (dBFS) C015 C016 Figure 48. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) Figure 49. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 71 95 Dither_EN Dither_EN 90 Dither_DIS Amplitude (dBFS) 70 SNR (dBFS) 12.5 C013 69 68 Dither_DIS 85 80 75 70 67 65 66 60 0 50 100 150 200 250 300 350 Frequency (MHz) Figure 50. Signal-to-Noise Ratio vs Input Frequency 26 Submit Documentation Feedback 400 C017 0 50 100 150 200 250 300 350 Frequency (MHz) 400 C018 Figure 51. Spurious-Free Dynamic Range vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J24 (continued) 70.5 70 69.5 69 68.5 68 67.5 67 66.5 66 65.5 65 64.5 64 120 10 MHz 70 MHz 100 MHz 170 MHz 230 MHz 270 MHz 400 MHz 110 SFDR (dBc) 170 MHz 230 MHz 270 MHz 400 MHz 100 90 80 60 1 1.5 2 2.5 3 3.5 4 Digital Gain (dB) 4.5 5 5.5 0 6 72 100 71 80 70 60 69 68 67 -70 -50 -40 -30 -20 Input Amplitude (dBFS) 2 -10 3 3.5 4 4.5 5 5.5 73 72 100 71 80 70 60 40 69 40 20 68 20 0 67 -70 74 0 Figure 54. Performance vs Input Amplitude (30 MHz) 0 -60 -50 -40 -30 -20 Input Amplitude (dBFS) -10 0 C022 Figure 55. Performance vs Input Amplitude (170 MHz) 69.6 73 93 69.4 84 72.8 92 69.2 83.5 72.6 91 72.4 90 68.8 89 68.6 0.85 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBc) SNR SFDR SFDR (dBc) 94 72.2 0.85 1.1 C023 Figure 56. Performance vs Input Common-Mode Voltage (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 6 C020 160 SNR (dBFS) SFDR (dBc) 140 SFDR (dBFS) 120 C021 73.2 2.5 75 SNR (dBFS) 73 -60 1.5 Figure 53. Spurious-Free Dynamic Range vs Digital Gain and Input Frequency 160 SNR (dBFS) SFDR (dBc) 140 SFDR (dBFS) 120 74 1 Digital Gain (dB) SFDR (dBc,dBFS) 75 0.5 C019 SFDR (dBc,dBFS) 0.5 Figure 52. Signal-to-Noise Ratio vs Digital Gain and Input Frequency SNR (dBFS) 70 MHz 100 MHz 70 0 SNR (dBFS) 10 MHz 84.5 SNR SFDR 69 83 SFDR (dBc ,dBFS) SNR (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 82.5 82 0.9 0.95 1 1.05 1.1 Input Common-Mode Voltage (V) C024 Figure 57. Performance vs Input Common-Mode Voltage (170 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 27 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J24 (continued) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 94 70.5 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 92 AVDD = 1.85 V AVDD = 1.9 V 90 86 84 69 68.5 68 82 67.5 80 78 -40 -15 10 35 Temperature (°C) 60 67 -40 85 -15 85 C026 70.5 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 92 DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 70 90 DVDD = 1.85 V DVDD = 1.9 V 69.5 88 SNR (dBFS) 86 84 69 68.5 68 82 67.5 80 78 -40 -15 10 35 Temperature (°C) 60 67 -40 85 -15 10 35 Temperature (°C) C027 Figure 60. Spurious-Free Dynamic Range vs DVDD Supply and Temperature 85 C028 Figure 61. Signal-to-Noise Ratio vs DVDD Supply and Temperature 74 72 95 72 90 71 90 70 80 70 85 68 70 69 80 66 60 75 64 68 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) Figure 62. Performance vs Clock Amplitude (40 MHz) Submit Documentation Feedback SNR (dBFS) 100 SNR SFDR SFDR (dBc) 73 60 50 0.2 C029 100 SNR SFDR SFDR (dBc) SFDR (dBc) 60 Figure 59. Signal-to-Noise Ratio vs AVDD Supply and Temperature 94 SNR (dBFS) 10 35 Temperature (°C) C025 Figure 58. Spurious-Free Dynamic Range vs AVDD Supply and Temperature 28 AVDD = 1.85 V AVDD = 1.9 V 69.5 88 SNR (dBFS) SFDR (dBc) AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 70 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) C030 Figure 63. Performance vs Clock Amplitude (150 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J24 (continued) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 71 100 70.5 90 70 85 69.5 80 75 71 95 70.5 90 70 85 69 80 68.5 69.5 30 40 50 60 70 70 30 Input Clock Duty Cycle (%) 95 SNR SFDR SFDR (dBc) SNR (dBFS) 71.5 105 SNR (dBFS) SNR SFDR SFDR (dBc) 72 40 50 60 70 Input Clock Duty Cycle (%) C031 Figure 64. Performance vs Clock Duty Cycle (40 MHz) C032 Figure 65. Performance vs Clock Duty Cycle (150 MHz) 80 60 40 32.82 20 2047 0.06 2048 2049 0.87 0 Output Code (LSB) 2046 Code Occurrence (%) 66.25 C033 RMS noise = 1.4 LSBs Figure 66. Idle Channel Histogram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 29 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.17 Typical Characteristics: ADC34J23 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 Frequency (MHz) 40 0 fS = 80 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 96.6 dBc 32 40 C002 Figure 68. FFT for 10-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 24 fS = 80 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz, SFDR = 90.3 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 Frequency (MHz) 40 0 8 16 24 32 Frequency (MHz) C003 fS = 80 MSPS, SNR = 70 dBFS, fIN = 70 MHz, SFDR = 99.5 dBc 40 C004 fS = 80 MSPS, SNR = 70.4 dBFS, fIN = 70 MHz, SFDR = 90.1 dBc Figure 69. FFT for 70-MHz Input Signal (Dither On) Figure 70. FFT for 70-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 16 Frequency (MHz) Figure 67. FFT for 10-MHz Input Signal (Dither On) ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 Frequency (MHz) fS = 80 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz, SFDR = 92.7 dBc Figure 71. FFT for 170-MHz Input Signal (Dither On) 30 8 C001 Submit Documentation Feedback 40 C005 0 8 16 24 32 Frequency (MHz) 40 C006 fS = 80 MSPS, SNR = 69.6 dBFS, fIN = 10 MHz, SFDR = 92.9 dBc Figure 72. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J23 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 Frequency (MHz) 40 0 24 32 40 C008 fS = 80 MSPS, SNR = 68.3 dBFS, fIN = 270 MHz, SFDR = 76.9 dBc Figure 73. FFT for 270-MHz Input Signal (Dither On) Figure 74. FFT for 270-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 16 Frequency (MHz) fS = 80 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz, SFDR = 76.4 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 Frequency (MHz) 40 0 8 16 24 32 C010 fS = 80 MSPS, SNR = 65.5 dBFS, fIN = 450 MHz, SFDR = 63.3 dBc fS = 80 MSPS, SNR = 66.2 dBFS, fIN = 450 MHz, SFDR = 62.9 dBc Figure 75. FFT for 450-MHz Input Signal (Dither On) Figure 76. FFT for 450-MHz Input Signal (Dither Off) 0 0 ±20 ±20 ±40 ±60 ±80 ±100 40 Frequency (MHz) C009 Amplitude (dBFS) Amplitude (dBFS) 8 C007 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 Frequency (MHz) fS = 80 MSPS, IMD = 95 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 99 dBFS Figure 77. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 40 C011 0 8 16 24 32 40 Frequency (MHz) C012 fS = 80 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 106 dBFS Figure 78. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 31 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J23 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 8 16 24 32 40 Frequency (MHz) 0 fS = 80 MSPS, IMD = 88 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 94 dBFS 24 32 40 C014 fS = 80 MSPS, IMD = 100 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 102 dBFS Figure 80. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) ±85 ±85 ±90 ±90 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) 16 Frequency (MHz) Figure 79. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) ±95 ±100 ±105 ±95 ±100 ±105 ±110 ±110 ±35 ±31 ±27 ±23 ±19 ±15 ±11 Each Tone Amplitude (dBFS) ±35 ±7 71 ±27 ±23 ±19 ±15 ±11 Each Tone Amplitude (dBFS) ±7 C016 Figure 82. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 100 Dither_EN Dither_EN 95 Dither_DIS Amplitude (dBFS) 70 ±31 C015 Figure 81. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) SNR (dBFS) 8 C013 69 68 Dither_DIS 90 85 80 75 67 70 66 65 0 50 100 150 200 250 300 350 Frequency (MHz) Figure 83. Signal-to-Noise Ratio vs Input Frequency 32 Submit Documentation Feedback 400 C017 0 50 100 150 200 250 300 350 Frequency (MHz) 400 C018 Figure 84. Spurious-Free Dynamic Range vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J23 (continued) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 72 10 MHz 100 MHz 230 MHz 400 MHz 71 10 MHz 100 MHz 230 MHz 400 MHz 105 SFDR (dBc) SNR (dBFS) 70 115 70 MHz 170 MHz 270 MHz 69 68 67 66 70 MHz 170 MHz 270 MHz 95 85 75 65 64 65 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 6 Digital Gain (dB) 73 100 72 80 71 60 70 40 69 -70 20 68 -70 -10 SNR (dBFS) 0 SNR (dBFS) 92 70.5 91 70.25 90 70 89 1.1 C023 Figure 89. Performance vs Input Common-Mode Voltage (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 6 C020 71 80 70 60 69 40 20 -60 -50 -40 -30 -20 Input Amplitude (dBFS) -10 0 C022 86 SNR SFDR 85 69.2 84 69 83 68.8 82 68.6 81 68.4 0.85 88 Input Common-Mode Voltage (V)) 5.5 100 69.4 70.75 1.05 5 72 69.6 93 1 4.5 120 94 71 0.95 4 73 95 SNR (dBFS) SNR SFDR 0.9 3.5 Figure 88. Performance vs Input Amplitude (170 MHz) SFDR (dBc) 71.5 3 160 SNR (dBFS) SFDR (dBc) 140 SFDR (dBFS) C021 71.25 2.5 74 Figure 87. Performance vs Input Amplitude (30 MHz) 69.75 0.85 2 75 SFDR (dBc,dBFS) SNR (dBFS) 74 -50 -40 -30 -20 Input Amplitude (dBFS) 1.5 Figure 86. Spurious-Free Dynamic Range vs Digital Gain and Input Frequency 140 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 120 -60 1 Digital Gain (dB) Figure 85. Signal-to-Noise Ratio vs Digital Gain and Input Frequency 75 0.5 C019 SFDR (dBc,dBFS) 0.5 SFDR (dBc) 0 80 0.9 0.95 1 1.05 1.1 Input Common-Mode Voltage (V)) C024 Figure 90. Performance vs Input Common-Mode Voltage (170 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 33 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J23 (continued) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 90 71 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 89 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 70.5 AVDD = 1.85 V AVDD = 1.9 V SNR (dBFS) SFDR (dBFS) 88 87 86 70 69.5 69 85 68.5 84 83 -40 -15 10 35 Temperature (°C) 60 68 -40 85 -15 10 35 Temperature (°C) C025 Figure 91. Spurious-Free Dynamic Range vs AVDD Supply and Temperature 60 85 C026 Figure 92. Signal-to-Noise Ratio vs AVDD Supply and Temperature 90 71 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 89 DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 70.5 DVDD = 1.85 V DVDD = 1.9 V SNR (dBFS) 87 86 70 69.5 69 85 68.5 84 83 -40 -15 10 35 Temperature (°C) 60 68 -40 85 -15 Figure 93. Spurious-Free Dynamic Range vs DVDD Supply and Temperature 60 85 C028 Figure 94. Signal-to-Noise Ratio vs DVDD Supply and Temperature 80 72 95 75 90 70 90 70 85 68 85 65 80 66 80 60 75 75 55 64 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) Figure 95. Performance vs Clock Amplitude (40 MHz) Submit Documentation Feedback SNR (dBFS) 100 SNR SFDR SFDR (dBc) SNR (dBFS) 74 34 10 35 Temperature (°C) C027 70 0.2 C029 95 SNR SFDR SFDR (dBc) SFDR (dBFS) 88 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) C030 Figure 96. Performance vs Clock Amplitude (150 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J23 (continued) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 105 71 100 70.5 95 70 90 69.5 71 SNR (dBFS) 71.5 40 50 60 70 90 70 85 69 80 69 75 70 70 30 Input Clock Duty Cycle (%) 95 68 85 30 100 SNR SFDR SFDR (dBc) 71 110 SNR SFDR SFDR (dBc) SNR (dBFS) 72 40 50 60 70 Input Clock Duty Cycle (%) C031 Figure 97. Performance vs Clock Duty Cycle (40 MHz) C032 Figure 98. Performance vs Clock Duty Cycle (150 MHz) 100 80 60 40 11.22 4.74 0 2046 0 2047 0 2049 0 Output Code (LSB) 2045 20 2048 Code Occurrence (%) 84.03 C033 RMS noise = 1.4 LSBs Figure 99. Idle Channel Histogram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 35 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.18 Typical Characteristics: ADC34J22 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 5 10 15 20 Frequency (MHz) 25 0 fS = 50 MSPS, SNR = 70.2 dBFS, fIN = 10 MHz, SFDR = 96.5 dBc 20 25 C002 Figure 101. FFT for 10-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 15 fS = 50 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz, SFDR = 90.4 dBc ±40 ±60 ±80 ±40 ±60 ±80 ±100 ±100 ±120 ±120 0 5 10 15 20 Frequency (MHz) 0 25 5 10 15 20 Frequency (MHz) C003 fS = 50 MSPS, SNR = 69.9 dBFS, fIN = 70 MHz, SFDR = 92.6 dBc 25 C004 fS = 50 MSPS, SNR = 70.3 dBFS, fIN = 70 MHz, SFDR = 88 dBc Figure 103. FFT for 70-MHz Input Signal (Dither Off) Figure 102. FFT for 70-MHz Input Signal (Dither On) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 10 Frequency (MHz) Figure 100. FFT for 10-MHz Input Signal (Dither On) ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 5 10 15 20 Frequency (MHz) fS = 50 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz, SFDR = 88.7 dBc Figure 104. FFT for 170-MHz Input Signal (Dither On) 36 5 C001 Submit Documentation Feedback 25 C005 0 5 10 15 20 Frequency (MHz) 25 C006 fS = 50 MSPS, SNR = 69.5 dBFS, fIN = 170 MHz, SFDR = 88.5 dBc Figure 105. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J22 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 5 10 15 20 Frequency (MHz) 25 0 15 20 25 C008 fS = 50 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz, SFDR = 76.5 dBc Figure 106. FFT for 270-MHz Input Signal (Dither On) Figure 107. FFT for 270-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 10 Frequency (MHz) fS = 50 MSPS, SNR = 68.3 dBFS, fIN = 270 MHz, SFDR = 76.9 dBc ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 ±120 0 5 10 15 20 Frequency (MHz) 25 0 5 10 15 20 Frequency (MHz) C009 fS = 50 MSPS, SNR = 66.1 dBFS, fIN = 450 MHz, SFDR = 63.1 dBc 25 C010 fS = 50 MSPS, SNR = 66.3 dBFS, fIN = 450 MHz, SFDR = 63.2 dBc Figure 108. FFT for 450-MHz Input Signal (Dither On) Figure 109. FFT for 450-MHz Input Signal (Dither Off) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) 5 C007 ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 0 5 10 15 20 Frequency (MHz) fS = 50 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 96 dBFS Figure 110. FFT for Two-Tone Input Signal (–7dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 25 C011 ±120 0 5 10 15 20 Frequency (MHz) 25 C012 fS = 50 MSPS, IMD = 99 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz, SFDR = 106 dBFs Figure 111. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 37 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J22 (continued) 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. ±40 ±60 ±80 ±100 ±40 ±60 ±80 ±100 ±120 0 5 10 15 20 ±120 25 Frequency (MHz) 0 fS = 50 MSPS, IMD = 86 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 92 dBFS 20 25 C014 Figure 113. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) ±85 ±80 ±90 ±85 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) 15 fS = 50 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz, SFDR = 102 dBFs ±95 ±100 ±105 ±90 ±95 ±100 ±105 ±110 ±110 ±35 ±31 ±27 ±23 ±19 ±15 ±11 ±7 Each Tone Amplitude (dBFS) ±35 71 ±27 ±23 ±19 ±15 ±11 ±7 Each Tone Amplitude (dBFS) C016 Figure 115. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 100.0 Dither_EN 70.5 ±31 C015 Figure 114. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) Dither_EN 95.0 Dither_DIS 70 Dither_DIS 90.0 69.5 SFDR (dBc) SNR (dBFS) 10 Frequency (MHz) Figure 112. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) 69 68.5 68 85.0 80.0 75.0 67.5 70.0 67 65.0 66.5 60.0 0 50 100 150 200 250 300 350 400 Frequency (MHz) Figure 116. Signal-to-Noise Ratio vs Input Frequency 38 5 C013 Submit Documentation Feedback C017 0 50 100 150 200 250 300 350 Frequency (MHz) 400 C018 Figure 117. Spurious-Free Dynamic Range vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J22 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 72 120 71 70 MHz 100 MHz 170 MHz 270 MHz 400 MHz 110 SFDR (dBc) SNR (dBFS) 70 10 MHz 69 68 10 MHz 70 MHz 100 MHz 170 MHz 270 MHz 400 MHz 100 90 67 80 66 65 70 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Digital Gain (dB) 6 0 1 1.5 2 160 SNR SFDR 140 SFDR 73 120 72 100 71 80 70 3.5 60 69 40 68 -70 20 73.5 4 4.5 5 -50 -40 -30 Amplitude (dBFS) -20 -10 72.5 72 100 71.5 90 71 80 70.5 70 70 60 69.5 50 69 40 68 -70 0 SNR (dBFS) SFDR (dBc) 70 70.4 95 70.2 90 70 85 1 1.05 SNR (dBFS) Input Common-Mode Voltage (V) 0 C022 87 SNR SFDR 86 85 69.5 84 69 68 0.85 1.1 C023 Figure 122. Performance vs Input Common-Mode Voltage (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated -10 83 68.5 80 0.95 SNR (dBFS) 100 SFDR (dBc) 70.6 0.9 -50 -40 -30 -20 Input Amplitude (dBFS) 71 110 70.5 69.8 0.85 -60 Figure 121. Performance vs Input Amplitude (170 MHz) 105 70.8 30 20 C021 Figure 120. Performance vs Input Amplitude (30 MHz) 71 6 C020 68.5 -60 5.5 130 SNR (dBFS) 120 SFDR (dBc) SFDR (dBFS) 110 73 SNR (dBFS) 74 3 Figure 119. Spurious-Free Dynamic Range vs Digital Gain and Input Frequency SFDR (dBc,dBFS) 75 2.5 Digital Gain (dB) Figure 118. Signal-to-Noise Ratio vs Digital Gain and Input Frequency SNR (dBFS) 0.5 C019 SFDR (dBc,dBFS) 0.5 SFDR (dBc) 0 82 0.9 0.95 1 1.05 1.1 Input Common-Mode Voltage (V) C024 Figure 123. Performance vs Input Common-Mode Voltage (170 MHz) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 39 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: ADC34J22 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 110 70.6 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 70.4 SNR (dBFS) 100 95 90 70.2 70 69.8 85 -40 -15 10 35 Temperature (°C) 60 69.6 -40 85 -15 85 C026 70.6 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 70.4 SNR (dBFS) 105 100 95 90 DVDD = 1.85 V DVDD = 1.9 V 70.2 70 69.8 85 -40 -15 10 35 Temperature (°C) 60 85 69.6 -40 -15 70 90 68 85 66 80 64 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 75 2.2 C029 Figure 128. Performance vs Clock Amplitude (40 MHz) Submit Documentation Feedback SNR (dBFS) 95 85 C028 76 100 72 60 Figure 127. Signal-to-Noise Ratio vs DVDD Supply and Temperature 105 SNR SFDR SFDR (dBc) 76 74 10 35 Temperature (°C) C027 Figure 126. Spurious-Free Dynamic Range vs DVDD Supply and Temperature SNR (dBFS) 60 Figure 125. Signal-to-Noise Ratio vs AVDD Supply and Temperature 110 SFDR (dBFS) 10 35 Temperature (°C) C025 Figure 124. Spurious-Free Dynamic Range vs AVDD Supply and Temperature 40 AVDD = 1.85 V AVDD = 1.9 V 90 SNR SFDR 72 85 68 80 64 75 60 70 56 SFDR (dBc) SFDR (dBFS) 105 AVDD = 1.85 V AVDD = 1.9 V 65 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Differential Clock Amplitudes (Vpp) C030 Figure 129. Performance vs Clock Amplitude (150 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Characteristics: ADC34J22 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 71 71 105 70 95 70.5 100 70 90 69 85 80 70 95 69.5 90 69 85 68 69 30 40 50 60 70 75 30 Input Clock Duty Cycle (%) 100 SNR SFDR SFDR (dBc) SNR (dBFS) 110 SNR SFDR SFDR (dBc) SNR (dBFS) 71.5 40 50 60 70 Input Clock Duty Cycle (%) C031 Figure 130. Performance vs Clock Duty Cycle (40 MHz) C032 Figure 131. Performance vs Clock Duty Cycle (150 MHz) 105 84.28 75 60 45 30 12.04 15 3.68 2049 2050 2051 2052 0 0 Output Code (LSB) 0 2048 Code Occurrence (%) 90 C033 RMS noise = 1.3 LSBs Figure 132. Idle Channel Histogram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 41 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 7.19 Typical Characteristics: Common Plots Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 -10 -20 Amplitude (dBFS) -20 CMRR (dB) -40 -60 -80 -30 -40 -50 -100 -60 -70 -120 0 16 32 48 Frequency (MHz) 64 0 80 C401 fS = 160 MSPS, fCM = 10 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fCM ) = –98 dBFS, Amplitude (fIN – fCM ) = –91 dBFS 60 90 120 150 180 210 240 270 Common-Mode Test Signal Frequency (MHz) 300 C402 Input frequency = 30 MHz, 50-mVPP signal superimposed on VCM Figure 134. Common-Mode Rejection Ratio vs Test Signal Frequency Figure 133. Common-Mode Rejection Ratio FFT 0 0 -10 -20 Amplitude (dBFS) -20 PSRR (dB) -40 -60 -80 -30 -40 -50 -100 -60 -70 -120 0 16 32 48 Frequency (MHz) 64 0 80 C403 fS = 160 MSPS, fPSRR = 5 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fPSRR ) = –62 dBFS, Amplitude (fIN – fPSRR ) = –65.35 dBFS 60 90 120 150 180 210 240 270 Common-Mode Test Signal Frequency (MHz) 300 C404 Figure 136. Power-Supply Rejection Ratio vs Test Signal Frequency 1 1 AVDD_POWER DVDD_POWER TOTAL_POWER AVDD_POWER DVDD_POWER TOTAL_POWER 0.8 Power (mW) 0.8 Power (mW) 30 Input frequency = 30 MHz, 50-mVPP signal superimposed on VCM Figure 135. Power-Supply Rejection Ratio FFT for AVDD Supply 0.6 0.4 0.2 0.6 0.4 0.2 0 0 0 20 40 60 80 100 120 Sampling Speed (MSPS) 140 160 Figure 137. Power vs Sampling Frequency (20x Mode) 42 30 Submit Documentation Feedback C405 0 20 40 60 80 100 120 Sampling Speed (MSPS) 140 160 C406 Figure 138. Power vs Sampling Frequency (40x Mode) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 7.20 Typical Characteristics: Contour Plots Typical values are at TA = 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 160 84 Sampling Frequency, MSPS 87 140 81 90 78 75 69 72 84 120 87 90 100 81 84 78 75 72 75 72 69 80 60 87 90 81 84 50 100 78 150 200 250 Input Frequency, MHz 70 75 300 80 69 350 400 85 90 Figure 139. Spurious-Free Dynamic Range (SFDR) for 0-dB Gain Sampling Frequency, MSPS 160 85 88 140 79 82 76 73 120 100 82 85 88 79 76 80 60 85 88 50 70 100 72 74 82 85 150 200 250 Input Frequency, MHz 76 78 80 79 300 82 73 76 350 84 86 400 88 Figure 140. Spurious-Free Dynamic Range (SFDR) for 6-dB Gain Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 43 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Characteristics: Contour Plots (continued) Typical values are at TA = 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Sampling Frequency, MSPS 160 67 66 69.5 70 140 69 67.5 68 66.5 68.5 67 120 69.5 70 100 67.5 69 68 68.5 80 68.5 60 69.5 70 50 100 65.5 66 150 200 250 Input Frequency, MHz 66.5 67 67.5 67.5 68 69 68 300 68.5 350 69 400 69.5 70 Figure 141. Signal-to-Noise Ratio (SNR) for 0-dB Gain 160 63.7 Sampling Frequency, MSPS 65.8 140 66.1 64.9 65.5 64.6 65.2 64 64.3 120 100 65.2 65.8 66.1 64.9 65.5 80 60 66.1 50 63.5 100 64 65.2 65.5 65.8 150 200 250 Input Frequency, MHz 64.5 65 300 65.5 64.9 64.6 350 400 66 Figure 142. Signal-to-Noise Ratio (SNR) for 6-dB Gain 44 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 8 Parameter Measurement Information 8.1 Timing Diagrams N+3 N+2 Sample N N+4 N + Latency + 1 N + Latency N+1 N + Latency + 2 tA CLKP Input Clock CLKM ADC Latency (1) tD (2) DxP, DxM N - Latency-1 N + Latency N - Latency+1 N - Latency+2 (1) Overall latency = ADC latency + tD. (2) x = A for channel A and B for channel B. N - Latency+3 N N-1 N+1 N+1 Figure 143. ADC Latency CLKP Input Clock CLKM tSU_SYNC~ tH_SYNC~ SYNC~ tD SYNC~ Asserted Latency CGS Phase (1) DxP, DxM Data (1) Data Data Data Data Data Data Data Data K28.5 x = A for channel A, B for channel B, C for channel C, and D for channel D. Figure 144. SYNC~ Latency in CGS Phase (Two-Lane Mode) CLKP Input Clock CLKM tSU_SYNC~ tH_SYNC~ SYNC~ tD SYNC~ Deasserted Latency ILA Sequence (1) DxP, DxM K28.5 (1) K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.0 K28.0 x = A for channel A, B for channel B, C for channel C, and D for channel D. Figure 145. SYNC~ Latency in ILAS Phase (Two-Lane Mode) Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 45 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Timing Diagrams (continued) Sample N tSU_SYSREF tH_SYSREF Input Clock (CLKP - CLKM) SYSREF Figure 146. SYSREF Timing (Subclass 1) Sample N tSU_SYNC~ tH_SYNC~ Input Clock (CLKP - CLKM) SYNC~ Figure 147. SYNC~ Timing (Subclass 2) 46 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 9 Detailed Description 9.1 Overview The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-todigital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J2x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 12-bit data from each channel. The ADC34J2x devices support subclass 1 with interface data rates up to 3.2 Gbps. 9.2 Functional Block Diagram INAP, INAM 12-Bit ADC Digital Encoder and JESD204B INBP, INBM 12-Bit ADC Digital Encoder and JESD204B CLKP, CLKM Divide by 1,2,4 DAP, DAM OVRA DBP, DBM OVRB PLL x20 SYNCP, SYNCM SYSREFP, SYSREFM INCP, INCM 12-Bit ADC Digital Encoder and JESD204B INDP, INDM 12-Bit ADC Digital Encoder and JESD204B Copyright © 2014–2015, Texas Instruments Incorporated OVRC DDP, DDM OVRD SDOUT SDATA SCLK SEN Configuration Registers RESET Common Mode PDN VCM DCP, DCM Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 47 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 9.3 Feature Description 9.3.1 Analog Inputs The ADC34J2x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving 50-Ω termination between INP and INM). 9.3.2 Clock Input The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC34J2x can be driven by the transformercoupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer. 0.1 mF 0.1 mF Zo CLKP Differential Sine-Wave Clock Input CLKP RT Typical LVDS Clock Input 0.1 mF 100 W CLKM Device 0.1 mF Zo NOTE: RT = termination resistor, if necessary. CLKM Figure 148. Differential Sine-Wave Clock Driving Circuit Zo Device Figure 149. LVDS Clock Driving Circuit 0.1 mF CLKP 150 W Typical LVPECL Clock Input 100 W Zo 0.1 mF CLKM Device 150 W Figure 150. LVPECL Clock Driving Circuit 48 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Clock Buffer LPKG 2 nH 20 W CLKP CBOND 1 pF 5 kW RESR 100 W CEQ CEQ 1.4 V LPKG 2 nH 20 W 5 kW CLKM CBOND 1 pF RESR 100 W NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 151. Internal Clock Buffer A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 152. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM Device Figure 152. Single-Ended Clock Driving Circuit 9.3.2.1 SNR and Clock Jitter The signal-to-noise ratio of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter noise, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is 74 dBFS for a 12-bit ADC.. Thermal noise limits SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies. §  SNRQuantizatoin Noise 20 SNRADC[dBc] 20 ˜ log ¨10 ¨ © 2 · §  SNRThermal Noise ¸  ¨10 20 ¸ ¨ ¹ © 2 · §  SNRJitter ¸  ¨10 20 ¸ ¨ ¹ © · ¸ ¸ ¹ 2 (1) The SNR limitation resulting from sample clock jitter can be calculated with Equation 2: SNRJitter [dBc] 20 ˜ log( 2S ˜ f in ˜ TJitter ) (2) The total clock jitter (TJitter) has two components: the internal aperture jitter (200 fs for the device) which is set by the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3: TJitter (TJitter , Ext .Clock _ Input ) 2  (TAperture _ ADC ) 2 Copyright © 2014–2015, Texas Instruments Incorporated (3) Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 49 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The devices have a thermal noise of 73.5 dBFS and internal aperture jitter of 200 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 153. 71 Ext Clock Jitter 35 fs 50 fs 100 fs 150 fs 200 fs 70 SNR (dBFS) 69 68 67 66 65 64 10 100 Input Frequency (MHz) 1000 D001 D036 Figure 153. SNR vs Frequency vs Jitter 9.3.2.2 Input Clock Divider The devices are equipped with an internal divider on the clock input. The divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for operation with a 160-MHz clock while the divide-by-2 option supports a maximum input clock of 320 MHz and the divide-by-4 option supports a maximum input clock frequency of 640 MHz. 9.3.3 Power-Down Control The power-down functions of the ADC34J2x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see Figure 181, register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality. Table 3. Power-Down Modes 50 FUNCTION POWER CONSUMPTION (mW) WAKE-UP TIME (µs) Global power-down 5 85 Standby 185 35 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 9.3.4 Internal Dither Algorithm 0 0 ±20 ±20 Amplitude (dBFS) Amplitude (dBFS) The ADC34J2x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect of using dither algorithms. ±40 ±60 ±80 ±40 ±60 ±80 ±100 ±100 ±120 ±120 0 16 32 48 64 Frequency (MHz) fS = 160 MSPS fIN = 70 MHz 0 80 16 fS = 160 MSPS fIN = 70 MHz SNR = 69.7 dBFS SFDR = 86 dBc 32 48 64 Frequency (MHz) C003 80 C004 SNR = 69.9 dBFS SFDR = 86 dBc Figure 155. FFT with Dither Off Figure 154. FFT with Dither On 9.3.5 JESD204B Interface The ADC34J2x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial transmitter, as shown in Figure 156. The data of each ADC are serialized by 20x using an internal PLL and then transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. SYSREF SYNC JESD204B DA INA INB DB JESD 204B DC INC IND DD Sample Clock Figure 156. JESD204B Interface Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 51 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and determines if the ADC output data or test patterns are transmitted. The link layer performs the 8b or 10b data encoding and the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled. JESD204B Block Transport Layer Link Layer Frame Data Mapping 8b, 10b Encoding Scrambler 1+x14+x15 DA DB DC DD Comma Characters Initial Lane Alignment Test Patterns SYNC Figure 157. JESD204B Block 9.3.5.1 JESD204B Initial Lane Alignment (ILA) The initial lane alignment process is started by the receiving device by asserting the SYNC signal. When a logic high is detected on the SYNC input pins, the ADC34J2x starts transmitting comma (K28.5) characters to establish code group synchronization. When synchronization is complete, the receiving device de-asserts the SYNC signal and the ADC34J2x starts the initial lane alignment sequence with the next local multiframe clock boundary. The ADC34J2x transmits four multiframes, each containing K frames (K is SPI programmable). Each multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration data. 9.3.5.2 JESD204B Test Patterns There are three different test patterns available in the transport layer of the JESD204B interface. The ADC34J2x supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled via SPI register writes and are located in address 2Ah (bits 7:6). 9.3.5.3 JESD204B Frame Assembly The JESD204B standard defines the following parameters: • L is the number of lanes per link, • M is the number of converters per device, • F is the number of octets per frame clock period, and • S is the number of samples per frame. Table 4 lists the available JESD204B format and valid range for the ADC34J2x. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency. Table 4. LMFS Values and Interface Rate 52 L M F S MINIMUM ADC SAMPLING RATE (MSPS) 4 4 2 1 15 300 160 3.2 20x (default) 2 4 4 1 10 400 80 3.2 40x Submit Documentation Feedback MAXIMUM fSERDES (Mbps) MAXIMUM ADC SAMPLING RATE (Msps) MAXIMUM fSERDES (GSPS) MODE Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration can be changed from 20x (default) to 40x by setting the registers listed in Table 5. Figure 158. JESD Frame Assembly Table 5. Configuring 40x Mode ADDRESS DATA 2Bh 01h 30h 11h Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 53 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 9.3.5.4 Digital Outputs The ADC34J2x JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential 100-Ω load impedance and the termination resistors should be placed as close to the receiver inputs as possible to avoid unwanted reflections and signal distortion. Because the JESD204B employs 8b, 10b encoding, the output data stream is dc-balanced and ac-coupling can be used to avoid the need to match up common-mode voltages between the transmitter and receivers. The termination resistors should be connected to the termination voltage as shown in Figure 159. Vterm R t = ZO Transmission Line, Zo R t = ZO 0.1 PF DAP, DBP Receiver DAM, DBM 0.1 PF Figure 159. CML Output Connections Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 3.125 Gbps (156.25 MSPS, 20x mode), respectively. 300 Voltage (mV) 150 0 -150 -300 -200 -150 -100 -50 0 50 100 150 200 Time (ps) Figure 160. Eye Diagram: 3.125 Gbps 54 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 9.4 Device Functional Modes 9.4.1 Digital Gain The input full-scale amplitude can be selected between 1 VPP to 2 VPP (default is 2 VPP) by choosing the appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for SFDR performance. A larger input full-scale increases SNR performance (2 VPP is recommended for maximum SNR) while reduced input swing typically results in better SFDR performance. Table 6 lists the available digital gain settings. Table 6. Digital Gain vs Full-Scale Amplitude DIGITAL GAIN (dB) MAX INPUT VOLTAGE (VPP) 0 2.0 0.5 1.89 1 1.78 1.5 1.68 2 1.59 2.5 1.50 3 1.42 3.5 1.34 4 1.26 4.5 1.19 5 1.12 5.5 1.06 6 1.00 9.4.2 Overrange Indication The ADC34J2x provides two different overrange indications. The normal OVR (default) is triggered if the final 14bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRx pins (where x is A, B, C, or D). The fast OVR indication can be presented on the overrange pins instead by using the SPI register map. 9.5 Programming The ADS34Jxx can be configured using a serial programming interface, as described in this section. 9.5.1 Serial Interface The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 55 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Programming (continued) 9.5.1.1 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 161. If required, the serial interface registers can be cleared during operation either: 1. Through a hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 9.5.1.1.1 Serial Register Write The device internal register can be programmed with these steps: 1. Drive the SEN pin low, 2. Set the R/W bit to 0 (bit A15 of the 16-bit address), 3. Set bit A14 in the address field to 1, 4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and 5. Write the 8-bit data that are latched in on the SCLK rising edge. Figure 161 and Table 7 show the timing requirements for the serial register write operation. Register Address [13:0>] SDATA R/W 1 A13 A12 A11 A1 Register Data [7:0] A0 D7 D6 D5 D4 =0 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 161. Serial Register Write Timing Diagram Table 7. Serial Interface Timing (1) PARAMETER MIN TYP UNIT 20 MHz fSCLK SCLK frequency (equal to 1 / tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) 56 > dc MAX Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 9.5.1.1.2 Serial Register Readout The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. Given below is the procedure to read contents of serial registers: 1. Drive the SEN pin low. 2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. 3. Set bit A14 in the address field to 1. 4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read. 5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin. 6. The external controller can latch the contents at the SCLK rising edge. 7. To enable register writes, reset the R/W register bit to 0. When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 163. Register Data: GRQ¶WFDUH Register Address [13:0] SDATA R/W 1 A13 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 =1 Register Read Data [7:0] SDOUT D7 D6 D5 D4 D3 D2 SCLK SEN Figure 162. Serial Register Read Timing Diagram SCLK tSD_DELAY SDOUT Figure 163. SDOUT Timing Diagram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 57 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 9.5.2 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 164 and Table 8. Power Supplies t1 RESET t2 t3 SEN Figure 164. Initialization of Serial Registers after Power-Up Table 8. Power-Up Timing PARAMETER CONDITIONS t1 Power-on delay Delay from power up to active high RESET pulse t2 Reset pulse width Active high RESET pulse width t3 Register write delay Delay from RESET disable to SEN active MIN 1 10 TYP MAX UNIT ms 1000 100 ns ns If required, the serial interface registers can be cleared during operation either: 1. Through hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 9.5.3 Start-Up Sequence After power-up, the sequence described in Table 9 can be used to set up the ADC34J2x for basic operation. Table 9. Start-Up Settings STEP 58 DESCRIPTION REGISTER ADDRESS AND DATA 1 Bring up all supply voltages. There is no required power supply sequence for AVDD and DVDD 2 Pulse hardware reset (low to high to low) on pin 24 3 Optional configure LMFS of JESD204B interface to LMFS = 2441 (default is LMFS = 4421) 4 Pulse SYNC~ from high to low to transmit data from k28.5 sync mode Submit Documentation Feedback — — Address 2Bh, data 01h Address 30h, data 11h — Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 9.6 Register Map Table 10. Serial Register Map REGISTER ADDRESS A[13:0] (Hex) REGISTER DATA 7 01 6 5 DIS DITH CHA 4 3 DIS DITH CHB 2 1 DIS DITH CHC 0 DIS DITH CHD 02 0 0 0 0 0 0 CHA GAIN EN 0 03 0 0 0 0 0 0 CHB GAIN EN 0 04 0 0 0 0 0 0 CHC GAIN EN 0 05 0 0 0 0 0 0 CHD GAIN EN 0 SPECIAL MODE1 CHA TEST PATTERN EN RESET 06 0 0 0 07 0 0 0 SPECIAL MODE1 CHB EN FOVR 0 08 0 0 0 SPECIAL MODE1 CHC 0 0 SPECIAL MODE1 CHD ALIGN TEST PATTERN DATA FORMAT 09 0 0 0 0A CHA TEST PATTERN CHB TEST PATTERN 0B CHC TEST PATTERN CHD TEST PATTERN 0C CHA DIGITAL GAIN CHB DIGITAL GAIN 0D CHC DIGITAL GAIN CHD DIGITAL GAIN 0E CUSTOM PATTERN[11:4] 0F CUSTOM PATTERN [3:0] 0 0 0 0 13 LOW SPEED MODE 0 0 0 0 0 0 0 15 CHA PDN CHB PDN CHC PDN CHD PDN STANDBY GLOBAL PDN 0 PDN PIN DISABLE 0 0 0 0 0 0 IDLE SYNC TRP LAYER TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN TXMIT LINKDATA DIS 0 0 0 CTRL K CTRL F 0 0 0 0 0 0 0 27 2A CLK DIV SERDES TEST PATTERN 2B 0 0 0 2F SCR (SCR EN) 0 0 30 31 OCTETS PER FRAME 0 0 34 SUBCLASSV 3A SYNC REQ OPTION SYNC REG 3B 0 FRAMES PER MULTI FRAME 0 0 LINK LAYER TESTMODE SEL[2:0] 0 0 LINK LAYER RPAT 0 OUTPUT CURRENT SEL 0 PULSE DET MODES Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 59 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Register Map (continued) Table 10. Serial Register Map (continued) REGISTER ADDRESS 60 REGISTER DATA A[13:0] (Hex) 7 3C FORCE LMFC COUNT 6 5 4 3 2 122 0 0 0 0 0 0 134 0 0 DIS DITH CHA 0 DIS DITH CHA 0 222 0 0 0 0 0 0 234 0 0 DIS DITH CHD 0 DIS DITH CHD 0 422 0 0 0 0 0 0 434 0 0 DIS DITH CHB 0 DIS DITH CHB 0 522 0 0 0 0 0 0 534 0 0 DIS DITH CHC 0 DIS DITH CHC 0 1 LMFC COUNT INIT 0 LMFC COUNT INIT Submit Documentation Feedback SPECIAL MODE2 CHA [1:0] 0 0 SPECIAL MODE2 CHD [1:0] 0 0 SPECIAL MODE2 CHB [1:0] 0 0 SPECIAL MODE2 CHC [1:0] 0 0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 9.6.1 Serial Register Description Figure 165. Register 01h 7 6 5 DIS DITH CHA 4 3 DIS DITH CHB 2 1 DIS DITH CHC 0 DIS DITH CHD Table 11. Register 01h Description Name Description Bits 7:6 DIS DITH CHA 00 = Default 11 = Dither is disabled, high SNR mode is selected for channel A. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 134 (bits 5 and 3) are also set to 11. Bits 5:4 DIS DITH CHB 00 = Default 11 = Dither is disabled, high SNR mode is selected for channel B. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 434 (bits 5 and 3) are also set to 11. Bits 3:2 DIS DITH CHC 00 = Default 11 = Dither is disabled, high SNR mode is selected for channel C. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 534 (bits 5 and 3) are also set to 11. Bits 1:0 DIS DITH CHD 00 = Default 11 = Dither is disabled, high SNR mode is selected for channel D. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 234 (bits 5 and 3) are also set to 11. Figure 166. Register 02h 7 0 6 0 5 0 4 0 3 0 2 0 1 CHA GAIN EN 0 0 Table 12. Register 02h Description Name Description Bits 7:2 Must write 0 Bit 1 CHA GAIN EN Enable digital gain control for channel A. 0 = Default 1 = Digital gain for channel A can be programmed with the CHA DIGITAL GAIN bits. Bit 0 Must write 0 Figure 167. Register 03h 7 0 6 0 5 0 4 0 3 0 2 0 1 CHB GAIN EN 0 0 Table 13. Register 03h Description Name Description Bits 7:2 Must be 0 Bit 1 CHB GAIN EN: Enable digital gain control for channel B. 0 = Default 1 = Digital gain for channel B can be programmed with the CHB DIGITAL GAIN bits. Bit 0 Must write 0 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 61 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 168. Register 04h 7 0 6 0 5 0 4 0 3 0 2 0 1 CHC GAIN EN 0 0 Table 14. Register 04h Description Name Description Bits 7:2 Must write 0 Bit 1 CHC GAIN EN Enable digital gain control for channel C. 0 = Default 1 = Digital gain for channel C can be programmed with the CHC DIGITAL GAIN bits. Bit 0 Must write 0 Figure 169. Register 05h 7 0 6 0 5 0 4 0 3 0 2 0 1 CHD GAIN EN 0 0 Table 15. Register 05h Description Name Description Bits 7:2 Must write 0 Bit 1 CHD GAIN EN: Enable digital gain control for channel D 0 = Default 1 = Digital gain for channel D can be programmed with the CHD DIGITAL GAIN bits. Bit 0 Must write 0 Figure 170. Register 06h 7 6 5 0 0 0 4 3 2 SPECIAL MODE1 CHA 1 TEST PATTERN EN 0 RESET Table 16. Register 06h Description Name Description Bits 7:5 Must write 0 Bits 4:2 SPECIAL MODE1 CHA 010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz Bit 1 TEST PATTERN EN This bit enables test pattern selection for the digital outputs. 0 = Normal operation 1 = Test pattern output enabled Bit 0 RESET: Software reset applied This bit resets all internal registers to the default values and self-clears to 0. 62 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Figure 171. Register 07h 7 0 6 0 5 0 4 3 SPECIAL MODE1 CHB 2 1 EN FOVR 0 0 2 1 0 0 0 Table 17. Register 07h Description Name Description Bits 7:5 Must write 0 Bits 4:2 SPECIAL MODE1 CHB 010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz Bit 1 EN FOVR 0 = Normal OVR on OVRx pins 1 = Enable fast OVR on OVRx pins Bit 0 Must write 0 Figure 172. Register 08h 7 0 6 0 5 0 4 3 SPECIAL MODE1 CHC Table 18. Register 08h Description Name Description Bits 7:5 Must write 0 Bits 4:2 SPECIAL MODE1 CHC 010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz Bits 1:0 Must write 0 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 63 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 173. Register 09h 7 6 5 0 0 0 4 3 2 SPECIAL MODE1 CHD 1 ALIGN TEST PATTERN 0 DATA FORMAT Table 19. Register 09h Description Name Description Bits 7:5 Must write 0 Bits 4:2 SPECIAL MODE1 CHD 010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz Bit 1 ALIGN TEST PATTERN This bit aligns test patterns across the outputs of four channels. 0 = Test patterns of four channels are free running. 1 = Test patterns of four channels are aligned. Bit 0 DATA FORMAT: Digital output data format 0 = Twos complement 1 = Offset binary Figure 174. Register 0Ah 7 6 5 CHA TEST PATTERN 4 3 2 1 CHB TEST PATTERN 0 Table 20. Register 0Ah Description Name Description Bits 7:4 CHA TEST PATTERN These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use Bits 3:0 CHB TEST PATTERN These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use 64 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Figure 175. Register 0Bh 7 6 5 CHC TEST PATTERN 4 3 2 1 CHD TEST PATTERN 0 Table 21. Register 0Bh Description Name Bits 7:4 Description CHC TEST PATTERN These bits control the test pattern for channel C after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use Bits 3:0 CHD TEST PATTERN These bits control the test pattern for channel D after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 65 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 176. Register 0Ch 7 6 5 CHA TEST PATTERN 4 3 2 1 CHB TEST PATTERN 0 Table 22. Register 0Ch Description Name Description Bits 7:4 CHA TEST PATTERN In address 0Ch, these bits control the test pattern for channel A after the CHA GAIN EN bit is set. See Table 23 for register settings. Bits 3:0 CHB TEST PATTERN In address 0Ch, these bits control the test pattern for channel B after the CHB GAIN EN bit is set. See Table 23 for register settings. Table 23. Channel Digital Gain REGISTER VALUE DIGITAL GAIN (dB) 0000 0 MAXIMUM INPUT VOLTAGE (VPP) 2.0 0001 0.5 1.89 0010 1 1.78 0011 1.5 1.68 0100 2 1.59 0101 2.5 1.50 0110 3 1.42 0111 3.5 1.34 1000 4 1.26 1001 4.5 1.19 1010 5 1.12 1011 5.5 1.06 1100 6 1.00 Figure 177. Register 0Dh 7 6 5 CHC TEST PATTERN 4 3 2 1 CHD TEST PATTERN 0 Table 24. Register 0Dh Description Name Description Bits 7:4 CHC TEST PATTERN In address 0Dh, these bits control the test pattern for channel C after the CHC GAIN EN bit is set. See Table 23 for register settings. Bits 3:0 CHD TEST PATTERN In address 0Dh, these bits control the test pattern for channel D after the CHD GAIN EN bit is set. See Table 23 for register settings. Figure 178. Register 0Eh 7 6 5 4 3 CUSTOM PATTERN[11:4] 2 1 0 Table 25. Register 0Eh Description Name Description Bits 7:0 CUSTOM PATTERN[11:4] These bits set the 14-bit custom pattern (11:4) for all channels. 66 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Figure 179. Register 0Fh 7 6 5 CUSTOM PATTERN[3:0] 4 3 0 2 0 1 0 0 0 1 0 0 0 Table 26. Register 0Fh Description Name Description Bits 7:2 CUSTOM PATTERN[3:0] These bits set the 14-bit custom pattern (3:0) for all channels. Bits 3:0 Must write 0 Figure 180. Register 13h 7 LOW SPEED MODE 6 0 5 0 4 0 3 0 2 0 Table 27. Register 13h Description Name Bit 7 Description LOW SPEED MODE Use this bit for sampling frequencies < 25 MSPS. 0 = Normal operation 1 = Low-speed mode enabled Bits 6:0 Must write 0 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 67 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 181. Register 15h 7 6 5 4 3 2 1 CHA PDN CHB PDN CHC PDN CHD PDN STANDBY GLOBAL PDN 0 0 CONFIG PDN PIN Table 28. Register 15h Description Name Description Bit 7 CHA PDN: Power-down channel A 0 = Normal operation 1 = Power-down channel A Bit 6 CHB PDN: Power-down channel B 0 = Normal operation 1 = Power-down channel B Bit 5 CHC PDN: Power-down channel C 0 = Normal operation 1 = Power-down channel C Bit 4 CHD PDN: Power-down channel D 0 = Normal operation 1 = Power-down channel D Bit 3 STANDBY This bit places the ADCs of all four channels into standby. 0 = Normal operation 1 = Standby Bit 2 GLOBAL PDN Places device in global power down. 0 = Normal operation 1 = Global power-down Bit 1 Must write 0 Bit 0 CONFIG PDN PIN This bit configures the PDN pin as either global power-down or standby pin. 0 = Logic high voltage on the PDN pin sends places the into global power-down. 1 = Logic high voltage on the PDN pin places the device into standby. Figure 182. Register 27h 7 6 5 0 CLK DIV 4 0 3 0 2 0 1 0 0 0 Table 29. Register 27h Description Name Description Bits 7:6 CLK DIV: Internal clock divider for the input sampling clock 00 01 10 11 Bits 5:0 68 = Clock divider bypassed = Divide-by-1 = Divide-by-2 = Divide-by-4 Must write 0 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Figure 183. Register 2Ah 7 6 SERDES TEST PATTERN 5 4 3 2 1 IDLE SYNC TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN 0 TX LINK CONFIG DATA DIS Table 30. Register 2Ah Description Name Description Bits 7:6 SERDES TEST PATTERN: These bits set the test patterns in the transport layer of the JESD204B interface. 00 = Normal operation 01 = Outputs clock pattern (output is 10101010) 10 = Encoded pattern (output is 1111111100000000) 11 = Output is 215 – 1 Bit 5 IDLE SYNC This bit generates the long transport layer test pattern mode according to 5.1.6.3 clause of JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled Bit 4 TESTMODE EN This bit sets the output pattern when SYNC is high. 0 = Sync code is k28.5 (0xBCBC) 1 = Sync code is 0xBC50 Bit 3 FLIP ADC DATA This bit sets the output pattern when SYNC is high. 0 = Normal operation 1 = Output data order is reversed: MSB – LSB Bit 2 LANE ALIGN This bit inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts lane alignment characters Bit 1 FRAME ALIGN This bit inserts a frame alignment character (K28.7) for the receiver to align to the frame boundary per section 5.3.3.4 of the JESD204B specification. 0 = Normal operation 1 = Inserts frame alignment characters Bit 0 TX LINK CONFIG DATA DIS This bit disables the initial link alignment (ILA) sequence when SYNC is de-asserted. 0 = Normal operation 1 = ILA disabled Figure 184. Register 2Bh 7 0 6 0 5 0 4 0 3 0 2 0 1 CTRL K 0 CTRL F Table 31. Register 2Bh Description Name Description Bits 7:2 Must write 0 Bit 1 CTRL K: Enable bit for number of frames per multiframe 0 = Default is 9 frames (20x mode) per multiframe 1 = Frames per multiframe can be set in register 31h Bit 0 CTRL F: Enable bit for number of octets per frame 0 = 20x mode using one lane per ADC (default is F = 2) 1 = Octets per frame can be specified in register 30h Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 69 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 185. Register 2Fh 7 SCRAMBLE EN 6 5 4 3 2 1 0 0 0 0 0 0 0 0 2 1 0 2 1 FRAMES PER MULTI FRAME 0 Table 32. Register 2Fh Description Name Description Bit 7 SCRAMBLE EN This bit scrambles the enable bit in the JESD204B interface. 0 = Scrambling disabled 1 = Scrambling enabled Bits 6:0 Must write 0 Figure 186. Register 30h 7 6 5 4 3 OCTETS PER FRAME Table 33. Register 30h Description Name Description Bits 7:0 OCTETS PER FRAME These bits set the number of octets per frame (F). 01 = 20x serialization: two octets per frame 11 = 40x serialization: four octets per frame Figure 187. Register 31h 7 0 6 0 5 0 4 3 Table 34. Register 31h Description Name Description Bits 7:5 Must write 0 Bits 4:0 FRAMES PER MULT IFRAME These bits set the number of frames per multiframe. After reset, the default settings for frames per multiframe are: 20x mode: K = 8 (for each mode, K should not be set to a lower value). Figure 188. Register 34h 7 6 SUBCLASS 5 4 0 3 0 2 0 1 0 0 0 Table 35. Register 34h Description Name Description Bits 7:5 SUBCLASS These bits set the JESD204B subclass. 000 = Subclass 0 (backward compatibility with JESD204A) 001 = Subclass 1 (deterministic latency using SYSREF signal) 010 = Subclass 2 (deterministic latency using SYNC detection) Bits 4:0 70 Must write 0 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Figure 189. Register 3Ah 7 SYNC REQ 6 SYNC REQ EN 5 0 4 0 3 2 1 OUTPUT CURRENT SEL 0 Table 36. Register 3Ah Description Name Description Bit 7 SYNC REQ This bit generates a synchronization request only when the SYNC REQ EN register bit is set. 0 = Normal operation 1 = Generates sync request Bit 6 SYNC REQ EN 0 = Sync request is made with the SYNCP~, SYNCM~ pins 1 = Sync request is made with the SYNC REQ register bit Bits 5:4 Must write 0 Bits 3:0 OUTPUT CURRENT SEL: JESD output buffer current selection Program current (mA) 000 =16 001 = 12 010 = 8 011 = 4 100 = 32 101 = 28 110 = 24 111 = 20 Figure 190. Register 3Bh 7 6 5 4 LINK LAYER RPAT LINK LAYER TESTMODE 3 2 1 0 0 PULSE DET MODES Table 37. Register 3Bh Description Name Description Bits 7:5 LINK LAYER TESTMODE These bits generate a pattern according to clause 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high frequency jitter pattern) 010 = K28.5 (mixed frequency jitter pattern) 011 = Repeat initial lane alignment (generates K28.5 character and repeat lane alignment sequences continuously) 100 = 12 octet RPAT jitter pattern Bit 4 LINK LAYER RPAT This bit changes the running disparity in the modified RPAT pattern test mode (only when link layer test mode = 100). 0 = normal operation 1 = changes disparity Bit 3 Must write 0 Bits 2:0 PULSE DET MODES These bits select different detection modes for SYSREF (subclass 1) and SYNC (subclass2). Table 38. PULSE DET MODES Register Settings D2 D1 D0 0 Don’t care 0 Allow all pulses to reset input clock dividers 1 Don’t care 0 Do not allow reset of analog clock dividers Don’t care 0 to 1 transition 1 Allow one pulse immediately after the 0 to1 transition to reset the divider Copyright © 2014–2015, Texas Instruments Incorporated FUNCTIONALITY Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 71 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 191. Register 3Ch 7 FORCE LMFC COUNT 6 5 4 3 2 LMFC COUNT INIT 1 0 RELEASE ILANE SEQ Table 39. Register 3Ch Description Name Description Bit 7 FORCE LMFC COUNT: Force LMFC count 0 = Normal operation 1 = Enables using different starting values for the LMFC counter Bits 6:2 LMFC COUNT INIT If SYSREF is transmitted to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx receives the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled. Bits 1:0 RELEASE ILANE SEQ These bits delay the lane alignment sequence generation by 0, 1, 2, or 3 multiframes after the code group synchronization. 00 = 0 01 = 1 10 = 2 11 = 3 Figure 192. Register 122h 7 0 6 0 5 0 4 0 3 0 2 0 1 0 SPECIAL MODE2 CHA [1:0] Table 40. Register 122h Description Name Description Bits 7:2 Must write 0 Bit 1:0 SPECIAL MODE2 CHA [1:0] Always write '11' for better HD2 performance. Figure 193. Register 134h 7 0 6 0 5 DIS DITH CHA 4 0 3 DIS DITH CHA 2 0 1 0 0 0 Table 41. Register 134h Description Name Description Bits 7:6 Must write 0 Bit 5 DIS DITH CHA 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 7:6) are also set to 11. Bit 4 Must write 0 Bit 3 DIS DITH CHA 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 7:6) are also set to 11. Bits 2:0 72 Must write 0 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Figure 194. Register 222h 7 0 6 0 5 0 4 0 3 0 2 0 1 0 SPECIAL MODE 2 CHD [1:0] Table 42. Register 222h Description Name Description Bits 7:2 Must write 0 Bit 1:0 SPECIAL MODE 2 CHD [1:0] Always write '11' for better HD2 performance. Figure 195. Register 234h 7 0 6 0 5 DIS DITH CHD 4 0 3 DIS DITH CHD 2 0 1 0 0 0 Table 43. Register 234h Description Name Description Bits 7:6 Must write 0 Bit 5 DIS DITH CHD 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel D. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 1:0) are also set to 11. Bit 4 Must write 0 Bit 3 DIS DITH CHD 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel D. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 1:0) are also set to 11. Bits 2:0 Must write 0 Figure 196. Register 422h 7 0 6 0 5 0 4 0 3 0 2 0 1 0 SPECIAL MODE 2 CHB [1:0] Table 44. Register 422h Description Name Description Bits 7:2 Must write 0 Bit 1:0 SPECIAL MODE 2 CHB [1:0] Always write '11' for better HD2 performance. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 73 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Figure 197. Register 434h 7 0 6 0 5 DIS DITH CHB 4 0 3 DIS DITH CHB 2 0 1 0 0 0 Table 45. Register 434h Description Name Description Bits 7:6 Must write 0 Bit 5 DIS DITH CHB 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 5:4) are also set to 11. Bit 4 Must write 0 Bit 3 DIS DITH CHB 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 5:4) are also set to 11. Bits 2:0 Must write 0 Figure 198. Register 522h 7 0 6 0 5 0 4 0 3 0 2 0 1 0 SPECIAL MODE 2 CHC [1:0] Table 46. Register 522h Description Name Description Bits 7:2 Must write 0 Bit 1:0 SPECIAL MODE 2 CHC [1:0] Always write '11' for better HD2 performance. Figure 199. Register 534h 7 0 6 0 5 DIS DITH CHC 4 0 3 DIS DITH CHC 2 0 1 0 0 0 Table 47. Register 534h Description Name Description Bits 7:6 Must write 0 Bit 5 DIS DITH CHC 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel C. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11. Bit 4 Must write 0 Bit 3 DIS DITH CHC 00 = Default 11 = Dither is disabled and high SNR mode is selected for channel C. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11. Bits 2:0 74 Must write 0 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 10 Application and Implementation 10.1 Application Information Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 200 and Figure 201 show the impedance (Zin = Rin || Cin) across the ADC input pins. 6 Differential Capacitance, Cin (pF) Differential Resistance, Rin (kOhm) 10 1 0.1 5 4 3 2 1 0.01 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 0 100 200 300 D024 Figure 200. Differential Input Resistance, RIN 400 500 600 700 Frequency (MHz) 800 900 1000 D025 Figure 201. Differential Input Capacitance, CIN 10.2 Typical Applications 10.2.1 Driving Circuit Design: Low Input Frequencies 39 nH 0.1uF INP 0.1uF 50 Ÿ 0.1uF 25 Ÿ 50 Ÿ 22 pF 25 Ÿ 50 Ÿ 50 Ÿ INM 1:1 1:1 0.1uF 39 nH VCM Device Figure 202. Driving Circuit for Low Input Frequencies 10.2.1.1 Design Requirements For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source. 10.2.1.2 Detailed Design Procedure A typical application using two back-to-back coupled transformers is illustrated in Figure 202. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the series inductor (39 nH), this combination helps absorb the sampling glitches. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 75 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Applications (continued) 10.2.1.3 Application Curve Figure 203 shows the performance obtained by using the circuit shown in Figure 202. 0 Amplitude (dBFS) ±20 ±40 ±60 ±80 ±100 ±120 0 16 32 48 Frequency (MHz fS = 160 MSPS fIN = 10 MHz 64 80 C001 SNR = 70.3 dBFS SFDR = 84 dBc Figure 203. Performance FFT at 10 MHz (Low Input Frequency) 76 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 Typical Applications (continued) 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz 0.1 PF 10 Ÿ INP 0.1 PF 0.1 PF 15 Ÿ 25 Ÿ 56 nH 10 pF 25 Ÿ 15 Ÿ INM 1:1 1:1 10 Ÿ 0.1 PF VCM Device Figure 204. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz) 10.2.2.1 Design Requirements See the Design Requirements section for further details. 10.2.2.2 Detailed Design Procedure When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 204. 10.2.2.3 Application Curve Figure 205 shows the performance obtained by using the circuit shown in Figure 204. 0 Amplitude (dBFS) ±20 ±40 ±60 ±80 ±100 ±120 0 16 32 48 Frequency (MHz) fS = 160 MSPS fIN = 170 MHz 64 80 C005 SNR = 67.9 dBFS SFDR = 84.1 dBc Figure 205. Performance FFT at 170 MHz (Mid Input Frequency) Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 77 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com Typical Applications (continued) 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz 0.1uF 10 Ÿ 0.1uF INP 0.1uF 25 Ÿ 25 Ÿ INM 1:1 1:1 10 Ÿ 0.1uF VCM Device Figure 206. Driving Circuit for High Input Frequencies (fIN > 230 MHz) 10.2.3.1 Design Requirements See the Design Requirements section for further details. 10.2.3.2 Detailed Design Procedure For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 206. 10.2.3.3 Application Curve Figure 207 shows the performance obtained by using the circuit shown in Figure 206. 0 Amplitude (dBFS) ±20 ±40 ±60 ±80 ±100 ±120 0 16 32 48 Frequency (MHz) fS = 160 MSPS fIN = 450 MHz 64 80 C009 SNR = 63.1 dBFS SFDR = 73 dBc Figure 207. Performance FFT at 450 MHz (High Input Frequency) 11 Power-Supply Recommendations The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply requirements during device power-up. AVDD and DVDD can power up in any order. 78 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 ADC34J22, ADC34J23, ADC34J24, ADC34J25 www.ti.com SBAS669A – MAY 2014 – REVISED JANUARY 2015 12 Layout 12.1 Layout Guidelines The ADC34J2x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 208. Some important points to remember while laying out the board are: 1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs should exit the pin out in opposite directions, as shown in the reference layout of Figure 208 as much as possible. 2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 208 as much as possible. 3. Digital outputs should be kept away from the analog inputs. When these digital outputs exit the pin out, the digital output traces should not be kept parallel to the analog input traces because this configuration may result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] should be matched in length to avoid skew among outputs. 4. At each power-supply pin (AVDD and DVDD), a 0.1-µF decoupling capacitor should be kept close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1µF capacitors can be kept close to the supply source. 12.2 Layout Example Analog Input Routing ADC3xJxx Sampling Clock Routing Digital Output Routing Clock Distribution IC Figure 208. Typical Layout of the ADC34J2x Board Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 79 ADC34J22, ADC34J23, ADC34J24, ADC34J25 SBAS669A – MAY 2014 – REVISED JANUARY 2015 www.ti.com 13 Device and Documentation Support 13.1 Related Links Table 48 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 48. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADC34J22 Click here Click here Click here Click here Click here ADC34J23 Click here Click here Click here Click here Click here ADC34J24 Click here Click here Click here Click here Click here ADC34J25 Click here Click here Click here Click here Click here 13.2 Trademarks PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 80 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25 PACKAGE OPTION ADDENDUM www.ti.com 20-Jan-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC34J22IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J22 ADC34J22IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J22 ADC34J23IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J23 ADC34J23IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J23 ADC34J24IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J24 ADC34J24IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J24 ADC34J25IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J25 ADC34J25IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ34J25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 20-Jan-2017 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Feb-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC34J22IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J22IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J23IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J23IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J24IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J24IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J25IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADC34J25IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Feb-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC34J22IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC34J22IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC34J23IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC34J23IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC34J24IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC34J24IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 ADC34J25IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADC34J25IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. 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