ADC7802

® ADC7802 Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES q TOTAL UNADJUSTED ERROR ≤ 1/2LSB OVER FULL TEMPERATURE RANGE q FOUR-CHANNEL INPUT MULTIPLEXER q LOW POWER: 10mW plus Power Down Mode q SINGLE SUPPLY: +5V q FAST CONVERSION TIME: 8.5µs Including Acquisition q AUTOCAL: No Offset or Gain Adjust Required q UNIPOLAR INPUTS: 0V to 5V q MICROPROCESSOR-COMPATIBLE INTERFACE q INTERNAL SAMPLE/HOLD DESCRIPTION The ADC7802 is a monolithic CMOS 12-bit A/D converter with internal sample/hold and four-channel multiplexer. An autocalibration cycle, occurring automatically at power on, guarantees a total unadjusted error within ±1/2LSB over the specified temperature range, eliminating the need for offset or gain adjustment. The 5V single-supply requirements and standard CS, RD, and WR control signals make the part very easy to use in microprocessor applications. Conversion results are available in two bytes through an 8bit three-state output bus. The ADC7802 is available in a 28-pin plastic DIP and 28-lead PLCC, fully specified for operation over the industrial –40°C to +85°C temperature range. A0 A1 Address Latch and Decoder Calibration Microcontroller and Memory Clock Control Logic CS RD WR SFR AIN0 AIN1 AIN2 AIN3 Analog Multiplexer BUSY Capacitor Array Sampling ADC Three-State Input/Output 8-Bit Data Bus VREF + VREF – International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1990 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1050B Printed in U.S.A. June, 1993 SPECIFICATIONS ELECTRICAL At VA = VD = VREF+ = 5V ±5%; VA ≥ VD ≥ VREF+; VREF– = AGND = DGND = 0V; CLK = 2MHz external with 50% duty cycle, TA = – 40°C to +85°C, after calibration cycle at any temperature, unless otherwise specified. ADC7802BP, ADC7802BN PARAMETER RESOLUTION ANALOG INPUT Voltage Input Range Input Capacitance On State Bias Current Off State Bias Current On Resistance Multiplexer Off Resistance Multiplexer Channel Separation REFERENCE INPUT For Specified Performance: VREF+ VREF– For Derated Performance: (1) VREF+ VREF– Input Reference Current THROUGHPUT TIMING Conversion Time With External Clock (Including Multiplexer Settling Time and Acquisition Time) With Internal Clock Using Recommended Clock Components Analog Signal Bandwidth (2) Slew Rate (2) Multiplexer Settling Time to 0.01% Multiplexer Access Time ACCURACY Total Adjusted Error,(3) All Channels Differential Nonlinearity No Missing Codes Gain Error Gain Error Drift Offset Error Offset Error Drift Channel-to-Channel Mismatch Power Supply Sensitivity DIGITAL INPUTS All Pins Other Than CLK: VIL VIH Input Current CLK Input: VIL VIH IIL IIH IIH DIGITAL OUTPUTS VOL VOH Leakage Current Output Capacitance POWER SUPPLIES Supply Voltage for Specified Performance: VA VD Supply Current: IA ID Power Dissipation Power Down Mode TEMPERATURE RANGE Specification Storage VREF+ = 5V, VREF– = 0V TA = 25°C TA = – 40°C to +85°C 2 10 92 5 0 4.5 0 VREF+ = 5V, VREF– = 0V CLK = 2MHz, 50% Duty Cycle CLK = 1MHz, 50% Duty Cycle CLK = 500kHz, 50% Duty Cycle TA = +25°C TA = – 40°C to +85°C 8 460 20 ±1/2 ±1/2 Guaranteed All Channels Between Calibration Cycles All Channels Between Calibration Cycles VA = V D = 4.75V to 5.25V ±0.2 ±0.2 ±1/8 ±1/4 ±1/4 ±1/4 LSB ppm/°C LSB ppm/°C LSB LSB V V µA µA V V µA mA nA V V µA pF V V mA mA mW µW °C °C 10 VA 1 100 8.5 17 34 10 10 500 0 50 100 10 100 CONDITIONS MIN TYP MAX 12 5 UNITS Bits V pF nA nA nA kΩ MΩ dB V V V V µA µs µs µs µs µs Hz mV/µs ns ns LSB LSB 500Hz VREF+ ≤ VA 0.8 2.4 TA = +25°C, VIN = 0 to VD TA = – 40°C to +85°C, VIN = 0 to VD 3.5 10 1.5 100 0.4 4 4 4.75 4.75 5 5 1 1 10 50 ±1 15 5.25 5.25 2.5 2 1 10 0.8 Power Down Mode (D3 in SFR HIGH) ISINK = 1.6mA ISOURCE = 200µA High-Z State, VOUT = 0V to VD High-Z State VA ≥ VD Logic Input Pins HIGH or LOW WR = RD = CS = BUSY = HIGH See Table III, Page 9 –40 –65 +85 +150 NOTES: (1) For (VREF+) – (VREF–) as low as 4.5V, the total error will typically not exceed ±1LSB. (2) Faster signals can be accurately converted by using an external sample/hold in front of the ADC7802. (3) After calibration cycle, without external adjustment. Includes gain (full scale) error, offset error, integral nonlinearity, differential nonlinearity, and drift. ® ADC7802 2 ABSOLUTE MAXIMUM RATINGS VA to Analog Ground ........................................................................... 6.5V VD to Digital Ground ............................................................................ 6.5V Pin VA to Pin VD ................................................................................ ±0.3V Analog Ground to Digital Ground ......................................................... ±1V Control Inputs to Digital Ground ................................... –0.3V to VD + 0.3V Analog Input Voltage to Analog Ground ...................... –0.3V to VD + 0.3V Maximum Junction Temperature ..................................................... 150°C Internal Power Dissipation ............................................................. 875mW Lead Temperature (soldering, 10s) ................................................ +300°C Thermal Resistance, θJA : Plastic DIP ............................................. 75°C/W PLCC ..................................................... 75°C/W PACKAGE INFORMATION MODEL ADC7802BN ADC7802BP PACKAGE 28-Pin PLCC 28-Pin Plastic DIP PACKAGE DRAWING NUMBER(1) 251 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MAXIMUM TOTAL ERROR, LSB ±1/2 ±1/2 SPECIFICATION TEMPERATURE RANGE, °C –40 to +85 –40 to +85 MODEL ADC7802BN ADC7802BP PACKAGE PLCC Plastic DIP The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADC7802 PIN CONFIGURATIONS Top View SFR AIN0 AIN1 AIN2 AIN3 VREF+ VREF– DGND VD D7 D6 D5 D4 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VA AGND CAL A1 25 A1 A0 CLK BUSY HBE WR CS DIP Top View LCC AGND 27 AIN2 AIN1 AIN0 SFR 4 3 2 1 28 26 A0 CLK BUSY HBE WR CS RD D0 D1 D2 AIN3 V REF + V REF – DGND VD D7 D6 5 24 6 23 7 22 8 21 9 20 10 19 11 12 13 14 15 16 17 18 PIN ASSIGNMENTS PIN # 1 2 to 5 6 7 8 9 10 to 17 NAME SFR AIN0 to AIN3 VREF+ VREF– DGND VD D0 to D7 DESCRIPTION Special Function Register. When connected to a microprocessor address pin, allows access to special functions through D0 to D7. See the sections discussing the Special Function Register. If not used, connect to DGND. This pin has an internal pull-down. Analog inputs. Channel 0 to channel 3. Positive voltage reference input. Normally +5V. Must be ≤ VA. Negative voltage reference input. Normally 0V. Digital ground. DGND = 0V. Logic supply voltage. VD = +5V. Must be ≤ VA and applied after VA. Data Bus Input/Output Pins. Normally used to read output data. See section on SFR (Special Function Register) for other uses. When SFR is LOW, these function as follows: Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration, goes LOW after the conversion is completed. (Acts as an inverted BUSY.) Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. Data Bit 5 if HBE is LOW; LOW if HBE is HIGH. Data Bit 4 if HBE is LOW; LOW if HBE is HIGH. Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH. Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH. Read Input. Active LOW; used to read the data outputs in combination with CS and HBE. Chip Select Input. Active LOW. Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1 in combination with CS. The minimum WR pulse LOW width is 100ns. High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR. BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed. Clock Input. For internal/external clock operation. For external clock operation, connect pin 23 to a 74 HC-compatible clock source. For internal clock operation, connect pin 23 per the clock operation description. Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs are latched on the rising edge of WR or CS. A1 A0 Selected Channel LOW LOW AIN0 LOW HIGH AIN1 HIGH LOW AIN2 HIGH HIGH AIN3 Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not used, connect to VD. In this case calibration is only initiated at power on, or with SFR. This pin has an internal pull-up. Analog Ground. AGND = 0V. Analog Supply. VA = +5V. Must be ≥ VD and VREF+. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 to 25 D7 D6 D5 D4 D3 D2 D1 D0 RD CS WR HBE BUSY CLK A0 to A1 26 27 28 CAL AGND VA ® ADC7802 4 RD D5 D4 D3 D1 D2 D0 CAL VA TYPICAL PERFORMANCE CURVES At VA = VD = VREF+ = 5V, VREF– = AGND = 0V, TA = +25°C, unless otherwise specified. CHANNEL SEPARATION vs FREQUENCY Conversions Yielding Expected Code (%) CODE TRANSITION NOISE 100 100 Channel Separation (dB) 80 Channel AIN3 Channel AIN1 Channel AIN0 75 60 50 40 20 25 0 1 10 100 1000 Frequency of 5Vp-p Signal on Channel AIN2 (kHz) 0 0 0.25 0.5 0.75 1 Analog Input Voltage – Expected Code Center (LSBs) SIGNAL/(NOISE + DISTORTION) vs INPUT FREQUENCY 75 POWER SUPPLY REJECTION vs FREQUENCY 10 Full-Scale Error vs Change in Supply Voltage (mV/V) Signal/(Noise + Distortion) (dB) 6 4 2 VA 1 0.6 0.4 0.2 0.1 VD 50 25 0 0.1 0.2 0.4 0.6 1 2 4 6 10 Input Frequency (kHz) 0.1 1 10 Frequency (kHz) 100 1000 INTERNAL CLOCK FREQUENCY vs TEMPERATURE 1.15 10 INTERNAL CLOCK FREQUENCY vs RCLOCK Clock Frequency (MHz) RCLOCK = 70kΩ 1.05 Clock Frequency (MHz) 1.1 1 1 0.95 0.9 –50 –25 0 25 50 75 100 Ambient Temperature (°C) 0.1 10 100 RCLOCK (kΩ) 1k ® 5 ADC7802 THEORY OF OPERATION ADC7802 uses the advantages of advanced CMOS technology (logic density, stable capacitors, precision analog switches, and low power consumption) to provide a precise 12-bit analog-to-digital converter with on-chip sampling and four-channel analog-input multiplexer. The input stage consists of an analog multiplexer with an address latch to select from four input channels. The converter stage consists of an advanced successive approximation architecture using charge redistribution on a capacitor network to digitize the input signal. A temperaturestabilized differential auto-zeroing circuit is used to minimize offset errors in the comparator. This allows offset errors to be corrected during the acquisition phase of each conversion cycle. Linearity errors in the binary weighted main capacitor network are corrected using a capacitor trim network and correction factors stored in on-chip memory. The correction terms are calculated by a microcontroller during a calibration cycle, initiated either by power-up or by applying an external calibration signal at any time. During conversion, the correct trim capacitors are switched into the main capacitor array as needed to correct the conversion accuracy. This is faster than a complex digital error correction system, which could slow down the throughput rate. With all of the capacitors in both the main array and the trim array on the same chip, excellent stability is achieved, both over temperature and over time. For flexibility, timing circuits include both an internal clock generator and an input for an external clock to synchronize with external systems. Standard control signals and threestate input/output registers simplify interfacing ADC7802 to most micro-controllers, microprocessors or digital storage systems. Finally, this performance is matched with the low-power advantages of CMOS structures to allow a typical power consumption of 10mW. +5V NC 0-5V Input 1 2 3 4 +5V + 10µF 10nF 7 8 9 BUSY LOW LOW LOW Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 10 11 12 13 14 5 6 SFR AIN0 AIN1 AIN2 AIN3 VREF+ VREF– DGND VD D7 D6 D5 D4 D3 VA AGND CAL A1 A0 CLK BUSY HBE WR CS RD D0 D1 D2 28 10nF 27 26 25 24 23 22 21 20 19 18 17 16 15 Read Command Data Bit 0 (LSB) Data Bit 1 Data Bit 8 Data Bit 9 BUSY High Byte Enable Command Convert Command NC 100kΩ + 10µF Data Bit 11 Data Bit 3 (MSB) HBE Input HBE Input LOW HIGH Data Bit 2 Data Bit 10 HBE Input HBE Input LOW HIGH FIGURE 1. Basic Operation. Figures 2 and 3 show the full conversion sequence and the timing to initiate a conversion. CALIBRATION A calibration cycle is initiated automatically upon power-up (or after a power failure). Calibration can also be initiated by the user at any time by the rising edge of a minimum 100nswide LOW pulse on the CAL pin (pin 26), or by setting D1 HIGH in the Special Function Register (see SFR section). A calibration command will initiate a calibration cycle, regardless of whether a conversion is in process. During a calibration cycle, convert commands are ignored. Calibration takes 168 clock cycles, and a normal conversion (17 clock cycles) is added automatically. For maximum accuracy, the supplies and reference need to be stable during the calibration procedure. To ensure that supply voltages and reference voltages have settled and are stable, an internal timer provides a waiting period of 42,425 clock cycles between power-up/power-failure and the start of the calibration cycle. READING DATA Data from the ADC7802 is read in two 8-bit bytes, with the Low byte containing the 8 LSBs of data, and the High byte containing the 4 MSBs of data. The outputs are coded in straight binary (with 0V = 000 hex, 5V = FFF hex), and the data is presented in a right-justified format (with the LSB as the most right bit in the 16-bit word). Two read operations are required to transfer the High byte and Low byte, and the bytes are presented according to the input level on the High Byte Enable pin (HBE). OPERATION BASIC OPERATION Figure 1 shows the simple circuit required to operate ADC7802 in the Transparent Mode, converting a single input channel. A convert command on pin 20 (WR) starts a conversion. Pin 22 (BUSY) will output a LOW during the conversion process (including sample acquisition and conversion), and rises only after the conversion is completed. The two bytes of output data can then be read using pin 18 (RD) and pin 21 (HBE). STARTING A CONVERSION A conversion is initiated on the rising edge of the WR input, with valid signals on A0, A1 and CS. The selected input channel is sampled for five clock cycles, during which the comparator offset is also auto-zeroed to below 1/4LSB of error. The successive approximation conversion takes place during clock cycles 6 through 17. ® ADC7802 6 The bytes can be read in either order, depending on the status of the HBE input. If HBE changes while CS and RD are LOW, the output data will change to correspond to the HBE input. Figure 4 shows the timing for reading first the Low byte and then the High byte. ADC7802 provides two modes for reading the conversion results. At power-up, the converter is set in the Transparent Mode. 1 CLK 2 3 4 5 6 7 16 17 18 WR Multiplexer Settling, Offset Auto Zeroing and Sample Acquisition BUSY Successive Approximation Conversion FIGURE 2. Converter Timing. CS t1 t2 t3 WR or CAL t4 BUSY t5 SFR t6 A0, A1 V IH V IL FIGURE 3. Write Cycle Timing (for initiating conversion or calibration). BUSY t7 CS t8 RD t9 t10 t8 t10 SFR t11 HBE t13 Hi-Z State D0 - D7 t14 Low Byte Data Hi-Z t13 t14 High Byte Data t12 t11 t12 FIGURE 4. Read Cycle Timing. ® 7 ADC7802 TRANSPARENT MODE This is the default mode for ADC7802. In this mode, the conversion decisions from the successive approximation register are latched into the output register as they are made. Thus, the High byte (the 4 MSBs) can be read after the end of the ninth clock cycle (five clock cycles for the mux settling, sample acquisition and auto-zeroing of the comparator, followed by the four clock cycles for the 4MSB decisions.) The complete 12-bit data is available after BUSY has gone HIGH, or the internal status flag goes LOW (D7 when HBE is HIGH). LATCHED OUTPUT MODE This mode is activated by writing a HIGH to D0 and LOWs to D1 to D7 in the Special Function Register with CS and WR LOW and SFR and HBE HIGH. (See the discussion of the Special Function Register below.) In this mode, the data from a conversion is latched into the output buffers only after a conversion is complete, and remains there until the next conversion is completed. The conversion result is valid during the next conversion. This allows the data to be read even after a new conversion is started, for faster system throughput. TIMING CONSIDERATIONS Table I and Figures 3 through 8 show the digital timing of ADC7802 under the various operating modes. All of the critical parameters are guaranteed over the full –40oC to +85oC operating range for ease of system design. SPECIAL FUNCTION REGISTER (SFR) An internal register is available, either to determine additional data concerning the ADC7802, or to write additional instructions to the converter. Access to the Special Function Register is made by driving SFR HIGH. MIN 0 100 0 20 0 20 0 0 100 0 50 0 0 0 0 0 0 50 0 150 TYP 0 MAX 0 UNITS ns ns ns ns ns ns ns ns ns ns ns ns 80 90 20 100 20 150 180 60 ns ns ns ns ns SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 PARAMETER CS to WR Setup Time CS to WR Hold Time (2) (1) WR or CAL Pulse Width (2) WR to BUSY Propagation Delay A0, A1, HBE, SFR Valid to WR Setup Time A0, A1, HBE, SFR Valid to WR Hold Time BUSY to CS Setup Time CS to RD Setup Time RD Pulse Width CS to RD Hold Time (2) (2) HBE, SFR to RD Setup Time HBE, SFR to RD Hold Time RD to Valid Data (Bus Access Time) RD to Hi-Z Delay For SFR (3) (3) (3) RD to Hi-Z Delay (Bus Release Time) Data Valid to WR Setup Time Data Valid to WR Hold Time NOTES: (1) All input control signals are specified with tRISE = tFALL = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from VIH, VIL, VOH or VOL. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR. (3) Figures 7 and 8 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states. TABLE I. Timing Specifications (CLK = 1MHz external, TA = – 40°C to +85°C). CS t1 WR t5 HBE SFR VIH D0 - D7 Valid Data t16 VIL t17 t6 t2 t3 CS t8 RD t11 SFR t11 HBE t13 D0–D7 SFR Data t14 t12 t12 t10 FIGURE 5. Writing to the SFR. FIGURE 6. Reading the SFR. ® ADC7802 8 Table II shows the data in the Special Function Register that will be transferred to the output bus by driving HBE HIGH (with SFR HIGH) and initiating a read cycle (driving RD and CS LOW with WR HIGH as shown in Figure 4.) The Power Fail flag in the SFR is set when the power supply falls below about 3V. The flag also means that a new calibration has been started, and any data written to the SFR has been lost. Thus, the ADC7802 will again be in the Transparent Mode. Writing a LOW to D5 in the SFR resets the Power Fail flag. The Cal Error flag in the SFR is set when an overflow occurs during PIN D0 FUNCTION Mode Status DESCRIPTION If LOW, Transparent Mode enabled for data latches. If HIGH, Latched Output Mode enabled. If HIGH, calibration cycle in progress. Reserved for factory use. If HIGH, in Power Down Mode. Reserved for factory use. If HIGH, a power supply failure has occurred. (Supply fell below 3V.) If HIGH, an overflow occured during calibration. If HIGH, conversion or calibration in progress. calibration, which may happen in very noisy systems. It is reset by starting a calibration, and remains low after a calibration without an overflow is completed. Writing a HIGH to D3 in the FSR puts the ADC7802 in the Power Down Mode. Power consumption is reduced to 50µW and D3 remains HIGH. To exit Power Down Mode, either write a LOW to D3 in the SFR, or initiate a calibration by sending a LOW to the CAL pin or writing a HIGH to D1. During Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADC7802 will revert to power down. Table III shows how instructions can be transferred to the Special Function Register by driving HBE HIGH (with SFR HIGH) and initiating a write cycle (driving WR and CS LOW with RD HIGH.) The timing is shown in Figure 3. Note that writing to the SFR also initiates a new conversion. CONTROL LINES Table IV shows the functions of the various control lines on the ADC7802. The use of standard CS, RD and WR control signals simplifies use with most microprocessors. At the same time, flexibility is assured by availability of status information and control functions, both through the SFR and directly on pins. D1 D2 D3 D4 D5 D6 D7 CAL Flag Power Down Status POWER FAIL Flag CAL ERROR Flag BUSY Flag NOTE: These data are transferred to the bus when a read cycle is initiated with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW is reserved for factory use at this time, and will yield unpredictable data. TABLE II. Reading the Special Function Register. CS/WR Enables Transparent Mode for Data Latches. Enables Latched Output Mode for Data Latches. Initiates Calibration Cycle. Resets Power Fail flag. Activates Power Down Mode LOW LOW LOW LOW LOW SFR/HBE HIGH HIGH HIGH HIGH HIGH D0 LOW HIGH X X X D1 X X HIGH X X D3 LOW LOW LOW LOW HIGH D5 X X X LOW X D7 LOW LOW LOW LOW LOW D2/D4/D6 LOW LOW LOW LOW LOW NOTES: (1) In Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADC7802 will revert to power down. (2) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D2, D3, D4 or D6, or writing with SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time. TABLE III. Writing to the Special Function Register. CS X X 1 0 0 0 0 0 0 0 RD X X X 1 0 0 1 0 1 0 WR X X X 0↑1 1 1 0 1 0 1 SFR X X X 0 0 0 1 1 1 1 HBE X X X X 0 1 1 1 0 0 CAL 0↑1 X 1 1 1 1 1 1 1 1 BUSY X 0 X 1 X X 1 X X X OPERATION Initiates calibration cycle. Conversion or calibration in process. Inhibits new conversion from starting. None. Outputs in Hi-Z State. Initiates conversion. Low byte conversion results output on data bus. High byte conversion results output on data bus. Write to SFR and rising edge on WR initiates conversion. Contents of SFR output on data bus. Reserved for factory use. Reserved for factory use. (Unpredictable data on data bus.) TABLE IV. Control Line Functions. ® 9 ADC7802 INSTALLATION INPUT BANDWIDTH From the typical performance curves, it is clear that ADC7802 can accurately digitize signals up to 500Hz, but distortion will increase beyond this point. Input signals slewing faster than 8mV/µs can degrade accuracy. This is a result of the high-precision auto-zeroing circuit used during the acquisition phase. For applications requiring higher signal bandwidth, any good external sample/hold, like the SHC5320, can be used. INPUT IMPEDANCE ADC7802 has a very high input impedance (input bias current over temperature is 100nA max), and a low 50pF input capacitance. To ensure a conversion accurate to 12 bits, the analog source must be able to charge the 50pF and settle within the first five clock cycles after a conversion is initiated. During this time, the input is also very sensitive to noise at the analog input, since it could be injected into the capacitor array. Output Enable 3kΩ ADC7802 Output CL Test Point ADC7802 Output 3kΩ CL Test Point (a) Load Circuit tFALL Output Enable VD 90% 50% 10% Gnd VOH Gnd t15 t14 90% (b) From HIGH to Hi-Z, CL = 10pF tRISE VD Gnd 10% t13 VOH 2.4V Gnd (c) From Hi-Z to HIGH, CL = 50pF (a) Load Circuit 5V 90% 50% FIGURE 8. Measuring Active HIGH to/from Hi-Z State. Output Enable VD tFALL 90% 50% 10% Gnd VD VOL 10% t15 t14 (b) From LOW to Hi-Z, CL = 10pF In many applications, a simple passive low-pass filter as shown in Figure 9a can be used to improve signal quality. In this case, the source impedance needs to be less than 5kΩ to keep the induced offset errors below 1/2LSB, and to meet the acquisition time of five clock cycles. The values in Figure 9a meet these requirements, and will maintain the full power bandwidth of the system. For higher source impedances, a buffer like the one in Figure 9b should be used. 100Ω To ADC7802 22nF Analog Input Output Enable VD 10% tRISE 90% 50% VREF– (Normally 0V) (a) Passive Low Pass Filter Gnd t13 VD VOL 0.8V Analog Input R C OPA27 To ADC7802 (c) From Hi-Z to LOW, C L = 50pF VREF– (Normally 0V) (b) Active Low Pass Filter FIGURE 7. Measuring Active LOW to/from Hi-Z State. FIGURE 9. Input Signal Conditioning. ® ADC7802 10 INPUT PROTECTION The input signal range must not exceed ±VREF or VA by more than 0.3V. The analog inputs are internally clamped to VA. To prevent damage to the ADC7802, the current that can flow into the inputs must be limited to 20mA. One approach is to use an external resistor in series with the input filter resistor. For example, a 1kΩ input resistor allows an overvoltage to 20V without damage. REFERENCE INPUTS A 10µF tantalum capacitor is recommended between VREF+ and VREF– to insure low source impedance. These capacitors should be located as close as possible to the ADC7802 to reduce dynamic errors, since the reference provides packets of current as the successive approximation steps are carried out. VREF+ must not exceed VA. Although the accuracy is specified with VREF+ = 5V and VREF– = 0V, the converter can function with VREF+ as low as 2.5V and VREF– as high as 1V. As long as there is at least a 2.5V difference between VREF+ and VREF–, the absolute value of errors does not change significantly, so that accuracy will typically be within ±1LSB. (1/2LSB for a 5V span is 610µV, which is 1LSB for a 2.5V span.) The power supply to the reference source needs to be considered during system design to prevent VREF+ from exceeding (or overshooting) VA, particularly at power-on. Also, after power-on, if the reference is not stable within 42,425 clock cycles, an additional calibration cycle may be needed. POWER SUPPLIES The digital and analog power supply lines to the ADC7802 should be bypassed with 10µF tantalum capacitors as close to the part as possible. Although ADC7802 has excellent power supply rejection, even for higher frequencies, linear regulated power supplies are recommended. Care should be taken to insure that VD does not come up before VA, or permanent damage to the part may occur. Figure 10 shows a good supply approach, powering both VA and VD from a clean linear supply, with the 10Ω resistor between VA and VD insuring that VD comes up after VA. This is also a good method to further isolate the ADC7802 from digital supplies in a system with significant switching currents that could degrade the accuracy of conversions. GROUNDING To maximize accuracy of the ADC7802, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise feeding back into the analog ground. The VREF– pin is used as the reference point for input signals, so it should be connected directly to AGND to reduce potential noise problems. EXTERNAL CLOCK OPERATION The circuitry required to drive the ADC7802 clock from an external source is shown in Figure 11a. The external clock must provide a 0.8V max for LOW and a 3.5V min for HIGH, with rise and fall times that do not exceed 200ns. The minimum pulse width of the external clock must be 200ns. Synchronizing the conversion clock to an external system clock is recommended in microprocessor applications to prevent beat-frequency problems. Note that the electrical specification tables are based on using an external 2MHz clock. Typically, the specified accuracy is maintained for clock frequencies between 0.5 and 2.2MHz. INTERNAL CLOCK OPERATION Figure 11b shows how to use the internal clock generating circuitry. The clock frequency depends only on the value of the resistor, as shown in “Internal Clock Frequency vs RCLOCK” in the Typical Performance Curves section. +5V 1 2 5V REF 3 4 5 10µF + SFR AIN0 AIN1 AIN2 AIN3 VREF+ VREF– DGND VD D7 D6 D5 D4 D3 10Ω VA AGND CAL A1 A0 CLK BUSY HBE WR CS RD D0 D1 D2 28 10nF 27 26 25 24 23 22 21 20 19 18 17 16 15 + 10µF 6 10nF 7 8 10nF 9 10 11 12 13 14 10µF + FIGURE 10. Power Supply and Reference Decoupling. 74HC-Compatible Clock Source CLK To ADC7802 Pin 23 (a) External Clock Operation R +5V To ADC7802 Pin 23 11 fCLOCK (in Hz) = 10 /R (b) Internal Clock Operation FIGURE 11. Internal Clock Operation. ® 11 ADC7802 The clock generator can operate between 100kHz and 2MHz. With R = 100kΩ, the clock frequency will nominally be 800kHz. The internal clock oscillators may vary by up to 20% from device to device, and will vary with temperature, as shown in the typical performance curves. Therefore, use of an external clock source is preferred in many applications where control of the conversion timing is critical, or where multiple converters need to be synchronized. More iterations may be required if the op amp selected has large offset voltage or bias currents, or if the +5V reference is not precise. This circuit can also be used to adjust gain and offset errors due to the components preceding the ADC7802, to match the performance of the self-calibration provided by the converter. INTERFACING TO MOTOROLA MICROPROCESSORS Figure 14 shows a typical interface to Motorola microprocessors, while Figure 15 shows how the result can be placed in register D0. APPLICATIONS BIPOLAR INPUT RANGES Figure 12 shows a circuit to accurately and simply convert a bipolar ±5V input signal into a unipolar 0 to 5V signal for conversion by the ADC7802, using a precision, low-cost complete difference amplifier, INA105. A1 - A23 (A0 - A19) INA105 25kΩ 25kΩ 2 5 Address Bus A1 INT MC68000 (MC68008) AS DACK Address ADC_CS Decoder HBE SFR BUSY Logic CS RD WR ADC7802 ±5V Input 1 25kΩ 25kΩ 3 +5V (VREF+) 6 0 to 5V to ADC7802 R/W DO 0 - DO 7 DO 0 DO 1 D0 - D7 A1 A0 FIGURE 12. ±5V Input Range. Figure 13 shows a circuit to convert a bipolar ±10V input signal into a unipolar 0 to 5V signal for conversion by the ADC7802. The precision of this circuit will depend on the matching and tracking of the three resistors used. FIGURE 14. Interface to Motorola Microprocessors. Conversion is initiated by a write instruction decoded by the address decoder logic, with the lower two bits of the address bus selecting an ADC input channel, as follows: MOVE.W D0, ADC-ADDRESS The result of the conversion is read from the data bus by a read instruction to ADC-ADDRESS as follows: MOVEP.W $000 (ADC-ADDRESS), D0 This puts the 12-bit conversion result in the DO register, as shown in Figure 15. The address decoder must pull down ADC_CS at ADC-ADDRESS to access the Low byte and ADC-ADDRESS +2 to access the High byte. INTERFACING TO INTEL MICROPROCESSORS Figure 16 shows a typical interface to Intel. A conversion is initiated by a write instruction to address ADC_CS. Data pins DO0 and DO1 select the analog input channel. The BUSY signal can be used to generate a microprocessor interrupt (INT) when the conversion is completed. A read instruction from the ADC_CS address fetches the Low byte, and a read instruction from the ADC_CS address +2 fetches the High byte. +5V (VREF+) R1 10kΩ R2 5kΩ OPA27 0 to 5V to ADC7802 ±10V Input R3 10kΩ FIGURE 13. ±10V Input Range. To trim this circuit for full 12-bit precision, R2 and R3 need to be adjustable over appropriate ranges. To trim, first have the ADC7802 converting continually and apply +9.9927V (+10V – 1.5LSB) at the input. Adjust R3 until the ADC7802 output toggles between the codes FFE hex and FFF hex. This makes R3 extremely close to R1. Then, apply –9.9976V (–10V + 0.5LSB) at the input, and adjust R2 until the ADC7802 output toggles between 000 hex and 001 hex. At each trim point, the current through the third resistor will be almost zero, so that one trim iteration will be enough in most cases. ® ADC7802 12 31 24 23 16 15 B U S Y 0 0 0 M S B DDD BBB 11 10 9 8 7 L S B0 DDDDDDDDD BBBBBBBBB 876543210 FIGURE 15. Conversion Results in Motorola Register D0. Intel Microprocessor Based Systems (IO/M) Address Bus A1 A2 INT 8085 8086/88 80186/188 80286 8031 8051 Address ADC_CS Decoder HBE SFR BUSY Logic CS RD WR RD WR ADC7802 Data Bus DO 0 DO 1 D0 - D7 A1 A0 FIGURE 16. Interface to Intel Microprocessors. ® 13 ADC7802