ADS1209
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SBAS491 – FEBRUARY 2010
Two 1-Bit, 10MHz, 2nd-Order
Delta-Sigma Modulators
Check for Samples: ADS1209
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The ADS1209 is a two-channel, high-performance,
delta-sigma (ΔΣ) modulator with an 86dB dynamic
range, operating from a single +5V supply. The
differential inputs are ideal for direct connection to
signal sources in an industrial environment. With the
appropriate digital filter and modulator rate, the
device can be used to achieve 16-bit analog-to-digital
(A/D) conversion with no missing codes. Effective
accuracy of 14 bits can be obtained with a digital filter
bandwidth of 20kHz at a modulator rate of 10MHz.
The ADS1209 is designed for use in high-resolution
measurement
applications
including
current
measurements, industrial process control, and
resolvers. It is available in a TSSOP-24 package and
is specified for operation over the ambient
temperature range of –40°C to +105°C.
1
2
•
16-Bit Resolution
13-Bit Linearity
±2.3V Specified Input Voltage Range
Internal Reference Voltage: 2%
Gain Error: 0.5%
Two Independent Delta-Sigma Modulators
Two Input Reference Buffers
On-Chip Oscillator
Selectable Internal or External Clock
Specified Temperature Range:
–40°C to +105°C
TSSOP-24 Package
APPLICATIONS
•
•
•
•
•
Motor Control
Current Measurement
Resolver
Industrial Process Control
Instrumentation
AVDD
CHA+
CHA-
2nd-Order
DS Modulator
BVDD
OUTA
Output
Interface
Circuit
CLKOUT
REFINA
CHB+
CHB-
OUTB
2nd-Order
DS Modulator
Divider
REFINB
Clock
Select
Out
REFOUT
CLKIN
CLKSEL
EN
Reference
Voltage
2.5V
RC
Oscillator
20MHz
AGND
BGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
ADS1209
SBAS491 – FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
ADS1209
TSSOP-24
PW
SPECIFIED
TEMPERATURE
RANGE
–40°C to +105°C
TRANSPORT MEDIA,
QUANTITY
ORDERING NUMBER
ADS1209SPW
Tube, 60
ADS1209SPWR
Tape and Reel, 2000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating ambient temperature range, unless otherwise noted.
ADS1209
UNIT
–0.3 to 6
V
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
–0.3 to 6
V
Analog input voltage
AGND – 0.3 to AVDD + 0.3
V
Reference input voltage
AGND – 0.3 to AVDD + 0.3
V
Digital input voltage
BGND – 0.3 to BVDD + 0.3
V
Ground voltage difference, AGND to BGND
±0.3
V
Input current to any pin except supply
±10
mA
Operating virtual junction temperature range, TJ
–40 to +150
°C
Operating ambient temperature range, TOA
ESD ratings,
all pins
(1)
–40 to +125
°C
Human body model (HBM) JEDEC standard 22, test method A114-C.01
+2000
V
Charged device model (CDM) JEDEC standard 22, test method C101
+500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
PACKAGE
TA ≤ +25°C
POWER RATING
DERATING FACTOR
ABOVE TA = +25°C (1)
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
TA = +105°C
POWER RATING
TSSOP-24
1420mW
11.3mW/°C
909mW
738mW
511mW
This is the inverse of the traditional junction-to-ambient thermal resistance (RqJA). Thermal resistances are not production tested and are
for informational purposes only.
THERMAL CHARACTERISTICS: TSSOP-24
Over the operating ambient temperature range of –40°C to +105°C, unless otherwise noted.
PARAMETER
RqJA
Junction-to-air thermal resistance
RqJC
Junction-to-case thermal resistance
PD
Device power dissipation
(1)
2
TEST CONDITIONS
High-K thermal resistance (1)
CLKSEL = 0, 5V supply
MIN
TYP
MAX
UNIT
88
°C/W
26
°C/W
100
mW
Modeled in accordance with the High-K thermal definitions of EIA/JESD51-3.
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SBAS491 – FEBRUARY 2010
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
Low-voltage levels
2.7
3.0
3.6
V
5V logic levels
4.5
5
5.5
V
0.5
2.5
2.6
V
0
AVDD
V
–0.92 ×
VREF
+0.92 ×
VREF
V
24
MHz
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
Reference input voltage, VREF
Operating common-mode signal
Analog inputs
External clock
+IN – (–IN)
(1)
16
20
Operating ambient temperature range, TOA
–40
+125
°C
Specified ambient temperature range, TA
–40
+105
°C
(1)
With reduced accuracy, clock can go from 1MHz up to 33MHz; see Typical Characteristic curves.
ELECTRICAL CHARACTERISTICS
Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– =
2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
ADS1209
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP (1)
MAX
UNIT
16
Bits
DC ACCURACY
Integral linearity error (2)
INL
VIN = ±2.3VPP
–8
±3.8
+8
LSB
VIN = ±2.0VPP
–4
±1.8
+4
LSB
1
4
LSB
Integral linearity match
DNL
Differential nonlinearity
–1
VOS
Input offset error
–3
+1
LSB
±1.5
+3
mV
0.2
2
mV
–8
1
+8
mV/°C
–0.5
±0.02
+0.5
% FSR
0.1
0.5
Input offset error match
TCVOS
Input offset error thermal drift
GERR
Gain error
Referenced to VREFIN
Gain error match
TCGERR
Gain error thermal drift
PSRR
Power-supply rejection ratio
±1.3
4.5V < AVDD < 5.5V
% FSR
ppm/°C
82
dB
ANALOG INPUTS
FSR
Full-scale differential input voltage
range
(CHx+) – (CHx–); CHx– = 2.5V
Specified differential input voltage
range
(CHx+) – (CHx–); CHx– = 2.5V
Absolute operating input voltage
range
Input capacitance
CHx to AGND
IIL
Input leakage current
Clock turned off
RID
Differential input resistance
CID
Differential input capacitance
Common-mode rejection ratio
BW
Bandwidth
(1)
(2)
+VREFIN
–0.92 ×
VREF
V
+0.92 ×
VREF
0
CI
CMRR
–VREFIN
V
AVDD
V
1
µA
3
–1
pF
100
kΩ
2.5
pF
At dc
108
dB
VIN = ±1.25VPP at 40kHz
117
dB
50
MHz
Full-scale sine wave, –3dB
All typical values are at TA = +25°C.
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range, expressed either
as the number of LSBs or as a percent of specified input range (4.6V).
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ELECTRICAL CHARACTERISTICS (continued)
Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– =
2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
ADS1209
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
8
10
12
MHz
7.8
10
12
MHz
1
20
24
MHz
–85
–80
dB
SAMPLING DYNAMICS
CLKSEL = 1, –40°C ≤ TA ≤ +85°C
fCLK
Internal clock frequency
CLKSEL = 1,
–40°C ≤ TA ≤ +105°C
fCLKIN
External clock frequency
CLKSEL = 0
AC ACCURACY
THD
Total harmonic distortion
VIN = ±2.3VPP at 5kHz
SFDR
Spurious-free dynamic range
VIN = ±2.3VPP at 5kHz
82
86
dB
VIN = ±2.3VPP at 5kHz
86
90
dB
VIN = ±2.0VPP at 5kHz
85
89
dB
80
84
dB
100
dB
SNR
Signal-to-noise ratio
SINAD
Signal-to-noise + distortion
VIN = ±2.3VPP at 5kHz
Channel-to-channel isolation
VIN = ±2.3VPP at 5kHz
REFERENCE VOLTAGE OUTPUT
VREFOUT
Reference output voltage
TCVREFOUT
Reference output voltage drift
Output voltage noise
2.450
2.5
2.550
V
±20
ppm/°C
f = 0.1Hz to 10Hz, CL = 10mF
10
mVRMS
f = 10Hz to 10kHz, CL = 10mF
12
mVRMS
IREFOUT
Output current
10
mA
IREFSC
Short-circuit current
0.5
mA
100
ms
Turn-on settling time
To accuracy level of 0.1%, no load
REFERENCE VOLTAGE INPUT
VREFIN
Input voltage
RREFIN
Input resistance
CREFIN
Input capacitance
IREFIN
Input current
0.5
2.5
2.6
V
100
MΩ
5
pF
1
mA
V
DIGITAL INPUTS
Logic family
CMOS with Schmitt Trigger
VIH
High-level input voltage
0.7 × BVDD
BVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × BVDD
V
IIN
Input current
±50
nA
CI
Input capacitance
VIN = BVDD or BGND
5
pF
DIGITAL OUTPUTS
Logic family
CMOS
VOH
High-level output voltage
BVDD = 4.5V, IOH = –100mA
VOL
Low-level output voltage
BVDD = 4.5V, IOL = +100mA
CO
Output capacitance
CL
Load capacitance
V
0.5
5
V
pF
30
Data format
4
4.44
pF
Bit stream
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SBAS491 – FEBRUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– =
2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
ADS1209
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
DIGITAL INPUTS
Logic family
LVCMOS
VIH
High-level input voltage
BVDD = 3.6V
2
BVDD + 0.3
V
VIL
Low-level input voltage
BVDD = 2.7V
–0.3
0.8
V
IIN
Input current
VIN = BVDD or BGND
±50
nA
CI
Input capacitance
5
pF
DIGITAL OUTPUTS
Logic family
LVCMOS
VOH
High-level output voltage
BVDD = 2.7V, IOH = –100mA
VOL
Low-level output voltage
BVDD = 2.7V, IOL = +100mA
CO
Output capacitance
CL
Load capacitance
BVDD – 0.2
V
0.2
5
Data format
V
pF
30
pF
Bit stream
POWER SUPPLY
AVDD
Analog supply voltage
BVDD
Buffer I/O supply voltage
AIDD
Analog operating supply current
BIDD
PD
Buffer I/O operating supply current
Power dissipation
4.5
5.0
5.5
V
Low-voltage levels
2.7
3.0
3.6
V
5V logic levels
4.5
5.0
5.5
V
CLKSEL = 1
12.2
17
mA
CLKSEL = 0
11.8
16
mA
0.9
2
mA
BVDD = 3V, CLKOUT = 10MHz
BVDD = 5V, CLKOUT = 10MHz
1.3
3
mA
CLKSEL = 1, 5V supply
67.5
100.0
mW
CLKSEL = 0, 5V supply
65.5
95
mW
BLANKSPACE
EQUIVALENT INPUT CIRCUITS
BVDD
AVDD
RON
650W
C(SAMPLE)
1pF
AIN
DIN
Diode Turn-On Voltage: 0.35V
AGND
BGND
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
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PIN CONFIGURATION
PW PACKAGE
TSSOP-24
(TOP VIEW)
AVDD
1
24
AVDD
AGND
2
23
REFOUT
REFINA
3
22
AGND
NC
4
21
OUTA
CHA+
5
20
OUTB
CHA-
6
19
CLKOUT
ADS1209
CHB-
7
18
BGND
CHB+
8
17
BVDD
NC
9
16
CLKIN
REFINB
10
15
CLKSEL
AGND
11
14
AGND
AVDD
12
13
AVDD
PIN DESCRIPTIONS
PIN
NO.
I/O (1)
AVDD
1
P
Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AGND
2
P
Analog ground. Connect to analog ground plane.
REFINA
3
AI
Reference voltage input for channel A
NC
4
NC
This pin is not internally connected
CHA+
5
AI
Fully differential noninverting analog input channel A
CHA–
6
AI
Fully differential inverting analog input channel A
CHB–
7
AI
Fully differential inverting analog input channel B
CHB+
8
AI
Fully differential noninverting analog input channel B
NC
9
NC
This pin is not internally connected
REFINB
10
AI
Reference voltage input for channel B
AGND
11
P
Analog ground. Connect to analog ground plane.
AVDD
12
P
Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AVDD
13
P
Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AGND
14
P
Analog ground. Connect to analog ground plane.
CLKSEL
15
DI
Clock select input. When this pin is low, an external clock source at CLKIN is used. When high, the
internal RC oscillator is used as clock source.
CLKIN
16
DI
External clock input. Must be tied to BVDD or BGND, if not used.
BVDD
17
P
I/O buffer power supply, nominal: 3V. Decouple to BGND with a 0.1µF ceramic capacitor
BGND
18
P
I/O buffer ground. Connect to digital ground plane
CLKOUT
19
DO
Bit stream clock output
OUTB
20
DO
Bit stream data output of channel B modulator
OUTA
21
DO
Bit stream data output of channel A modulator
AGND
22
P
REFOUT
23
AO
AVDD
24
P
NAME
(1)
6
DESCRIPTION
Analog ground. Connect to analog ground plane.
Internal reference voltage output, nominal: 2.5V. Decouple to AGND with a 0.1µF ceramic capacitor.
Analog power supply, nominal: 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AI = analog input; AO = analog output; DI = digital input; DO = digital output; P = power supply; NC = not connected.
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PARAMETER MEASUREMENT INFORMATION
t2
t1
CLKIN
tD1
t3
tD2
t4
CLKOUT
tD3
tH1
OUTx
Figure 1. ADS1209 Timing Diagram
TIMING CHARACTERISTICS (1)
Over the recommended operating ambient temperature range of –40°C to +105°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless
otherwise noted.
MIN
MAX
UNIT
t1
CLKIN period
PARAMETER
CLKSEL = 0
TEST CONDITIONS
41.6
1000
ns
t2
CLKIN high time
CLKSEL = 0
10
t1 – 10
ns
CLKSEL = 0
2 × t1
t3
CLKOUT period
t4
CLKOUT high time
tD1
CLKIN rising edge to CLKOUT falling edge delay
CLKSEL = 0
tD2
CLKIN rising edge to CLKOUT rising edge delay
CLKSEL = 0
CLKSEL = 1
tD3
CLKOUT rising edge to new data valid delay
tH1
Data valid hold time referred to rising CLKOUT edge
(1)
ns
83
125
ns
(t3/2) – 5
(t3/2) + 5
ns
10
ns
10
ns
CLKSEL = 0
t2 + 7
ns
CLKSEL = 1
(t3/4) + 8
ns
CLKSEL = 0
t2 – 3
ns
CLKSEL = 1
(t3/4) – 8
ns
All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
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TYPICAL CHARACTERISTICS
At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and
16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
INTEGRAL NONLINEARITY MATCH
vs INPUT SIGNAL
8
4
6
3
4
2
INL Match (LSB)
INL (LSB)
INTEGRAL NONLINEARITY
vs INPUT SIGNAL VOLTAGE
2
0
-2
-40°C
+25°C
+85°C
+105°C
-4
-6
-8
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5
Differential Input Voltage (V)
2.0
-1
-40°C
+25°C
+85°C
+105°C
-3
-4
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5
Differential Input Voltage (V)
2.5
Figure 2.
Figure 3.
INTEGRAL NONLINEARITY
vs TEMPERATURE
OFFSET ERROR
vs ANALOG SUPPLY VOLTAGE
2.5
2.5
2.0
1.5
Offset Error (mV)
4
2
0
-2
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-4
-6
-2.5
-3.0
-8
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
4.5
110 125
4.6
4.7
4.8
4.9 5.0 5.1
AVDD (V)
5.2
Figure 4.
Figure 5.
OFFSET ERROR AND MATCH
vs TEMPERATURE
GAIN ERROR AND MATCH
vs TEMPERATURE
0.5
2.5
0.4
Gain Error and Match (%FSR)
3.0
2.0
1.5
1.0
Offset Match
0.5
0
-0.5
-1.0
Offset
-1.5
-2.0
5.3
5.4
5.5
0.3
0.2
Gain Match
0.1
0
Gain
-0.1
-0.2
-0.3
-0.4
-2.5
-3.0
-0.5
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
-40 -25 -10
Figure 6.
8
2.0
3.0
6
INL (LSB)
0
-2
8
Offset Error and Match (mV)
1
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and
16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO
vs RIPPLE FREQUENCY
COMMON-MODE REJECTION RATIO
vs INPUT SIGNAL FREQUENCY
90
120
CMRR (dB)
130
PSRR (dB)
100
80
70
110
100
60
90
100
1k
100
10k
1k
10k
Figure 8.
Figure 9.
INTERNAL CLOCK FREQUENCY
ANALOG SUPPLY VOLTAGE
INTERNAL CLOCK FREQUENCY
vs TEMPERATURE
12.0
12.0
11.5
11.5
11.0
11.0
10.5
10.5
10.0
1M
9.5
10.0
9.5
9.0
9.0
8.5
8.5
8.0
8.0
4.6
4.6
4.7
4.8
4.9 5.0 5.1
AVDD (V)
5.2
5.3
5.4
-40 -25 -10
5.5
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION AND SPURIOUS-FREE
DYNAMIC RANGE vs INPUT FREQUENCY
TOTAL HARMONIC DISTORTION AND SPURIOUS-FREE
DYNAMIC RANGE vs TEMPERATURE
96
-80
96
-82
94
-82
94
92
-84
-88
-90
88
THD
86
-92
-94
100
1k
10k
92
THD
-86
90
-88
88
-90
84
-92
82
-94
-40 -25 -10
fIN (Hz)
Figure 12.
SFDR (dB)
90
SFDR (dB)
-86
SFDR
THD (dB)
-80
-84
THD (dB)
100k
fIN (Hz)
fCLK (MHz)
fCLK (MHz)
fRIPPLE (Hz)
86
SFDR
84
82
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and
16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE +
DISTORTION vs TEMPERATURE
96
96
94
94
SNR
92
SNR and SINAD (dB)
SNR and SINAD (dB)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE +
DISTORTION vs INPUT FREQUENCY
90
88
86
SINAD
84
82
92
SNR
90
88
86
SINAD
84
82
80
100
80
1k
10k
-40 -25 -10
5
20 35 50 65
Temperature (°C)
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 1kHz, 4.6VPP)
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 5kHz, 4.6VPP)
0
0
-20
-20
-40
-40
-60
-80
110 125
-60
-80
-100
-100
-120
-120
-140
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
Frequency (kHz)
8
10
12
14
16
18
20
Frequency (kHz)
Figure 16.
Figure 17.
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
SUPPLY CURRENT
vs TEMPERATURE
2.55
18
2.54
16
2.53
14
2.52
IAVDD, Internal CLK
12
2.51
IDD (mA)
VREFOUT (V)
95
Figure 15.
-140
2.50
2.49
IAVDD, External CLK
10
8
6
2.48
2.47
4
2.46
2
2.45
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
IBVDD
-40 -25 -10
Figure 18.
10
80
Figure 14.
Magnitude (dB)
Magnitude (dB)
fIN (Hz)
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 19.
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ADS1209
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SBAS491 – FEBRUARY 2010
GENERAL DESCRIPTION
The ADS1209 is a two-channel, second-order, CMOS
device with two delta-sigma (ΔΣ) modulators,
designed for medium- to high-resolution A/D signal
conversions from dc to 40kHz (filter response –3dB) if
an oversampling ratio (OSR) of 64 is chosen. The
output of the converter (OUTx) provides a stream of
digital ones and zeros. The time average of this serial
output is proportional to the analog input voltage.
The modulator shifts the quantization noise to high
frequencies. A low-pass digital filter should be used
at the output of the ΔΣ modulator. The filter serves
two functions. First, it filters out high-frequency noise.
Second, the filter converts the 1-bit data stream at a
high sampling rate into a higher-bit data word at a
lower rate (decimation).
An application-specific integrated circuit (ASIC) or
field-programmable gate array (FPGA) can be used
to implement the digital filter. Alternatively, TI's
AMC1210 offers four programmable digital filters that
can be used. Figure 20 and Figure 21 show typical
application circuits with the ADS1209 connected to an
FPGA or ASIC.
The overall performance (that is, speed and
accuracy) depends on the selection of an appropriate
OSR and filter type. A higher OSR produces greater
output accuracy while operating at a lower data rate.
Alternatively, a lower OSR produces lower output
accuracy, but operates at a higher data rate. This
system allows flexibility with the digital filter design
and is capable of A/D conversion results that have a
dynamic range exceeding 86dB with an OSR = 256.
2kW
5kW
±5V
BVDD
AVDD
+5V
27W
0.1mF
CHA+
OPA2350
0.1nF
5kW
CHA-
OUTA
2nd-Order
DS Modulator
OUTB
Output
Interface
Circuit
2kW
FPGA
or
ASIC
REFINA
CLKOUT
5kW
2kW
CHB+
+5V
CHB-
±5V
BVDD
0.1mF
REFINB
OPA2350
Divider
0.1nF
5kW
+3V
BGND
27W
0.1mF
2nd-Order
DS Modulator
2kW
+3V
Clock
Select
CLKIN
CLKSEL
+5V
AVDD
+5V
Out EN
RC
Oscillator
20MHz
REFOUT
Reference
Voltage
2.5V
0.1mF
AVDD
+5V
AVDD
+5V
0.1mF
0.1mF
AVDD
AGND AGND AGND AGND
0.1mF
0.1mF
+5V
OPA336
0.1mF
Figure 20. Single-Ended Connection Diagram for the ADS1209 ΔΣ Modulator
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ADS1209
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AVDD
+5V
BVDD
27W
R1
CH A+
OPA4354
IN+
CH A-
0.1nF
2nd-Order
DS Modulator
R2
OUT A
Output
Interface
Circuit
OUT B
FPGA
or
ASIC
REFIN A
CLKOUT
+5V
CH B+
27W
R1
OPA4354
CH B-
2nd-Order
DS Modulator
+3V
BVDD
0.1mF
BGND
INREFIN B
R2
Divider
+5V
+3V
27W
R1
Clock
Select
OPA4354
IN+
CLKIN
CLKSEL
0.1nF
+5V
R2
AVDD
+5V
Out EN
+5V
RC
Oscillator
20MHz
27W
R1
OPA4354
IN-
REFOUT
R2
Reference
Voltage
2.5V
0.1mF
AVDD
+5V
AVDD
+5V
0.1mF
0.1mF
AVDD
AGND AGND AGND AGND
0.1mF
0.1mF
+5V
OPA336
0.1mF
Figure 21. Differential Connection Diagram for the ADS1209 ΔΣ Modulator
12
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ADS1209
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SBAS491 – FEBRUARY 2010
THEORY OF OPERATION
The differential analog input of the ADS1209 is
implemented with a switched-capacitor circuit. This
circuit implements a second-order modulator stage,
which digitizes the analog input signal into a 1-bit
output stream. The clock source can be internal as
well as external. Every analog input signal is
continuously sampled by the modulator and
compared to a reference voltage that is applied to the
REFINx pin. A digital stream that represents the
analog input voltage over time appears at the output
of the corresponding converter.
ANALOG INPUT STAGE
Analog Input
The topology of the analog inputs of ADS1209 is
based on fully differential switched-capacitor
architecture. This input stage provides the
mechanism to achieve low system noise, high
common-mode rejection, and excellent power-supply
rejection.
BLANKSPACE
The input impedance of the analog input depends on
the modulator clock frequency (fMOD). Figure 22
shows the basic input structure of one channel of the
ADS1209. The relationship between the input
impedance of the ADS1209 and the modulator clock
frequency is:
100kW
ZIN =
fMOD/10MHz
(1)
The input impedance becomes a consideration in
designs where the source impedance of the input
signal is high. This high impedance may cause
degradation in gain, linearity, and THD. The
importance of this effect depends on the desired
system performance. There are two restrictions on
the analog input signals, CHx+ and CHx–. If the input
voltage exceeds the range (AGND – 0.3V) to (AVDD
+ 0.3V), the input current must be limited to 10mA
because the input protection diodes on the front end
of the converter begin to turn on. In addition, the
linearity and noise performance of the device meet
the stored specifications only when the differential
analog voltage resides within ±2.3V (with VREFIN as a
midpoint); however, the FSR input voltage is ±2.5V.
650W
AIN+
1.2pF
0.4pF
High
Impedance
> 1GW
VCM
Switching Frequency = CLK
0.4pF
650W
1.2pF
AIN-
High
Impedance
> 1GW
Figure 22. Input Impedance of the ADS1209
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ADS1209
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www.ti.com
Modulator
The ADS1209 can be operated in two modes. When
CKLSEL = 1, the two modulators operate using the
internal clock, which is fixed at 20MHz. When
CKLSEL = 0, the modulators operate using an
external clock. In both modes, the clock is internally
divided by two and functions as the modulator clock.
The frequency of the external clock can vary from
1MHz to 24MHz to adjust for the clock requirements
of the application.
The modulator topology is a second-order,
switched-capacitor, ΔΣ modulator, such as the one
conceptualized in Figure 23. The analog input voltage
and the output of the 1-bit digital-to-analog converter
(DAC) are differentiated, providing analog voltages at
X2 and X3. The voltages at X2 and X3 are presented
to the respective individual integrators. The output of
these integrators progresses in a negative or positive
direction. When the value of the signal at X4 equals
the comparator reference voltage, the output of the
comparator switches from low to high, or vice versa,
depending on its original state. When the output
value of the comparator switches direction, the 1-bit
DAC responds on the next clock pulse by changing
its analog output voltage at X6, causing the
integrators to progress in the opposite direction. The
feedback of the modulator to the front end of the
integrators forces the value of the integrator output to
track the average of the input.
DIGITAL OUTPUT
A differential input signal of 0V ideally produces a
stream of ones and zeros that are high 50% of the
time and low 50% of the time. A differential input of
+2.3V produces a stream of ones and zeros that are
high 92% of the time. A differential input of –2.3V
produces a stream of ones and zeros that are high
8% of the time. The input voltage versus the output
modulator signal is shown in Figure 24.
fCLK
X(t)
X2
X3
Integrator 1
Integrator 2
X4
DATA
fS
VREF
Comparator
X6
DAC
Figure 23. Block Diagram of the Second-Order Modulator
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 24. Analog Input vs Modulator Output of the ADS1209
14
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DIGITAL INTERFACE
INTRODUCTION
The analog signal connected to the input of the ΔΣ
modulator is converted using the clock signal applied
to the modulator. The result of the conversion (or
modulation) is available on one of the OUTx pins,
depending on the modulator. In addition, a common
clock
output
signal
(CLKOUT)
for
both
simultaneously-sampling modulators is provided. If
CLKSEL = 1, CLKIN must not be left floating, but
should tied to BVDD or BGND.
This behavior can be adjusted by a cascaded filter
structure. For example, the first decimation stage can
be a Sinc3 filter with a low OSR, and the second
stage a high-order filter.
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter
for Current Measurement in Motor Control
Applications, available for download at www.ti.com.
0
OSR = 32
fDATA = 10MHz/32 = 312.5kHz
-3dB: 81.9kHz
-10
MODES OF OPERATION
The device clock is divided by two before being used
as the modulator clock. Therefore, the default clock
frequency of the modulator is 10MHz. With a possible
external clock range of 1MHz to 24MHz, the
modulator operates between 500kHz and 12MHz.
FILTER USAGE
Gain (dB)
-20
The device clock of the ADS1209 is 20MHz by
default. The device clock can either be generated by
the internal 20MHz RC oscillator or can be provided
by an external clock source. For this purpose, the
CLKIN pin is provided; it is controlled by the mode
setting, CLKSEL.
-60
-70
-80
0
H(z) =
1 - z-1
(2)
This filter provides the best output performance with a
relatively low number of gates required for
implementation. For oversampling ratios in the range
of 16 to 256, this filter architecture represents a good
choice. All the characterizations in this data sheet are
done using a Sinc3 filter with an oversampling ratio of
OSR = 256 and an output word width of 16 bits.
200
400
600
800
1000
1200
1400
1600
Frequency (kHz)
Figure 25. Frequency Response of Sinc3 Filter
(OSR = 32)
0
-10
-20
Gain (dB)
3
1 - z-OSR
-40
-50
The modulator generates a bitstream. In order to
output a digital word equivalent to the analog input
voltage, the bitstream must be processed by a digital
filter.
A simple filter, built with minimal effort and hardware,
is the Sinc3 filter shown in Equation 2:
-30
-30
-40
-50
-60
100
1k
10k
100k
Frequency (Hz)
Figure 26. Frequency Response of Sinc3 Filter
(OSR = 256)
In a Sinc3 filter response (shown in Figure 25 and
Figure 26), the location of the first notch occurs at the
frequency of output data rate fDATA = fMOD/OSR. The
–3dB point is located at half the Nyquist frequency or
fDATA/4.
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ADS1209
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www.ti.com
The effective number of bits (ENOB) can be used to
compare the performance of A/D converters and ΔΣ
modulators. Figure 27 shows the ENOB of the
ADS1209 with different filter types. In this data sheet,
the ENOB is calculated from the SNR as shown in
Equation 3:
SNR = 1.76dB + 6.02dB ´ ENOB
(3)
the modulator clock divided by the OSR. For
overcurrent protection, filter types other than Sinc3
may be a better choice. A simple example is a Sinc2
filter. The Sincfast is a modified Sinc2 filter as
Equation 4 shows:
2
H(z) =
1 - z-OSR
1-z
-1
(1 + z-2 ´ OSR)
(4)
16
Figure 28 compares the settling time of different filter
types operating with a 10MHz modulator clock.
14
Sinc3
Sinc2
10
10
Sinc
9
8
3
Sincfast
8
6
7
ENOB (Bits)
ENOB (Bits)
12
4
2
0
10
100
1000
Sinc
2
6
5
Sinc
4
3
2
OSR
1
Figure 27. Measured ENOB vs OSR
0
0
In motor-control applications, a very fast response
time is required for overcurrent detection. There is a
constraint between 1ms and 5ms with 3 bits to 7 bits
of resolution. The time for full settling depends on the
filter order. Therefore, the full settling of the Sinc3
filter requires three data clocks and the Sinc2 filter
requires two data clocks. The data clock is equal to
16
2
4
6
Settling Time (ms)
8
10
Figure 28. Measured ENOB vs Settling Time
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter
for Current Measurement in Motor Control
Applications, available for download at www.ti.com.
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ADS1209
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SBAS491 – FEBRUARY 2010
LAYOUT CONSIDERATIONS
POWER SUPPLIES
DECOUPLING
An applied external digital filter rejects high-frequency
noise. PSRR and CMRR improve at higher
frequencies because the digital filter suppresses
high-frequency noise. However, the suppression of
the filter is not infinite while high-frequency noise
continues to influence the conversion result.
Good decoupling practices must be used for the
ADS1209 and for all components in the design. All
decoupling capacitors, specifically the 0.1mF ceramic
capacitors, must be placed as close as possible to
the pin being decoupled. A 1mF and 10mF capacitor,
in parallel with the 0.1mF ceramic capacitor, can be
used to decouple AVDD to AGND as well as BVDD
to BGND. At least one 0.1mF ceramic capacitor must
be used to decouple every AVDD to AGND and
BVDD to BGND, as well as for the digital supply on
each digital component.
Inputs to the ADS1209, such as CHx+, CHx–, and
CLKIN, should not be present before the power
supply is on. Violating this condition could cause
latch-up. If these signals are present before the
supply is on, series resistors should be used to limit
the input current to a maximum of 10mA.
GROUNDING
The digital supply sets the I/O voltage for the
interface and can be set within a range of 2.7V to
5.5V.
Analog and digital sections of the design must be
carefully and cleanly partitioned. Each section should
have its own ground plane with a connection between
them underneath the converter.
In cases where both the analog and digital I/O
supplies share the same supply source, an RC filter
of 10Ω and 0.1mF can be used to help reduce the
noise in the analog supply.
For multiple converters, connect the two ground
planes as close as possible to each of the converters.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS1209SPW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1209
ADS1209SPWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ADS1209
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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