ADS1217
ADS
121
7
SBAS260C – MAY 2002 – REVISED FEBRUARY 2007
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
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The ADS1217 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from 2.7V to 5.25V supplies. The delta-sigma,
A/D converter provides up to 24 bits of no missing code
performance and effective resolution of 22 bits.
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24 BITS NO MISSING CODES
INL: 0.0012% of FSR (max)
FULL-SCALE INPUT: ±2VREF
PGA FROM 1 TO 128
22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
SINGLE CYCLE SETTLING MODE
PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
ON-CHIP 1.25V/2.5V REFERENCE
ON-CHIP CALIBRATION
SPI COMPATIBLE
POWER SUPPLY: 2.7V to 5.25V
< 1mW POWER CONSUMPTION, VDD = 3V
The eight input channels are multiplexed. Internal buffering
can be selected to provide a very high input impedance for
direct connection to transducers or low-level voltage signals.
Burnout current sources are provided that allow for the
detection of an open or shorted sensor. An 8-bit Digital-toAnalog Converter (DAC) provides an offset correction with a
range of 50% of the FSR (Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a 2nd-order,
delta-sigma modulator and programmable sinc filter. The
reference input is differential and can be used for ratiometric
measurements. The onboard current DACs operate independently with the maximum current set by an external resistor.
APPLICATIONS
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INDUSTRIAL PROCESS CONTROL
LIQUID/GAS CHROMATOGRAPHY
BLOOD ANALYSIS
SMART TRANSMITTERS
PORTABLE INSTRUMENTATION
WEIGH SCALES
PRESSURE TRANSDUCERS
The serial interface is SPI compatible. Eight bits of digital I/O
are also provided that can be used for input or output. The
ADS1217 is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh
scales, chromatography, and portable instrumentation.
AGND
RDAC
AVDD
IDAC2
8-Bit
IDAC
IDAC1
8-Bit
IDAC
VREFOUT
VRCAP
VREF+ VREF–
XIN
XOUT
Clock Generator
Voltage
Reference
Offset
DAC
PDWN
DYSNC
AIN0
RESET
AIN1
AIN2
AIN3
MUX
BUF
AIN4
+
PGA
2nd-Order
Modulator
AIN5
Programmable
Digital
Filter
Controller
Registers
RAM
AIN6
AIN7
POL
AINCOM
SCLK
Serial Interface
Digital I/O
Interface
DIN
DOUT
CS
DRDY
BUFEN
DVDD
DGND
D0
... D7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
AVDD to AGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
AIN ................................................................... GND –0.5V to AVDD + 0.5V
AVDD to DVDD ........................................................................... –6V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND .................................... –0.3V to DVDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
TQFP-48
PFB
–40°C to +85°C
ADS1217
"
"
"
"
ADS1217IPFBT
ADS1217IPFBR
Tape and Reel, 250
Tape and Reel, 2000
ADS1217
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V,
unless otherwise specified.
ADS1217
PARAMETER
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Full-Scale Input Voltage
Analog Input Voltage
Differential Input Impedance
Input Current
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
Programmable Gain Amplifier
Burnout Current Sources
CONDITIONS
MIN
Offset Error
Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection
Normal-Mode Rejection
Output Noise
Power-Supply Rejection
MAX
±2VREF /PGA
(AIN+) – (AIN–)
Buffer OFF
Buffer ON
Buffer OFF
Buffer ON
–3dB
–3dB
–3dB
User Selectable Gain Ranges
10/PGA
0.5
0.469fDATA
0.318fDATA
0.262fDATA
Hz
Hz
Hz
AVDD + 0.1
AVDD – 1.5
1
128
2
µA
±VREF /(PGA)
V
Bits
%
ppm/°C
8
±1
1
24
Sinc3 Filter
End Point Fit, Differential Input,
Buffer Off
Before Calibration
0.0003
24
0.0012
7.5
0.02
0.005
0.5
After Calibration
at DC
fCM = 60Hz, fDATA = 10Hz
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
fSIG = 50Hz, fDATA = 50Hz
fSIG = 60Hz, fDATA = 60Hz
100
at DC, dB = –20log(∆VOUT /∆VDD)(2)
80
UNITS
V
V
V
MΩ
nA
AGND – 0.1
AGND + 0.05
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Nonlinearity
TYP
130
120
120
100
100
See Typical Characteristics
95
Bits
Bits
% of FSR(1)
ppm of FSR
ppm of FSR/°C
%
ppm/°C
dB
dB
dB
dB
dB
dB
dB
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1217
2
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SBAS260C
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V,
unless otherwise specified.
ADS1217
PARAMETER
VOLTAGE REFERENCE INPUT
Reference Input (VREF)
Negative Reference Input (VREF–)
Positive Reference Input (VREF+)
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Short-Circuit Current Source
Short-Circuit Current Sink
Drift
Noise
Output Impedance
Startup Time
IDAC
Full-Scale Output Current
Current Setting Resistance (RDAC)
Monotonicity
Compliance Voltage
Output Impedance
PSRR
Gain Error
Gain Error Drift
Gain Error Mismatch
Gain Error Mismatch Drift
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current (IADC + IVREF + IIDAC)
A/D Converter Current (IADC)
VREF Current (IVREF)
IIDAC Current (IIDAC)
Digital Current
Power Dissipation
CONDITIONS
MIN
TYP
MAX
UNITS
VREF ≡ (VREF+) – (VREF–)
0.1
AGND – 0.1
(VREF–) + 0.1
2.5
2.6
(VREF+) – 0.1
AVDD + 0.1
V
V
V
dB
dB
µA
2.6
V
V
mA
µA
ppm/°C
µVrms
Ω
ms
at DC
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 2.5V, PGA = 1
REF HI = 1
REF HI = 0
120
120
1.3
2.4
VRCAP = 0.1µF, BW = 0.1Hz to 100Hz
Sourcing 100µA
RDAC = 150kΩ, Range = 1
RDAC = 150kΩ, Range = 2
RDAC = 150kΩ, Range = 3
RDAC = 15kΩ, Range = 3
2.5
1.25
8
50
15
10
3
5
0.5
1
2
20
10
8
0
RDAC = 150kΩ
VOUT = AVDD/2, Code > 16
Individual IDAC
Individual IDAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
AVDD – 1
See Typical Characteristics
400
5
75
0.25
15
4.75
mA
mA
mA
mA
kΩ
Bits
V
ppm/V
%
ppm/°C
%
ppm/°C
5.25
V
nA
µA
µA
µA
µA
µA
µA
Excludes Load Current
1
175
500
250
900
250
480
Normal Mode, DVDD = 5V
SLEEP Mode, DVDD = 5V
Read Data Continuous Mode, DVDD = 5V
PDWN = 0
180
150
230
1
275
µA
µA
µA
nA
PGA = 1, Buffer OFF, REFEN = 0,
IDACs OFF, DVDD = 5V
1.8
2.8
mW
275
750
350
1375
375
675
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1217
SBAS260C
www.ti.com
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V,
unless otherwise specified.
ADS1217
PARAMETER
CONDITIONS
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Full-Scale Input Voltage
Analog Input Range
Input Impedance
Input Current
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
Programmable Gain Amplifier
Burnout Current Sources
MIN
Offset Error
Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection
Normal-Mode Rejection
Output Noise
Power-Supply Rejection
VOLTAGE REFERENCE INPUT
Reference Input (VREF)
Negative Reference Input (VREF–)
Positive Reference Input (VREF+)
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Short-Circuit Current Source
Short-Circuit Current Sink
Drift
Noise
Output Impedance
Startup Time
IDAC
Full-Scale Output Current
Current Setting Resistance (RDAC)
Monotonicity
Compliance Voltage
Output Impedance
PSRR
Gain Error
Gain Error Drift
Gain Error Mismatch
Gain Error Mismatch Drift
MAX
±2VREF /PGA
(AIN+) – (AIN–)
Buffer OFF
Buffer ON
Buffer OFF
Buffer ON
–3dB
–3dB
–3dB
User Selectable Gain Ranges
10/ PGA
0.5
0.469fDATA
0.318fDATA
0.262fDATA
Hz
Hz
Hz
AVDD + 0.1
AVDD – 1.5
1
128
2
µA
±VREF /(PGA)
V
Bits
%
ppm/°C
8
±1
2
24
Sinc3 Filter
End Point Fit, Differential Input,
Buffer Off, T = 25°C
Before Calibration
at DC
60Hz, fDATA =
50Hz, fDATA =
60Hz, fDATA =
50Hz, fDATA =
60Hz, fDATA =
15
0.04
0.010
1.0
130
120
120
100
100
See Typical Characteristics
90
75
VREF ≡ (VREF+) – (VREF–)
0.1
AGND – 0.1
(VREF–) + 0.1
at DC
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 1.25V
REF HI = 0
75kΩ,
75kΩ,
75kΩ,
15kΩ,
1.2
Range
Range
Range
Range
=
=
=
=
1
2
3
3
1.3
(VREF+) – 0.1
AVDD + 0.1
V
V
V
dB
dB
µA
1.3
V
mA
µA
ppm/°C
µVrms
Ω
ms
1.25
3
50
15
10
3
5
0.5
1
2
20
10
8
0
RDAC = 75kΩ
VOUT = AVDD /2, Code > 16
Individual IDAC
Individual IDAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
dB
120
120
0.65
VRCAP = 0.1µF, BW = 0.1Hz to 100Hz
Sourcing 100µA
=
=
=
=
1.25
Bits
Bits
% of FSR(1)
ppm of FSR
ppm of FSR/°C
%
ppm/°C
dB
dB
dB
dB
dB
dB
100
10Hz
50Hz
60Hz
50Hz
60Hz
at DC, dB = –20 log(∆VOUT /∆VDD)(2)
RDAC
RDAC
RDAC
RDAC
24
0.0012
0.0003
After Calibration
fCM =
fCM =
fCM =
fSIG =
fSIG =
UNITS
V
V
V
MΩ
nA
AGND – 0.1
AGND + 0.05
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Nonlinearity
TYP
AVDD – 1
See Typical Characteristics
600
5
75
0.25
15
mA
mA
mA
mA
kΩ
Bits
V
ppm/V
%
ppm/°C
%
ppm/°C
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1217
4
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SBAS260C
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V,
unless otherwise specified.
ADS1217
PARAMETER
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current (IADC + IVREF + IIDAC)
A/D Converter Current (IADC)
VREF Current (IVREF)
IIDAC Current (IIDAC)
Digital Current
Power Dissipation
CONDITIONS
MIN
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
2.7
TYP
1
160
450
230
850
250
480
Excludes Load Current
Normal Mode, DVDD = 3V
SLEEP Mode, DVDD = 3V
Read Data Continuous Mode, DVDD = 3V
PDWN = 0
PGA = 1, Buffer OFF, REFEN = 0,
IDACs OFF, DVDD = 3V
MAX
UNITS
3.3
V
nA
µA
µA
µA
µA
µA
µA
250
700
325
1325
375
675
1.4
µA
µA
µA
nA
mW
MAX
UNITS
DVDD
0.2 × DVDD
90
75
113
1
0.8
200
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ELECTRICAL CHARACTERISTICS: Digital
All specifications at –40°C to +85°C, and DVDD = +2.7V to 5.25V.
PARAMETER
INPUT/OUTPUT
Logic Level
VIH
VIL(1)
VOH
VOL
Input Leakage: IIN
CLOCK RATES
Master Clock Rate: fOSC
Master Clock Period: tOSC
CONDITIONS
MIN
TYP
IOH = 1mA
IOL = 1mA
0 < VI < DVDD
0.8 × DVDD
DGND
DVDD – 0.4
DGND
–10
DGND + 0.4
10
V
V
V
V
µA
1/fOSC
1
125
8
1000
MHz
ns
NOTE: (1) Maximum VIL for XIN is DGND + 0.05V.
ADS1217
SBAS260C
www.ti.com
5
PIN CONFIGURATION
DIN
SCLK
CS
DRDY
DVDD
DGND
DSYNC
POL
PDWN
XOUT
XIN
TQFP
DOUT
Top View
36
35
34
33
32
31
30
29
28
27
26
25
D0 37
24 RESET
D1 38
23 BUFEN
D2 39
22 DGND
D3 40
21 DGND
D4 41
20 DGND
D5 42
19 DGND
ADS1217
D6 43
18 DGND
D7 44
17 RDAC
5
6
7
8
9
10
11
12
AGND
4
AINCOM
3
AIN7
2
AIN4
1
AIN6
13 AVDD
AIN5
VREF– 48
AIN3
14 VRCAP
AIN2
VREF+ 47
AIN1
15 IDAC1
AIN0
VREFOUT 46
AGND
16 IDAC2
AVDD
AGND 45
PIN DESCRIPTIONS
PIN
NUMBER
NAME
Analog Power Supply
25
XIN
AGND
Analog Ground
26
XOUT
Clock Output, used with crystal or resonator.
AIN0
Analog Input 0
27
PDWN
4
AIN1
Analog Input 1
5
AIN2
Analog Input 2
Active LOW. Power Down. The power-down
function shuts down the analog and digital
circuits.
6
AIN3
Analog Input 3
7
AIN4
Analog Input 4
8
AIN5
Analog Input 5
9
AIN6
Analog Input 6
PIN
NUMBER
NAME
DESCRIPTION
1
AVDD
2
3
10
AIN7
11
AINCOM
Analog Input Common
12
AGND
Analog Ground
13
AVDD
Analog Power Supply
VRCAP
VREFOUT Bypass Capacitor
15
IDAC1
Current DAC1 Output
16
IDAC2
Current DAC2 Output
14
17
RDAC
18-22
DGND
Analog Input 7
Current DAC Resistor
Digital Ground
23
BUFEN
Buffer Enable Input
24
RESET
Active LOW, resets the entire chip.
DESCRIPTION
Clock Input
28
POL
29
DSYNC
Serial Clock Polarity Input
Active LOW, Synchronization Control Input
30
DGND
Digital Ground
31
DVDD
Digital Power Supply
32
DRDY
Active LOW, Data Ready Output
33
CS
34
SCLK
35
DIN
36
DOUT
37-44
D0-D7
Active LOW, Chip Select Input
Serial Clock, Schmitt Trigger
Serial Data Input, Schmitt Trigger
Serial Data Output
Digital I/O 0-7
45
AGND
46
VREFOUT
Analog Ground
47
VREF+
Positive Differential Reference Input
48
VREF–
Negative Differential Reference Input
Voltage Reference Output
ADS1217
6
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SBAS260C
TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t4
DIN
MSB
t2
t6
t5
t11
LSB
(Command or Command and Data)
t7
DOUT
t8
MSB(1)
t9
LSB(1)
NOTE: (1) Bit Order = 0.
ADS1217
Resets On
Falling Edge
SCLK Reset Waveform
t13
t13
SCLK
t12
t14
t15
t16
t17
RESET, DSYNC, PDWN
DRDY
TIMING CHARACTERISTICS
SPEC
DESCRIPTION
MIN
t1
SCLK Period
t2
t3
t4
t5
t6
SCLK Pulse Width, HIGH and LOW
CS LOW to First SCLK Edge; Setup Time(1)
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
Delay Between Last SCLK Edge for DIN and First SCLK
Edge for DOUT:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM
CSREG, CSRAMX, CSRAM
CSARAM, CSARAMX
SCLK Edge to Valid New DOUT
SCLK Edge to DOUT, Hold Time
Last SCLK Edge to DOUT Tri-State
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
CS LOW Time After Final SCLK Edge
Final SCLK Edge of One Op Code Until First Edge SCLK
of Next Command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA,
RDATAC, STOPC
CREG, CRAM
CREGA
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (Input pin, command, or SCLK pattern)
MAX
4
3
t7(2)
t8(2)
t9
t10
t11
t12
t13
t14
t15
t16
t17
Pulse Width
Data Not Valid
200
0
50
50
50
200
1100
50
0
6
10
0
UNITS
tOSC Periods
DRDY Periods
ns
ns
ns
ns
tOSC Periods
tOSC Periods
tOSC Periods
ns
ns
tOSC Periods
ns
tOSC Periods
4
220
1600
7
14
16
300
5
550
1050
4
4
500
750
1250
tOSC Periods
tOSC Periods
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
NOTES: (1) CS may be tied LOW. (2) Load = 20pF.
ADS1217
SBAS260C
www.ti.com
7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
22
PGA2
PGA4
21
20
19
18
PGA128
PGA64
PGA32
17
ENOB (rms)
ENOB (rms)
PGA1
20
19
PGA16
16
18
17
PGA32
14
PGA16
14
Sinc3 Filter, BUFFER OFF
Sinc3 Filter, BUFFER ON
13
13
12
12
0
500
1000
1500
Decimation Ratio =
2000
0
500
fMOD
22
PGA1
PGA4
PGA2
2000
fDATA
22
PGA8
PGA4
PGA2
20
20
19
19
ENOB (rms)
21
18
PGA64
PGA16
1500
fMOD
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
21
17
1000
Decimation Ratio =
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
ENOB (rms)
PGA128
PGA64
16
15
15
PGA32
PGA128
16
PGA8
PGA1
18
17
16
PGA32
PGA128
PGA64
15
15
PGA16
14
14
Sinc3 Filter, VREF = 1.25V, BUFFER OFF
13
13
Sinc3 Filter, VREF = 1.25V, BUFFER ON
12
12
0
500
1000
1500
Decimation Ratio =
0
2000
500
1000
1500
2000
Decimation Ratio
fMOD
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
22
22
PGA2
21
PGA4
PGA8
21
PGA1
20
20
19
19
ENOB (rms)
ENOB (rms)
PGA8
PGA4
PGA2
21
PGA8
PGA1
18
17
PGA32
PGA16
PGA64
PGA128
16
15
18
17
16
15
14
14
Sinc2 Filter
13
Fast Settling Filter
13
12
12
0
500
1000
Decimation Ratio =
1500
2000
fMOD
0
500
1000
Decimation Ratio =
fDATA
1500
2000
fMOD
fDATA
ADS1217
8
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SBAS260C
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
COMMON-MODE REJECTION RATIO vs FREQUENCY
NOISE vs INPUT SIGNAL
0.7
0.5
CMRR (dB)
Noise (rms, ppm of FS)
0.6
0.4
0.3
0.2
0.1
0
–5
–4
–3
–2
–1
0
1
2
3
4
130
120
110
100
90
80
70
60
50
40
30
20
10
0
5
1
10
VIN (V)
1k
10k
100k
OFFSET vs TEMPERATURE
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
140
120
PGA128
100
Offset (ppm of FS)
PSRR (dB)
100
Frequency of CM Signal (Hz)
80
60
PGA64
40
PGA1
20
0
PGA16
–20
–40
1
10
100
1k
10k
100k
–50
0
50
100
Temperature (°C)
Frequency of Power Supply (Hz)
GAIN vs TEMPERATURE
INTEGRAL NONLINEARITY vs INPUT SIGNAL
1.00010
6
1.00006
4
INL (ppm of FS)
Gain (Normalized)
–40°C
1.00002
0.99998
0.99994
2
0
+25°C
–2
0.99990
–4
0.99986
–6
+85°C
–50
–30
–10
10
30
50
70
90
–5
Temperature (°C)
–3
–2
–1
0
1
2
3
4
5
VIN (V)
ADS1217
SBAS260C
–4
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9
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
CURRENT vs TEMPERATURE
A/D CURRENT vs PGA
270
900
AVDD = 5V, Buffer = ON
800
600
IADC (µA)
Current (µA)
Buffer = OFF
700
240
IANALOG
210
500
AVDD = 3V, Buffer = ON
400
Buffer = OFF
300
180
200
100
IDIGITAL
150
0
–60
–30
0
30
60
90
120
1
2
4
Temperature (°C)
DIGITAL CURRENT
16
32
64
128
HISTOGRAM OF OUTPUT DATA
5000
400
Number of Occurrences
Normal
4.91MHz
350
300
Current (µA)
8
PGA Setting
250
Normal
2.45MHz
200
SLEEP
4.91MHz
150
100
SLEEP
2.45MHz
50
0
4000
3000
2000
1000
0
2.5
3.0
3.5
4.0
4.5
5
5.5
–2.0
–1.5
–1.0 –0.5
VDD (V)
0
0.5
1.0
1.5
2.0
ppm of FS
VREFOUT vs LOAD CURRENT
OFFSET DAC: OFFSET vs TEMPERATURE
200
2.55
170
Offset (ppm of FSR)
VREFOUT (V)
140
2.50
110
80
50
20
–10
–40
–70
2.45
–0.5
–100
0
0.5
1.0
1.5
2.0
–50
2.5
–30
–10
10
30
50
70
90
Temperature (°C)
VREFOUT Current Load (mA)
ADS1217
10
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SBAS260C
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
OFFSET DAC: GAIN vs TEMPERATURE
IDAC IOUT vs VOUT
1.00020
1.0000
1.00016
+85°C
1.000
1.00008
IOUT (Normalized)
Normalized Gain
1.00012
1.00004
1.00000
0.99996
0.99992
0.99988
+25°C
0.999
0.999
0.99984
–40°C
0.99980
0.99976
–50
–30
–10
10
30
50
70
0.998
90
0
1
2
Temperature (°C)
3
4
5
VDD – VOUT (V)
IDAC NORMALIZED IOUT vs TEMPERATURE
IDAC MATCHING vs TEMPERATURE
1.010
3000
2000
1000
IDAC Match (ppm)
IOUT (Normalized)
1.005
1.000
0.995
0
–1000
–2000
–3000
–4000
0.990
–5000
0.985
–6000
–30
–10
10
30
50
70
90
–50
–30
–10
10
30
50
70
Temperature (°C)
Temperature (°C)
IDAC DIFFERENTIAL NONLINEARITY
(Range = 1, RDAC = 150kΩ, VREF = 2.5V)
IDAC INTEGRAL NONLINEARITY
(Range = 1, RDAC = 150kΩ, VREF = 2.5V)
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
INL (LSB)
DNL (LSB)
–50
0.1
0
–0.1
90
0.1
0
–0.1
–0.2
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0
32
64
96
128
160
192
224
0
255
ADS1217
SBAS260C
32
64
96
128
160
192
224
255
IDAC Code
IDAC Code
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11
OVERVIEW
BURNOUT CURRENT SOURCES
INPUT MULTIPLEXER
The input multiplexer (mux) provides for any combination of
differential inputs to be selected on any of the input channels,
as shown in Figure 1. If channel 1 is selected as the positive
differential input channel, any other channel can be selected
as the negative differential input channel. With this method,
it is possible to have up to eight fully differential input
channels.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.
AIN0
AIN1
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2µA of current.
The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open circuit
(full-scale reading) or short circuit (0V differential reading) on
the selected input differential pair.
INPUT BUFFER
The input impedance of the ADS1217 without the buffer
is 10MΩ/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the buffer pin with
the state of the BUFFER bit in the ACR register. See Application Report Input Currents for High-Resolution ADCs
(SBAA090) for more information.
IDAC1 AND IDAC2
AVDD
The ADS1217 has two 8-bit current output DACs that can
be controlled independently. The output current is set with
RDAC, the range select bits in the ACR register, and the
8-bit digital value in the IDAC register. The output
current = (VREF/8RDAC) (2RANGE–1) (DAC CODE). With
VREFOUT = 2.5V and RDAC = 150kΩ, the full-scale output can
be selected to be 0.5, 1, or 2mA. The compliance voltage
range is AGND to within 1V of AV DD. When the internal
voltage reference of the ADS1217 is used, it is the reference for the IDAC. An external reference may be used for
the IDACs by disabling the internal reference and tying the
external reference input to the VREFOUT pin.
Burnout Current Source On
AIN2
AIN3
AIN+
AIN4
AIN–
AIN5
Burnout Current Source On
PGA
AIN6
AGND
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can improve the effective resolution of the A/D
converter. For instance, with a PGA of 1 on a 10V full-scale
range, the A/D converter can resolve to 2µV. With a PGA of
128 on a 80mV full-scale range, the A/D converter can resolve
to 150nV.
IDAC1
AIN7
AINCOM
PGA OFFSET DAC
FIGURE 1. Input Multiplexer Configuration.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to all
1s, the diode is connected to the input of the A/D converter.
All other channels are open. The anode of the diode is
connected to the positive input of the A/D converter, and the
cathode of the diode is connected to negative input of the
A/D converter. The output of IDAC1 is connected to the
anode to bias the diode and the cathode of the diode is also
connected to ground to complete the circuit.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode. See Application Report
Measuring Temperature with the ADS1216, ADS1217, or
ADS1218 (SBAA073) for more information.
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign and
the seven LSBs provide the magnitude of the offset. Using the
ODAC does not reduce the performance of the A/D converter.
See Application Report The Offset DAC (SBAA077) for more
information.
MODULATOR
The modulator is a single-loop, 2nd-order system. The modulator runs at a clock speed (fMOD) that is derived from the
external clock (fOSC). The frequency division is determined by
the SPEED bit in the setup register.
SPEED BIT
fMOD
0
1
fOSC /128
fOSC / 256
ADS1217
12
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SBAS260C
VOLTAGE REFERENCE INPUT
The ADS1217 uses a differential voltage reference input.
The input signal is measured against the differential voltage
VREF ≡ (VREF+) – (VREF–). For AVDD = 5V, VREF is typically
2.5V. For AVDD = 3V, VREF is typically 1.25V. Due to the
sampling nature of the modulator, the reference input current
increases with higher modulator clock frequency (fMOD) and
higher PGA settings.
ON-CHIP VOLTAGE REFERENCE
A selectable voltage reference (1.25V or 2.5V) is available for
supplying the voltage reference input. To use, connect VREF–
to AGND and VREF+ to VREFOUT. The enabling and voltage
selection are controlled through bits REF EN and REF HI in
the setup register. The 2.5V reference requires AVDD = 5V.
When using the on-chip voltage reference, the VREFOUT pin
should be bypassed with a 0.1µF capacitor to AGND.
VRCAP PIN
This pin provides a bypass cap for noise filtering on internal
VREF circuitry only. As this is a sensitive pin, place the
capacitor as close as possible and avoid any resistive loading. The recommended capacitor is a 0.001µF ceramic cap.
If an external VREF is used, this pin can be left unconnected.
CLOCK GENERATOR
The clock source for the ADS1217 can be provided from a
crystal, oscillator, or external clock. When the clock source is
a crystal, external capacitors must be provided to ensure startup and a stable clock frequency; see Figure 2 and Table I.
XIN
C1
complete both an offset and gain calibration. Self-gain calibration is optimized for PGA gains less than 8. When using
higher gains, system gain calibration is recommended.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“zero” differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive “full-scale” differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven tDATA periods to complete.
Calibration must be performed after power on, a change in
decimation ratio, or a change of the PGA. For operation with
a reference voltage greater than (AVDD – 1.5V), the buffer
must also be turned off during calibration.
At the completion of calibration, the DRDY signal goes LOW,
which indicates the calibration is finished and valid data is
available. See Application Report Calibration Routine and
Register Value Generation for the ADS121x Series (SBAA099)
for more information.
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc2, or
sinc3 filter, as shown in Figure 3. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
fast settling filter; It will then use the sinc2 followed by the
sinc3 filter. This combines the low-noise advantage of the
sinc3 filter with the quick response of the fast settling time
filter. See Figure 4 for the frequency response of each filter.
When using the fast setting filter, select a decimation value
set by the DEC0 and M/DEC1 registers that is evenly
divisible by four for the best gain accuracy. For example,
choose 260 rather than 261.
Crystal
Adjustable Digital Filter
XOUT
C2
Sinc3
FIGURE 2. Crystal Connection.
Modulator
Output
CLOCK
SOURCE
FREQUENCY
C1
C2
PART
NUMBER
Crystal
2.4576
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSL 4.91
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSD 4.91
Crystal
4.9152
0-20pF
0-20pF
CTS, MP 042 4M9182
Data Out
Fast Settling
FILTER SETTLING TIME
FILTER
SETTLING TIME
(Conversion Cycles)
Sinc3
Sinc2
Fast
3
2
1
TABLE I. Typical Clock Sources.
CALIBRATION
The offset and gain errors in the ADS1217, or the complete
system, can be reduced with calibration. Internal calibration
of the ADS1217 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven tDATA periods to complete. It takes 14 tDATA periods to
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
1
2
3
4+
Fast
Sinc2
Sinc3
Sinc3
FIGURE 3. Filter Step Responses.
ADS1217
SBAS260C
Sinc2
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13
SINC2 FILTER RESPONSE(1)
(–3dB = 0.318 • fDATA = 19.11Hz)
0
0
–20
–20
–40
–40
Gain (dB)
Gain (dB)
SINC3 FILTER RESPONSE(1)
(–3dB = 0.262 • fDATA = 15.76Hz)
–60
–60
–80
–80
–100
–100
–120
–120
0
30
60
90
120
150 180
210 240 270 300
0
30
60
90
Frequency (Hz)
120
150 180
210 240 270 300
Frequency (Hz)
FAST SETTLING FILTER RESPONSE(1)
(–3dB = 0.469 • fDATA = 28.125Hz)
0
–20
Gain (dB)
–40
–60
–80
–100
–120
0
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
NOTE: (1) fDATA = 60Hz.
FIGURE 4. Filter Frequency Responses.
DIGITAL I/O INTERFACE
The ADS1217 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as inputs.
All of the digital I/O pins are individually configurable as inputs
or outputs. They are configured through the DIR control register. The DIR register defines whether the pin is an input or
output, and the DIO register defines the state of the digital
output. When the digital I/O are configured as inputs, DIO is
used to read the state of the pin. If the digital I/O are not used,
either 1) configure as outputs; or, 2) leave as inputs and tie to
ground, this prevents excess power dissipation.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1217. The ADS1217
operates in slave only mode.
back with no delay in SCLKs or toggling of CS . Make sure
to avoid glitches on SCLK as they can cause extra shifting of
the data.
Polarity (POL)
The serial clock polarity is specified by the POL input. When
SCLK is active HIGH, set POL HIGH. When SCLK is active
LOW, set POL LOW.
DATA READY
The DRDY output is used as a status signal to indicate when
data is ready to be read from the ADS1217. DRDY goes LOW
when new data is available. It is reset HIGH when a read
operation from the data register is complete. It also goes HIGH
prior to the updating of the output register to indicate when not
to read from the device to ensure that a data read is not
attempted while the register is being updated.
Chip Select (CS )
The chip select (CS ) input of the ADS1217 must be externally asserted before a master device can exchange data
with the ADS1217. CS must be LOW for the duration of the
transaction. CS can be tied low.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input, clocks data transfer on the DIN
input and DOUT output. When transferring data to or from the
ADS1217, multiple bits of data may be transferred back-to-
DSYNC OPERATION
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the DSYNC pin or the DSYNC
command. When the DSYNC pin is used, the filter counter is
reset on the falling edge of DSYNC. The modulator is held in
reset until DSYNC is taken HIGH. Synchronization occurs on
the next rising edge of the system clock after DSYNC is
taken HIGH.
ADS1217
14
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SBAS260C
When the DSYNC command is sent, the filter counter is reset
on the edge of the last SCLK on the DSYNC command. The
modulator is held in reset until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command. After a DSYNC operation, DRDY is held HIGH
until valid data is ready.
Configuration
Registers
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RESET
There are three methods to reset the ADS1217: the RESET
input, the RESET command, and a special SCLK input pattern. When using the RESET input, take it LOW to force a
reset. Make sure to follow the minimum pulse width timing
specifications before taking the RESET input back high. Also,
avoid glitches on the RESET input as these may cause
accidental resets. The RESET command takes effect after all
8 bits have been shifted into DIN. Afterwards, the reset
releases automatically. The ADS1217 can also be reset with
a special pattern on SCLK, see the Timing Diagram. Reset
occurs on the falling edge of the last SCLK edge in the pattern
(for POL = 0). Afterwards, the reset releases automatically.
RAM
128 Bytes
Bank 0
16 bytes
Bank 2
16 bytes
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically.
Bank 7
16 bytes
MEMORY
Two types of memory are used on the ADS1217: registers
and RAM. 16 registers directly control the various functions
(PGA, DAC value, Decimation Ratio, etc.) and can be directly
read or written. Collectively, the registers contain all the
information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio,
etc. Additional registers, such as output data, are accessed
through dedicated instructions.
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers;
that is, the RAM can be used as general-purpose RAM.
The ADS1217 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations—one per input channel. In order
to facilitate this type of usage, eight separate register banks
are available. Therefore, each configuration could be written
once and recalled as needed without having to serially
retransmit all the configuration data. Checksum commands
are also included, which can be used to verify the integrity of
RAM.
FIGURE 5. Memory Organization.
The RAM provides eight “banks”, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively without having to address each bank individually. For example,
if you were currently accessing bank 0 at offset 0FH (the last
location of bank 0), the next access would be bank 1 and
offset 00H. Any access after bank 7 and offset 0FH will wrap
around to bank 0 and Offset 00H.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of
bank and offset addressing. Looking at linear and bank
addressing syntax, we have the following comparison: in the
linear memory map, the address 14H is equivalent to bank
1 and offset 04H. Simply stated, the most significant four bits
represent the bank, and the least significant four bits represent the offset. The offset is equivalent to the register
address for that bank of memory.
ADS1217
SBAS260C
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15
REGISTER MAP
ADDRESS
REGISTER
BIT 7
00H
SETUP
ID
01H
MUX
PSEL3
02H
ACR
BOCS
03H
IDAC1
04H
05H
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ID
ID
SPEED
REF EN
REF HI
BUF EN
BIT ORDER
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
IDAC2R1
IDAC2R0
IDAC1R1
IDAC1R0
PGA2
PGA1
PGA0
IDAC1_7
IDAC1_6
IDAC1_5
IDAC1_4
IDAC1_3
IDAC1_2
IDAC1_1
IDAC1_0
IDAC2
IDAC2_7
IDAC2_6
IDAC2_5
IDAC2_4
IDAC2_3
IDAC2_2
IDAC2_1
IDAC2_0
ODAC
SIGN
OSET_6
OSET_5
OSET_4
OSET_3
OSET_2
OSET_1
OSET_0
06H
DIO
DIO_7
DIO_6
DIO_5
DIO_4
DIO_3
DIO_2
DIO_1
DIO_0
07H
DIR
DIR_7
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
08H
DEC0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
09H
M/DEC1
DRDY
U/B
SMODE1
SMODE0
Reserved
DEC10
DEC09
DEC08
0AH
OCR0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
0BH
OCR1
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
0CH
OCR2
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
0DH
FSR0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
0EH
FSR1
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
0FH
FSR2
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
TABLE II. Registers.
DETAILED REGISTER DEFINITIONS
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
SETUP (Address 00H) Setup Register
Reset Value = iii01110
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
ID
ID
ID
SPEED
REF EN
REF HI
bit 1
bit 0
BUF EN BIT ORDER
bit 7-5
Factory Programmed Bits
bit 4
SPEED: Modulator Clock Speed
0 : fMOD = fOSC /128 (default)
1 : fMOD = fOSC /256
bit 3
REF EN: Internal Voltage Reference Enable
0 = Internal Voltage Reference Disabled
1 = Internal Voltage Reference Enabled (default)
bit 2
REF HI: Internal Reference Voltage Select
0 = Internal Reference Voltage = 1.25V
1 = Internal Reference Voltage = 2.5V (default)
bit 1
BUF EN: Buffer Enable
0 = Buffer Disabled
1 = Buffer Enabled (default)
bit 0
BIT ORDER: Set Order Bits are Transmitted
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted into the part most significant
bit first. Data is always shifted out of the part most
significant byte first. This configuration bit only controls the bit order within the byte of data that is
shifted out.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7-4
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1s)
1111 = Temperature Sensor Diode
bit 3-0
NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1s)
1111 = Temperature Sensor Diode
ADS1217
16
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SBAS260C
ACR (Address 02H) Analog Control Register
Reset Value = 00H
bit 7
BOCS
bit 7
bit 6
bit 5
bit 4
IDAC2R1 IDAC2R0 IDAC1R1
ODAC (Address 05H) Offset DAC Setting
Reset Value = 00H
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IDAC1R0
PGA2
PGA1
PGA0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
(
bit 7
1 = Negative
)
VREF RANGE−1
(DAC Code)
IDAC Current =
2
8RDAC
bit 6-5
bit 4-3
bit 2-0
bit 6-0
IDAC2R1: IDAC2R0: Full-Scale Range Select for
IDAC2
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
IDAC1R1: IDAC1R0: Full-Scale Range Select for
IDAC1
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
IDAC1 (Address 03H) Current DAC 1
Reset Value = 00H
bit 7
bit 6
IDAC1_7
IDAC1_6
bit 5
bit 4
IDAC1_5 IDAC1_4
bit 3
Offset Sign
0 = Positive
Offset =
VREF Code
•
PGA 127
NOTE: The offset must be used after calibration or the
calibration will notify the effects.
DIO (Address 06H) Digital I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
A value written to this register will appear on the digital
I/O pins if the pin is configured as an output in the DIR
register. Reading this register will return the value of the
digital I/O pins.
DIR (Address 07H) Direction control for digital I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Each bit controls whether the Digital I/O pin is an output
(= 0) or input (= 1). The default power-up state is as inputs.
DEC0 (Address 08H) Decimation Register
(Least Significant 8 bits)
Reset Value = 80H
bit 2
IDAC1_3 IDAC1_2
bit 1
bit 0
IDAC1_1
IDAC1_0
The DAC code bits set the output of DAC1 from 0 to fullscale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC1 range bits in the ACR register.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
The decimation value is defined with 11 bits for a range of 20
to 2047. This register is the least significant 8 bits. The 3
most significant bits are contained in the M/DEC1 register.
The default data rate is 10Hz with a 2.4576MHz crystal.
IDAC2 (Address 04H) Current DAC 2
Reset Value = 00H
bit 7
bit 6
IDAC2_7
IDAC2_6
bit 5
bit 4
IDAC2_5 IDAC2_4
bit 3
bit 2
IDAC1_3 IDAC1_2
bit 1
bit 0
IDAC1_1
IDAC1_0
The DAC code bits set the output of DAC2 from 0 to fullscale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC2 range bits in the ACR register.
ADS1217
SBAS260C
www.ti.com
17
M/DEC1 (Address 09H) Mode and Decimation Register
Reset Value = 07H
bit 7
bit 6
DRDY
U/B
bit 5
bit 4
SMODE1 SMODE0
bit 3
bit 2
bit 1
bit 0
Reserved
DEC10
DEC09
DEC08
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
U/B
DIGITAL OUTPUT
+FS
Zero
–FS
+FS
Zero
–FS
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
1
bit 5-4
bit 2-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
FSR0 (Address 0DH) Full-Scale Register
(Least Significant Byte)
Reset Value = 24H
ANALOG INPUT
0
OCR2 (Address 0CH) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
FSR1 (Address 0EH) Full-Scale Register
(Middle Byte)
Reset Value = 90H
SMODE1: SMODE0: Settling Mode
00 = Auto (default)
01 = Fast Settling filter
10 = Sinc2 filter
11 = Sinc3 filter
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR011
FSR10
FSR09
FSR08
FSR2 (Address 0FH) Full-Scale Register
(Most Significant Byte)
Reset Value = 67H
DEC10: DEC09: DEC08: Most Significant Bits of
the Decimation Value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR019
FSR18
FSR17
FSR16
OCR0 (Address 0AH) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR1 (Address 0BH) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
ADS1217
18
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SBAS260C
COMMAND DEFINITIONS
Operands:
The commands listed below control the operation of the
ADS1217. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four fOSC
cycles before the data is ready (e.g., RDATA).
COMMANDS
DESCRIPTION
RDATA
RDATAC
STOPC
RREG
RRAM
CREG
CREGA
WREG
WRAM
CRAM
CSRAMX
CSARAMX
CSREG
CSRAM
CSARAM
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC
SLEEP
RESET
Read Data
Read Data Continuously
Stop Read Data Continuously
Read from REG Bank rrrr
Read from RAM Bank aaa
Copy REGs to RAM Bank aaa
Copy REGS to all RAM Banks
Write to REG rrrr
Write to RAM Bank aaa
Copy RAM Bank aaa to REG
Calc RAM Bank aaa Checksum
Calc all RAM Bank Checksum
Calc REG Checksum
Calc RAM Bank aaa Checksum
Calc all RAM Banks Checksum
Self Cal Offset and Gain
Self Cal Offset
Self Cal Gain
Sys Cal Offset
Sys Cal Gain
Wake Up From Sleep Mode
Sync DRDY
Put in Sleep Mode
Reset to Power-Up Values
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
a = RAM bank address (0 to 7)
COMMAND BYTE
0000
0000
0000
0001
0010
0100
0100
0101
0110
1100
1101
1101
1101
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
1111
2ND COMMAND BYTE
0001 (01H)
0011 (03H)
1111 (0FH)
r r r r (1x H)
0aaa (2x H)
0aaa (4x H)
1000 (48H)
r r r r (5x H)
0aaa (6x H)
0aaa (CxH)
0aaa (DxH)
1000 (D8 H)
1111 (DFH)
0aaa (ExH)
1000 (E8H)
0000 (F0H)
0001 (F1H)
0010 (F2H)
0011 (F3H)
0100 (F4H)
1011 (FBH)
1100 (FCH)
1101 (FDH)
1110 (FE H)
—
—
—
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NOTE: (1) The data received by the A/D converter is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATA
Read Data
Description: Read a single 24-bit ADC conversion result. On
completion of read back, DRDY goes HIGH.
Operands:
None
Bytes:
1
Encoding:
0000 0001
Data Transfer Sequence:
DRDY
DIN
0000 0001
DOUT
• • •(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
MSB
Mid-Byte
LSB
RDATAC
Read Data Continuous
Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands:
None
Bytes:
1
Encoding:
0000 0011
Data Transfer Sequence:
Command terminated when uuuu uuuu equals STOPC
or RESET.
DIN
• • •(1)
0000 0011
uuuu uuuu
uuuu uuuu
uuuu uuuu
MSB
Mid-Byte
LSB
•••
DOUT
DRDY
•••
DIN
uuuu uuuu
uuuu uuuu
uuuu uuuu
MSB
Mid-Byte
LSB
•••
DOUT
NOTE: (1) For wait time, refer to timing specification.
ADS1217
SBAS260C
www.ti.com
19
STOPC
Stop Continuous
Description: Ends the continuous data output mode.
CREG
Copy Registers to RAM Bank
Operands:
None
Bytes:
1
Description: Copy the 16 control registers to the RAM bank
specified in the op code. Refer to timing specifications for
command execution time.
Encoding:
0000 1111
Operands:
a
Bytes:
1
Encoding:
0100 0aaa
Data Transfer Sequence:
DIN
Data Transfer Sequence:
Copy Register Values to RAM Bank 3
0000 1111
RREG
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte.
If the count exceeds the remaining registers, the addresses will
wrap back to the beginning.
Operands:
r, n
Bytes:
2
Encoding:
0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
DIN
DIN
Read from Registers
0001 0001
0000 0001
• • •(1)
DOUT
RRAM
xxxx xxxx
xxxx xxxx
MUX
ACR
CREGA
Description: Duplicate the 16 control registers to all the RAM
banks. Refer to timing specifications for command execution
time.
Operands:
None
Bytes:
1
Encoding:
0100 1000
DIN
Write to Register
Description: Write to the registers starting with the register
specified as part of the instruction. The number of registers that
will be written is one plus the value of the second byte.
Operands:
r, n
Bytes:
2
Encoding:
0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 06H (DIO)
Operands:
a, n
Bytes:
2
Encoding:
0010 0aaa xnnn nnnn
Data Transfer Sequence:
Read Two RAM Locations Starting from 20H
DOUT
0100 1000
WREG
Read from RAM
0010 0010
Copy Registers to All RAM Banks
Data Transfer Sequence:
Description: Up to 128 bytes can be read from RAM starting
at the bank specified in the op code. All reads start at the
address for the beginning of the RAM bank. The number of
bytes to read will be one plus the value of the second byte.
DIN
0100 0011
x000 0001
• • •(1)
DIN
xxxx xxxx
xxxx xxxx
RAM Data
20H
RAM Data
21H
0101 0110
xxxx 0001
Data for DIO
Data for DIR
NOTE: (1) For wait time, refer to timing specification.
ADS1217
20
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SBAS260C
WRAM
Write to RAM
Description: Write up to 128 RAM locations starting at the
beginning of the RAM bank specified as part of the instruction.
The number of bytes written is RAM is one plus the value of the
second byte.
Calculate the Checksum
for all RAM Banks
CSARAMX
Operands:
a, n
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY, and DIO bits are masked so they are
not included in the checksum.
Bytes:
2
Operands:
None
Encoding:
0110 0aaa xnnn nnnn
Bytes:
1
Encoding:
1101 1000
Data Transfer Sequence:
Write to Two RAM Locations starting from 10H
DIN
0110 0001
CRAM
x000 0001
Data for
10H
Data Transfer Sequence:
Data for
11H
DIN
Operands:
a
Bytes:
1
Encoding:
1100 0aaa
xxxx xxxx
Checksum
Calculate the Checksum
of Registers
CSREG
Description: Calculate the checksum of all the registers. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
DIN
• • •(1)
DOUT
Copy RAM Bank to Registers
Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers with the
data from the RAM bank.
1101 1000
1100 0000
Operands:
None
Bytes:
1
Encoding:
1101 1111
Data Transfer Sequence:
CSRAMX
Calculate RAM Bank Checksum
DIN
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes with
the carry ignored. The ID, DRDY, and DIO bits are masked so
they are not included in the checksum.
Operands:
a
Bytes:
1
Encoding:
1101 0aaa
DOUT
1101 0011
• • •(1)
• • •(1)
xxxx xxxx
Checksum
DOUT
CSRAM
Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes with
the carry ignored. All bits are included in the checksum
calculation, there is no masking of bits.
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
DIN
1101 1111
xxxx xxxx
Checksum
Operands:
a
Bytes:
1
Encoding:
1110 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 2
DIN
DOUT
1110 0010
• • •(1)
xxxx xxxx
Checksum
NOTE: (1) For wait time, refer to timing specification.
ADS1217
SBAS260C
www.ti.com
21
Calculate Checksum
for all RAM Banks
CSARAM
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. All bits are included in the checksum calculation, there
is no masking of bits.
SELFGCAL
Gain Self Calibration
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values after
this operation.
Operands:
None
Bytes:
1
Operands:
None
Encoding:
1111 0010
Bytes:
1
Data Transfer Sequence:
Encoding:
1110 1000
Data Transfer Sequence:
1111 0010
DIN
DIN
1110 1000
• • •(1)
xxxx xxxx
SYSOCAL
Checksum
DOUT
SELFCAL
Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Control Register (OCR) and the Full-Scale Register (FSR) are
updated with new values after this operation.
System Offset Calibration
Description: Starts the system offset calibration process. For
a system offset calibration the input should be set to 0V
differential, and the ADS1217 computes the OCR register
value that will compensate for offset errors. The Offset Control
Register (OCR) is updated after this operation.
Operands:
None
Bytes:
1
1111 0011
Operands:
None
Encoding:
Bytes:
1
Data Transfer Sequence:
Encoding:
1111 0000
Data Transfer Sequence:
DIN
DIN
1111 0011
1111 0000
SYSGCAL
System Gain Calibration
Description: Starts the process of self-calibration for offset.
The Offset Control Register (OCR) is updated after this operation.
Description: Starts the system gain calibration process. For
a system gain calibration, the differential input should be set to
the reference voltage and the ADS1217 computes the FSR
register value that will compensate for gain errors. The FSR is
updated after this operation.
Operands:
None
Operands:
None
Bytes:
1
Bytes:
1
1111 0001
Encoding:
1111 0100
SELFOCAL
Encoding:
Offset Self Calibration
Data Transfer Sequence:
Data Transfer Sequence:
DIN
DIN
1111 0001
1111 0100
NOTE: (1) For wait time, refer to timing specification.
ADS1217
22
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SBAS260C
WAKEUP Wakeup From Sleep Mode
Sync DRDY
DSYNC
Description: Synchronizes the ADS1217 to the serial clock
edge.
Description: Use this command to wake up from sleep mode.
Operands:
None
Operands:
None
Bytes:
1
Bytes:
1
Encoding:
1111 1011
Encoding:
1111 1100
Data Transfer Sequence:
Data Transfer Sequence:
1111 1011
DIN
1111 1100
DIN
RESET
SLEEP
Sleep Mode
Reset to Power-Up Values
Description: Restore the registers to their power-up values.
This command will also stop the Read Continuous mode. It
does not affect the contents of RAM.
Description: Puts the ADS1217 into a low power sleep mode.
SCLK must be inactive while in sleep mode. To exit this mode,
issue the WAKEUP command.
Operands:
None
Operands:
None
Bytes:
1
Bytes:
1
Encoding:
1111 1110
Encoding:
1111 1101
Data Transfer Sequence:
Data Transfer Sequence:
DIN
1111 1110
DIN
1111 1101
LSB
MSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
x
rdata
x
rdatac
x
x
x
x
x
x
x
x
x
x
x
stopc
0001
rreg
0
rreg
1
rreg
2
rreg
3
rreg
4
rreg
5
rreg
6
rreg
7
rreg
8
rreg
9
rreg
A
rreg
B
rreg
C
rreg
D
rreg
E
rreg
F
0010
rram
0
rram
1
rram
2
rram
3
rram
4
rram
5
rram
6
rram
7
x
x
x
x
x
x
x
x
0011
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0100
creg
0
creg
1
creg
2
creg
3
creg
4
creg
5
creg
6
creg
7
crega
x
x
x
x
x
x
x
0101
wreg
0
wreg
1
wreg
2
wreg
3
wreg
4
wreg
5
wreg
6
wreg
7
wreg
8
wreg
9
wreg
A
wreg
B
wreg
C
wreg
D
wreg
E
wreg
F
0110
wram
0
wram
1
wram
2
wram
3
wram
4
wram
5
wram
6
wram
7
x
x
x
x
x
x
x
x
0111
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1000
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1001
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1010
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1011
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1100
cram 0 cram 1
cram 2
cram 5 cram 6
cram 7
x
x
x
x
x
x
x
1101
csramx csramx
0
1
csramx csramx csramx csramx csramx
2
3
4
5
6
cram 3 cram 4
csramx
7
csa
ramx
x
x
x
x
x
x
csreg
1110
cs
ram 0
cs
ram 1
cs
ram2
cs
ram 3
cs
ram 4
cs
ram 5
cs
ram 6
cs
ram 7
csa
ram
x
x
x
x
x
x
x
1111
self
cal
self
ocal
self
gcal
sys
ocal
sys
gcal
x
x
x
x
x
x
wakeup
dsync
sleep
reset
x
x = Reserved
TABLE IV. Command Map.
ADS1217
SBAS260C
www.ti.com
23
DEFINITION OF TERMS
BITS rms
BIPOLAR Vrms
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
4VREF
PGA
Conversion Cycle—the term conversion cycle usually refers
to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used
here, a conversion cycle refers to the tDATA time period.
However, each digital output is actually based on the modulator results from several tDATA time periods.
FILTER SETTING
MODULATOR RESULTS
Fast Settling
1 tDATA Time Period
Sinc2
2 tDATA Time Period
Sinc3
3 tDATA Time Period
Data Rate—the rate at which conversions are completed.
See definition for fDATA.
Decimation Ratio—defines the ratio between the output of
the modulator and the output Data Rate. Valid values for the
Decimation Ratio are from 20 to 2047. Larger Decimation
Ratios will have lower noise.
The data from the A/D converter is output as codes, which
then can be easily converted to other units, such as ppm or
volts. The equations and table below show the relationship
between bits or codes, ppm, and volts.
ENOB =
–20 log(ppm)
6.02
6.02 • ENOB
20
10
10
24
596nV
298nV
22
2.38µV
1.19µV
4.77µV
20
9.54µV
18
38.1µV
19.1µV
16
153µV
76.4µV
14
610µV
305µV
12
2.44mV
1.22mV
fDATA—the frequency of the digital output data produced by
the ADS1217, fDATA is also referred to as the Data Rate.
fMOD
fOSC
fDATA =
=
Decimation
Ratio
mfactor
•
Decimation
Ratio
fMOD—the frequency or speed at which the modulator of the
ADS1217 is running. This depends on the SPEED bit as
shown below:
SPEED BIT
fMOD
0
1
fOSC /128
fOSC /256
fOSC—the frequency of the crystal input signal at the XIN input
of the ADS1217.
fSAMP—the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the following
equations:
PGA SETTING
Effective Resolution—the effective resolution of the
ADS1217 in a particular configuration can be expressed in
two different units: bits rms (referenced to output) and Vrms
(referenced to input). Computed directly from the converter’s
output data, each is a statistical calculation. The conversion
from one to the other is shown below.
Effective number of bits (ENOB) or effective resolution is
commonly used to define the usable resolution of the
A/D converter. It is calculated from empirical data taken
directly from the device. It is typically determined by applying
a fixed known signal source to the analog input and computing the standard deviation of the data sample set. The rms
noise defines the ±σ interval about the sample mean.
2VREF
PGA
6.02 • ENOB
20
Analog Input Differential Voltage—given by the following
equation: (AIN+) – (AIN–). Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differential is 2 • 2.5V. The negative full-scale output is produced
when the differential is 2 • (–2.5V). In each case, the actual
input voltages must remain within the AGND to AVDD range.
UNIPOLAR Vrms
SAMPLING FREQUENCY
1, 2, 4, 8
f SAMP =
fOSC
mfactor
8
f SAMP =
2fOSC
mfactor
16
f SAMP =
8fOSC
mfactor
32
f SAMP =
16fOSC
mfactor
64, 128
f SAMP =
16fOSC
mfactor
Filter Selection—the ADS1217 uses a (sinx /x) filter or sinc
filter. There are three different sinc filters that can be selected. A fast settling filter will settle in one tDATA cycle. The
sinc2 filter will settle in two cycles and have lower noise. The
sinc3 will achieve lowest noise and higher number of effective
bits, but requires three cycles to settle. The ADS1217 will
operate with any one of these filters, or it can operate in an
auto mode, where it will first select the fast settling filter after
a new channel is selected and will then switch to sinc2 for one
reading, followed by sinc3 from then on.
ADS1217
24
www.ti.com
SBAS260C
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1217 is defined as the “input”,
which produces the positive full-scale digital output minus the
“input”, which produces the negative full-scale digital output.
The full-scale range changes with gain setting, see Table V.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: 2 • [1.25V (positive full-scale) minus –1.25V (negative full-scale)] = 5V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
LSB Weight =
Full − Scale Range
2N
where N is the number of bits in the digital output.
tDATA—the inverse of fDATA, or the period between each data
output.
5V SUPPLY ANALOG INPUT(1)
GAIN SETTING
FULL-SCALE RANGE
1
10V
2
5V
DIFFERENTIAL
INPUT VOLTAGES(2)
GENERAL EQUATIONS
PGA OFFSET
RANGE
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
PGA SHIFT
RANGE
±5V
±2.5
±2.5V
±1.25V
4VREF
PGA
±2VREF
PGA
±VREF
PGA
4
2.5V
±1.25V
±0.625V
8
1.25V
±0.625V
±312.5mV
±156.25mV
16
0.625V
±312.5mV
32
312.5mV
±156.25mV
±78.125mV
64
156.25mV
±78.125mV
±39.0625mV
128
78.125mV
±39.0625mV
±19.531mV
NOTES: (1) With a 2.5V reference. (2) The ADS1217 allows common-mode voltage as long as the absolute input voltage on AIN+ or AIN– does not go below
AGND or above AVDD.
TABLE V. Full-Scale Range versus PGA Setting.
ADS1217
SBAS260C
www.ti.com
25
Revision History
DATE
REVISION
PAGE
SECTION
DESCRIPTION
2/07
C
2,4
Electrical Characteristics
Changed Gain Error condition from “Before Calibration” to “After Calibration”
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS1217
26
www.ti.com
SBAS260C
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS1217IPFBR
ACTIVE
TQFP
PFB
48
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1217
ADS1217IPFBT
ACTIVE
TQFP
PFB
48
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1217
ADS1217IPFBTG4
ACTIVE
TQFP
PFB
48
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1217
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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