ADS1244IDGST

ADS1244 ADS1 244 SBAS273 – DECEMBER 2002 Low-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES q 20-BIT EFFECTIVE RESOLUTION q CURRENT CONSUMPTION: 90µA q ANALOG SUPPLY: 2.5V to 5.25V q DIGITAL SUPPLY: 1.8V to 3.6V q ±5V DIFFERENTIAL INPUT RANGE q 0.0002% INL (TYP), 0.0008% INL (MAX) q SIMPLE 2-WIRE SERIAL INTERFACE q SIMULTANEOUS 50Hz AND 60Hz REJECTION q SINGLE CONVERSIONS WITH SLEEP MODE q SINGLE-CYCLE SETTLING q SELF-CALIBRATION q WELL-SUITED FOR MULTICHANNEL SYSTEMS q EASILY CONNECTS TO THE MSP430 DESCRIPTION The ADS1244 is a 24-bit, delta-sigma Analog-to-Digital (A/D) converter. It offers excellent performance and very low power in an MSOP-10 package and is well suited for demanding high-resolution measurements, especially in portable and other space- and power-constrained systems. A 3rd-order delta-sigma modulator and digital filter form the basis of the A/D converter. The analog modulator has a ±5V differential input range. The digital filter rejects both 50Hz and 60Hz signals, completely settles in one cycle, and outputs data at 15 samples per second. A simple, 2-wire serial interface provides all the necessary control. Data retrieval, self-calibration, and Sleep Mode are handled with a few simple waveforms. When only single conversions are needed, the ADS1244 can be shut down (Sleep Mode) while idle between measurements to dramatically reduce the overall power dissipation. Multiple ADS1244s can be connected together to create a synchronously sampling multichannel measurement system. The ADS1244 is designed to easily connect to microcontrollers, such as the MSP430. The ADS1244 supports 2.5V to 5.25V analog supplies and 1.8V to 3.6V digital supplies. Power is typically less than 270µW in normal operation and less than 1µW during Sleep Mode. APPLICATIONS q HAND-HELD INSTRUMENTATION q PORTABLE MEDICAL EQUIPMENT q INDUSTRIAL PROCESS CONTROL q WEIGH SCALES VREFP VREFN AVDD DVDD CLK DRDY/DOUT Digital Filter Serial Interface SCLK AINP AINN 3rd-Order Modulator GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) AVDD to GND ....................................................................... –0.3V to +6V DVDD to GND ................................................................... –0.3V to +3.6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................ 10mA, Continuous Analog Input Voltage to GND .............................. –0.5V to AVDD + 0.5V Digital Input Voltage to GND ............................... –0.3V to DVDD + 0.3V Digital Output Voltage to GND ............................. –0.3V to DVDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –60°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEMO BOARD ORDERING INFORMATION PRODUCT ADS1244-EVM DESCRIPTION ADS1244 Evaluation Module PACKAGE/ORDERING INFORMATION PACKAGE DESIGNATOR(1) DGS SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING BHG ORDERING NUMBER ADS1244IDGST ADS1244IDGSR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 PRODUCT ADS1244 PACKAGE-LEAD MSOP-10 " " " " " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View MSOP PIN DESCRIPTIONS PIN NUMBER 1 2 NAME GND VREFP VREFN AINN AINP AVDD DVDD DRDY/ DOUT DESCRIPTION Analog and Digital Ground Positive Reference Input Negative Reference Input Negative Analog Input Positive Analog Input Analog Power Supply, 2.5V to 5.25V Digital Power Supply, 1.8V to 3.6V Dual-Purpose Output: Data Ready: Indicates valid data by going LOW. Data Output: Outputs data, MSB first, on the first rising edge of SCLK. Serial Clock Input: Clocks out data on the rising edge. Used to initiate calibration and Sleep Mode, see text for more details. System Clock Input: Typically 2.4576MHz GND VREFP VREFN AINN AINP 1 2 3 4 5 10 9 8 7 6 CLK SCLK DRDY/DOUT DVDD AVDD 3 4 5 6 7 8 ADS1244 9 SCLK 10 CLK 2 ADS1244 www.ti.com SBAS273 ELECTRICAL CHARACTERISTICS All specifications –40°C to +85°C, AVDD = 5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = 2.5V, unless otherwise specified. ADS1244 PARAMETER ANALOG INPUT Full-Scale Input Voltage Range Absolute Input Range Differential Input Impedance SYSTEM PERFORMANCE Resolution Data Rate Integral Nonlinearity (INL) Offset Error Offset Error Drift(3) Gain Error Gain Error Drift(3) Common-Mode Rejection CONDITIONS MIN TYP ±2VREF GND – 0.1 5 24 15 ±0.0002 1 0.01 0.005 0.5 130 ±0.0008 10 0.02 AVDD + 0.1 MAX UNITS AINP – AINN AINP, AINN with Respect to GND fCLK = 2.4576MHz No Missing Codes fCLK = 2.4576MHz Differential Input Signal, End Point Fit V V MΩ Bits sps(1) % FSR(2) ppm of FSR ppm of FSR/°C % ppm/°C dB dB dB dB dB ppm of FSR, rms dB dB V V V MΩ Normal-Mode Rejection Input Referred Noise Analog Power-Supply Rejection Digital Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Voltage (VREF) Negative Reference Input (VREFN) Positive Reference Input (VREFP) Voltage Reference Impedance DIGITAL INPUT/OUTPUT Logic Levels VIH (CLK, SCLK) VIL (CLK, SCLK) VOH ( DRDY/DOUT ) VOL ( DRDY/DOUT ) Input Leakage (CLK, SCLK) CLK Frequency (fCLK) CLK Duty Cycle POWER SUPPLY AVDD DVDD AVDD Current at DC fCM(4) = 50 ± 1Hz, fCLK = 2.4576MHz fCM = 60 ± 1Hz, fCLK = 2.4576MHz fSIG(5) = 50 ± 1Hz, fCLK = 2.4576MHz fSIG = 60 ± 1Hz, fCLK = 2.4576MHz at DC, ∆AVDD = 5% at DC, ∆DVDD = 5% VREF ≡ VREFP – VREFN 90 100 100 60 70 1 105 100 0.5 GND – 0.1 VREFN + 0.5 2.5 AVDD(6) VREFP – 0.5 AVDD + 0.1 fCLK = 2.4576MHz 1 IOH = 1mA IOL = 1mA 0 < (CLK, SCLK) < DVDD 2.1 GND 2.6 5.25 0.9 0.4 ±10 6 70 5.25 3.6 1 150 5 10 30 2.5 1.8 Sleep Mode AVDD = 3V AVDD = 5V Sleep Mode, CLK Stopped Sleep Mode, 2.4576MHz CLK Running DVDD = 3V AVDD = DVDD = 3V 0.1 85 90 0.1 1.3 4.5 270 V V V V µA MHz % V V µA µA µA µA µA µA µW DVDD Current Total Power Dissipation NOTES: (1) sps = Samples Per Second. (2) FSR = Full-Scale Range = 4VREF. (3) Recalibration can reduce these errors to the level of the noise. (4) fCM is the frequency of the common-mode input. (5) fSIG is the frequency of the input signal. (6) It will not be possible to reach the digital output full-scale code when VREF > AVDD/2. ADS1244 SBAS273 www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. ANALOG CURRENT vs TEMPERATURE 110 105 100 12 10 AVDD = 5V, fCLK = 4.9152MHz 8 6 4 2 DIGITAL CURRENT vs TEMPERATURE DVDD = 3V, fCLK = 4.9152MHz Current (µA) 95 90 85 80 AVDD = 3V, fCLK = 2.4576MHz 75 70 –45 –25 –5 15 35 55 75 95 Temperature (°C) Current (µA) DVDD = 1.8V, fCLK = 2.4576MHz 0 –45 –25 –5 15 35 55 75 95 Temperature (°C) ANALOG CURRENT vs ANALOG SUPPLY 94 92 90 Current (µA) DIGITAL CURRENT vs DIGITAL SUPPLY 20 18 16 Current (µA) fCLK = 4.9152MHz 14 12 10 8 6 4 2 0 fCLK = 2.4576MHz 1.5 2 2.5 3 3.5 4 fCLK = 4.9152MHz 88 86 84 82 80 2.5 3 3.5 4 4.5 5 5.5 Analog Supply (V) fCLK = 2.4576MHz Digital Supply (V) INTEGRAL NONLINEARITY vs VIN 3 2 AVDD = 5V, VREF = 2.5V T = 25°C INTEGRAL NONLINEARITY vs VIN 3 AVDD = 3V, VREF = 1.25V 2 INL (ppm of FSR) INL (ppm of FSR) 1 0 –1 –2 –3 –5 –3 –1 VIN (V) 1 3 5 T = –40°C 1 0 T = 25°C –1 –2 T = –40°C T = 85°C T = 85°C –1.5 –0.5 VIN (V) 0.5 1.5 2.5 –3 –2.5 4 ADS1244 www.ti.com SBAS273 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. INTEGRAL NONLINEARITY vs ANALOG SUPPLY 20 18 16 VREF = AVDD T = –40°C INTEGRAL NONLINEARITY vs ANALOG SUPPLY 20 18 16 INL (ppm of FSR) VREF = AVDD/2 T = 85°C T = 25°C T = –40°C INL (ppm of FSR) 14 12 10 8 6 4 2 0 1.5 2 2.5 T = 85°C 3 3.5 4 4.5 5 5.5 T = 25°C 14 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Analog Supply (V) Analog Supply (V) OFFSET vs TEMPERATURE 1 Normalized Offset (ppm of FSR) 1.00008 1.00006 GAIN vs TEMPERATURE 0.5 Normalized Gain 1.00004 1.00002 1 0.99998 0.99996 0.99994 0.99992 0 –0.5 –1 –45 –25 –5 15 35 55 75 95 Temperature (°C) 0.9999 –45 –25 –5 15 35 55 75 95 Temperature (°C) NOISE vs INPUT SIGNAL 1.6 1.5 NOISE vs TEMPERATURE 1.6 1.4 Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 –5 –3 –1 VIN (V) 1 3 5 1.2 1.0 0.8 0.6 0.4 0.2 0 –45 –25 –5 15 35 55 75 95 Temperature (°C) ADS1244 SBAS273 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. HISTOGRAM OF OUTPUT DATA 1200 1000 Number of Occurences Input-Referred Noise (µV, rms) 14 13 12 11 10 9 8 7 6 INPUT-REFERRED NOISE vs VREF 800 600 400 200 0 –4 –3 –2 –1 0 1 2 3 4 ppm of FSR 0 1 2 VREF (V) 3 4 5 ANALOG PSRR vs FREQUENCY 120 100 Magnitude (dB) DIGITAL PSRR vs FREQUENCY 120 100 Magnitude (dB) 80 60 40 20 0 1 10 100 1k 10k 100k Frequency (Hz) 80 60 40 20 0 1 10 100 1k 10k 100k Frequency (Hz) CMRR vs FREQUENCY 160 140 120 Magnitude (dB) 100 80 60 40 20 0 1 10 100 1k 10k 100k Frequency (Hz) 6 ADS1244 www.ti.com SBAS273 OVERVIEW ESD Protection The ADS1244 is an A/D converter comprised of a 3rd-order modulator followed by a digital filter. The modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). Figure 1 shows a conceptual diagram. The differential reference is scaled internally so that the full-scale input range is ±2VREF. The digital filter receives the modulator’s signal and provides a low-noise digital output. The filter also sets the frequency response of the converter and provides 50Hz and 60Hz rejection while settling in a single conversion cycle. A 2-wire serial interface indicates conversion completion and provides the user with the output data. AVDD/2 AVDD CA1 = 4pF S1 AINP S1 AINN S2 CA2 = 4pF AVDD AVDD/2 CB = 8pF S2 FIGURE 2. Simplified Input Structure. VREFP VREFN Σ VREF 2 CLK tSAMPLE = 128/fCLK ON S1 OFF ON 2VREF VIN Digital Filter and Serial Interface S2 OFF AINP AINN Σ Modulator DRDY/DOUT SCLK FIGURE 3. S1 and S2 Switch Timing for Figure 1. The constant charging of the input capacitors presents a load on the inputs that can be represented by effective impedances. Figure 4 shows the input circuitry with the capacitors and switches of Figure 2 replaced by their effective impedances. These impedances scale inversely with fCLK frequency. For example, if fCLK’s frequency is reduced by a factor of 2, the impedances will double. FIGURE 1. Conceptual Diagram of the ADS1244. ANALOG INPUTS (AINP, AINN) The input signal to be measured is applied to the input pins AINP and AINN. The ADS1244 accepts differential input signals, but can also measure unipolar signals. When measuring unipolar (or “single-ended” signals) with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input (AINP). Note that when the ADS1244 is used this way, only half of the converter’s full-scale range is used since only positive digital output codes will be produced. The ADS1244 measures the input signal using internal capacitors that are continuously charged and discharged. Figure 2 shows a simplified schematic of the ADS1244’s input circuitry with Figure 3 showing the ON/OFF timings of the switches. S1 switches close during the input sampling phase. With S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP – AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately AVDD/2 and CB discharges to 0V. This 2-phase sample/discharge cycle repeats with a frequency of fCLK/128 (19.2kHz for fCLK = 2.4576MHz). AVDD/2 ZeffA = tSAMPLE/CA1 = 13MΩ(1) AINP ZeffB = tSAMPLE/CB = 6.5MΩ(1) AINN ZeffA = tSAMPLE/CA2 = 13MΩ(1) AVDD/2 NOTE: (1) fCLK = 2.4576MHz. FIGURE 4. Effective Analog Input Impedances. ESD diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV: GND – 100mV < (AINP, AINN) < AVDD + 100mV. ADS1244 SBAS273 www.ti.com 7 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs. A simplified diagram of the circuitry on the reference inputs is shown in Figure 5. The switches and capacitors can be modeled with an effective  tSAMPLE   / 25pF = 1MΩ for fCLK = 2.4576MHz. impedance =    2 VREFP VREFN Minimize the overshoot and undershoot on CLK for the best analog performance. A small resistor in series with CLK (10Ω to 100Ω) can often help. CLK can be generated from a number of sources including stand-alone crystal oscillators and microcontrollers. The MSP430, an ultra low power microcontroller, is especially well suited for this task. Using the MSP430’s FLL clock generator available on the 4xx family, it’s easy to produce a 2.4576MHz clock from a 32.768kHz crystal. DATA READY/DATA OUTPUT ( DRDY/DOUT) This digital output pin serves two purposes. It indicates when new data is ready by going LOW. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, MSB first. Data is shifted out on each subsequent SCLK rising edge. After all 24 bits have been retrieved, the pin can be forced HIGH with an additional SCLK. It will then stay HIGH until new data is ready. This is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. AVDD S1 25pF S1 AVDD ESD Protection SERIAL CLOCK INPUT (SCLK) S2 FIGURE 5. Simplified Reference Input Circuitry. ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV: GND – 100mV < (VREFP, VREFN) < AVDD + 100mV. VREF is typically AVDD/2, but it can be raised as high as AVDD. When VREF exceeds AVDD/2, it will not be possible to reach the full-scale digital output value corresponding to ±2VREF since this would require the analog inputs to exceed the power supplies. For example, if VREF = AVDD = 5V, the positive full-scale signal is 10V. The maximum positive input signal that can be supplied before the ESD diodes begin to turn on is when AINP = 5.1V and AINN = –0.1V → VIN = 5.2V. Therefore, it will not be possible to reach the positive (or negative) full-scale readings in this configuration. The digital output codes will be limited to approximately one half of the entire range. For best performance, bypass the voltage reference inputs with a 0.1µF capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD or AVDD voltage. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns. FREQUENCY RESPONSE The ADS1244’s frequency response for fCLK = 2.4576MHz is shown in Figure 6. The frequency response repeats at multiples of 19.2kHz. The overall response is that of a low-pass filter with a –3dB cutoff frequency of 13.7Hz. As can be seen, the ADS1244 does a good job attenuating out to 19kHz. For the best resolution, limit the input bandwidth to below this value to keep higher frequency noise from affecting performance. Often a simple RC filter on the ADS1244’s analog inputs is all that is needed. FREQUENCY RESPONSE fCLK = 2.4576MHz 0 –20 –40 Gain (dB) CLOCK INPUT (CLK) This digital input supplies the system clock to the ADS1244. The recommended CLK frequency is 2.4576MHz. This places the notches of the digital filter at 50Hz and 60Hz and sets the data rate at 15SPS. The CLK frequency can be increased to speed up the data rate, but the frequency notches will move in frequency proportionally. CLK must be left running during normal operation. It may be turned off during Sleep Mode to save power, but this is not required. The CLK input may be driven with 5V logic, regardless of the DVDD or AVDD voltage. –60 –80 –100 –120 –140 0 9.6 Frequency (kHz) 19.2 FIGURE 6. Frequency Response. 8 ADS1244 www.ti.com SBAS273 To help see the response at lower frequencies, Figure 7 illustrates the response out to 180Hz. Notice that both 50Hz and 60Hz signals are rejected. This feature is very useful for eliminating power line cycle interference during measurements. Figure 8 shows the ADS1244’s response around these frequencies. FREQUENCY RESPONSE TO 180Hz fCLK = 2.4576MHz 0 –20 –40 –60 Gain (dB) The ADS1244’s data rate and frequency response scale directly with CLK frequency. For example, if fCLK increases from 2.4576MHz to 4.9152MHz, the data rate increases from 15sps to 30sps while the notches in the response at 50Hz and 60Hz move out to 100Hz and 120Hz. SETTLING TIME The ADS1244 has single-cycle settling. That is, the output data is fully settled after a single conversion—there is no need to wait for additional conversions before retrieving the data when there is a change on the analog inputs. In order to realize single-cycle settling, synchronize changes on the analog inputs to the conversion beginning, which is indicated by the falling edge of DRDY/DOUT. For example, when using a multiplexer in front of the ADS1244, change the multiplexer’s inputs when DRDY/DOUT goes LOW. Increasing the time between the conversion beginning and the change on the analog inputs (tDELAY) will result in a settling error in the conversion data, as shown in Figure 9. The settling error versus delay time is shown in Figure 10. If the input change is delayed to the point where the settling error is too high, simply ignore the first data result and wait for the second conversion which will be fully-settled. –80 –100 –120 –140 –160 –180 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 Frequency (Hz) FIGURE 7. Frequency Response to 180Hz. FREQUENCY RESPONSE NEAR 50Hz AND 60Hz fCLK = 2.4576MHz –40 –50 1.000000 10.000000 SETTLING ERROR vs DELAY TIME fCLK = 2.4576MHz –60 Gain (dB) –70 –80 –90 –100 –110 –120 45 50 55 Frequency (Hz) 60 65 Settling Error (%) 0.100000 0.010000 0.001000 0.000100 0.000010 0.000001 0 2 4 6 8 10 12 Delay Time, tDELAY (ms) 14 16 FIGURE 8. Frequency Response Near 50Hz and 60Hz. FIGURE 10. Settling Error vs Delay Time. Begin New Conversion, Previous Conversion Data Complete Previous Conversion New Conversion Complete DRDY/DOUT tDELAY VIN FIGURE 9. Analog Input Change Timing. ADS1244 SBAS273 www.ti.com 9 POWER-UP Self-calibration is performed at power-up to minimize offset and gain errors. In order for the self-calibration at power-up to work properly, make sure that both AVDD and DVDD increase monotonically and are settled by t1, as shown in Figure 11. SCLK must be held LOW during this time. Once calibration is complete, DRDY/DOUT will go LOW indicating data is ready for retrieval. The time required before the first data is ready (t6) depends on how fast AVDD and DVDD ramp to their final value (t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz). If the system environment is not stable during power-up (the temperature is varying or the supply voltages are moving around), it is recommended that a self-calibration be issued after everything is stable. duces an output code of 7FFFFFH and the negative full-scale input produces an output code of 800000H. The output clips at these codes for signals exceeding full-scale. Table I summarizes the ideal output codes for different input signals. INPUT SIGNAL VIN (AINP – AINN) ≥ +2VREF IDEAL OUTPUT CODE(1) 7FFFFFH 000001H 000000H FFFFFFH +2VREF 2 23 − 1 0 −2VREF 2 23 − 1  2 23  ≤ − 2VREF  23   2 − 1 800000H NOTE: (1) Excludes effects of noise, INL, offset, and gain errors. DATA FORMAT The ADS1244 outputs 24 bits of data in Binary Two’s Complement format. The Least Significant Bit (LSB) has a weight of (2VREF)/(223 – 1). A positive full-scale input pro- TABLE I. Ideal Output Code versus Input Signal. AVDD and DVDD Data ready after power-up calibration. DRDY/DOUT SCLK t1 t2 SYMBOL t1(1) t2(1) DESCRIPTION AVDD and DVDD settling time. Wait time for calibration and first data conversion. MIN 316 MAX 100 UNITS ms ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 11. Power-Up Timing. 10 ADS1244 www.ti.com SBAS273 DATA RETRIEVAL The ADS1244 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes LOW, as shown in Figure 12. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out Most Significant Bit (MSB) first. It is not required to shift out all the 24 bits of data, but the data must be retrieved before the new data is updated (see t3) or else it will be overwritten. Avoid data retrieval during the update period. DRDY/DOUT will remain at the state of the last bit shifted out until it is taken HIGH (see t7), indicating that new data is being updated. To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT HIGH, see Figure 13. This technique is useful when a host controlling the ADS1244 is polling DRDY/DOUT to determine when data is ready. Data Data is ready. MSB DRDY/DOUT 23 t5 t3 SCLK 1 t4 t8 t4 24 22 21 LSB 0 t6 t7 New data is ready. SYMBOL t3 t4 t5(1) t6 t7(2) t8(2) DESCRIPTION DRDY/DOUT LOW to first SCLK rising edge. SCLK positive or negative pulse width. SCLK rising edge to new data bit valid: propagation delay. SCLK rising edge to old data bit valid: hold time. Data updating, no read back allowed. Conversion time (1/data rate). MIN 0 100 50 0 152 66.667 MAX UNITS ns ns ns ns 152 66.667 µs ms NOTES: (1) Load on DRDY/DOUT = 20pF || 100kΩ. (2) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8 → 33.333ms. FIGURE 12. Data Retrieval Timing. Data Data is ready. New data is ready. DRDY/DOUT 23 22 21 0 SCLK 1 24 25 25th SCLK to force DRDY/DOUT HIGH. FIGURE 13. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards. ADS1244 SBAS273 www.ti.com 11 SELF-CALIBRATION The user can initiate self-calibration at any time, though in many applications the ADS1244’s drift performance is good enough that the self-calibration performing automatically at power-up is all that is needed. To initiate a self-calibration, apply at least two additional SCLKs after retrieving 24 bits of data. Figure 14 shows the timing pattern. The 25th SCLK will send DRDY/DOUT HIGH. The falling edge of the 26th SCLK will begin the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK, but try to minimize activity on SCLK during calibration for best results. When the calibration is complete, DRDY/DOUT will go LOW indicating that new data is ready. There is no need to alter the analog input signal applied to the ADS1244 during calibration, the inputs pins are disconnected within the A/D converter and the appropriate signals applied internally automatically. The first conversion after a calibration is fully settled and valid for use. The time required for a calibration depends on two independent signals: the falling edge of SCLK and an internal clock derived from CLK. Variations in the internal calibration values will change the time required for calibration (t9) within the range given by the MIN/MAX specs. t12 and t13 described in the next section are affected likewise. Data ready after cal. DRDY/DOUT 23 22 21 0 Cal begins. 23 SCLK 1 24 25 26 t9 SYMBOL t9(1) DESCRIPTION First data ready after calibration. MIN 209 MAX 210 UNITS ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 14. Self-Calibration Timing. 12 ADS1244 www.ti.com SBAS273 SLEEP MODE Sleep Mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of the active circuitry. To enter Sleep Mode, simply hold SCLK HIGH after DRDY/DOUT goes LOW, as shown in Figure 15. Sleep Mode can be initiated at any time during read back; it is not necessary to retrieve all 24 bits of data beforehand. Once t11 has passed with SCLK held HIGH, Sleep Mode will activate. DRDY/DOUT stays HIGH once Sleep Mode begins. SCLK must remain HIGH to stay in Sleep Mode. To exit Sleep Mode (“wakeup”), set SCLK LOW. The first data after exiting Sleep Mode is valid. It is not necessary to stop CLK during Sleep Mode, but doing so will further reduce the digital supply current. To force a self-calibration with Sleep Mode, shift 25 bits out before taking SCLK HIGH to enter Sleep Mode. Self-calibration will then begin after wakeup. Figure 16 shows the appropriate timing. Note the extra time needed after wakeup for calibration before data is ready. The first data after Sleep Mode with self-calibration is fully-settled and can be used. SINGLE CONVERSIONS When only single conversions are needed, Sleep Mode can be used to start and stop the ADS1244. To make a single conversion, first enter the Sleep Mode holding SCLK HIGH. Now, when ready to start the conversion, take SCLK LOW. The ADS1244 will wake up and begin the conversion. Wait for DRDY/DOUT to go LOW, and then retrieve the data. Afterwards, take SCLK HIGH to stop the ADS1244 from converting and re-enter Sleep Mode. Continue to hold SCLK HIGH until ready to start the next conversion. Operating in this fashion greatly reduces power consumption since the ADS1244 is shut down while idle between conversions. Selfcalibrations can be performed prior to the start of the single conversions by using the waveform shown in Figure 16. Sleep Mode With Self-Calibration Self-calibration can be set to run immediately after exiting Sleep Mode. This is useful when the ADS1244 is put in Sleep Mode for long periods of time and self-calibration is desired afterwards to compensate for temperature or supply voltage changes. Data ready after wakeup. Sleep Mode DRDY/DOUT 23 22 21 0 Wakeup 23 SCLK 1 t10 t11 24 t12 SYMBOL t10 (1) DESCRIPTION SCLK HIGH after DRDY/DOUT goes LOW to activate Sleep Mode. Sleep Mode activation Time. Data ready after wakeup. MIN 0 66.5 71 MAX 63.7 66.5 72 UNITS ms ms ms t11(1) t12(1) NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 15. Sleep Mode Timing; Can be Used for Single Conversions. Data ready after wakeup and cal. Sleep Mode DRDY/DOUT 23 22 21 0 Wakeup and begin cal. SCLK 1 t11 24 25 t13 23 SYMBOL t13(1) DESCRIPTION Data ready after wakeup and calibration. MIN 210 MAX 211 UNITS ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 16. Sleep Mode with Self-Calibration on Wakeup Timing; Can be Used for Single Conversions. ADS1244 SBAS273 www.ti.com 13 SINGLE-SUPPLY OPERATION It is possible to operate the ADS1244 with a single supply. For a 3V supply, simply connect AVDD and DVDD together. Figure 17 shows an example of the ADS1244 running on a single 5V supply. An external resistor, R1, is used to drop 5V supply down to a desired voltage level of DVDD. For example, if the desired DVDD supply voltage is 3V and AVDD is 5V, the value of R1 should be: R1 = (5V – 3V)/4.5µA ≈ 440kΩ where 4.5µA is a typical digital current consumption when DVDD = 3V (refer to the typical characteristic “Digital Current vs Digital Supply”). A buffer on DRDY/DOUT can provide level-shifting if required. DVDD can be set to a desired voltage by choosing a proper value of R1, but keep in mind that DVDD must be set between 1.8V and 3.6V. Note that the maximum logic HIGH output of DRDY/DOUT is equal to DVDD, but both CLK and SCLK inputs can be driven with 5V logic regardless of the DVDD or AVDD voltage. Use 0.1µF capacitors to bypass both AVDD and DVDD. MULTICHANNEL SYSTEMS Multiple ADS1244s can be operated in parallel to measure multiple input signals. Figure 18 shows an example of a 2-channel system. For simplicity, the supplies and reference circuitry were not included. The same CLK signal should be applied to all devices. To be able to synchronize the ADS1244s, connect the same SCLK signal to all devices as well. When ready to synchronize, place all the devices in Sleep Mode. Afterwards, “wakeup” and all the ADS1244s will be synchronized. That is, they will sample the input signals simultaneously. The DRDY/DOUT outputs will go LOW at approximately the same time after synchronization. The falling edges indicating that new data is ready will vary with respect to each other no more than timing specification t14. This variation is due to posible differences in the ADS1244’s internal calibration settings. To account for this when using multiple devices, either wait for t14 to pass after seeing one device’s DRDY/DOUT go LOW, or wait until all DRDY/DOUTs have gone LOW before retrieving data. ADS1244 1 2 3 GND VREFP VREFN AINN AINP CLK 10 SCLK DRDY/DOUT DVDD AVDD 9 8 7 6 OUT1 to +5V logic +5V SN74LVCC3245A 0.1µF + 0.1µF + IN1 4 5 from +5V logic from +5V logic R1 ADS1244 1 GND VREFP VREFN AINN AINP CLK 10 SCLK DRDY/DOUT DVDD AVDD 9 8 7 6 OUT2 10 CLK 9 SCLK 8 DRDY/DOUT 7 DVDD 6 AVDD 2 3 4 IN2 5 ADS1244 GND 1 VREFP 2 VREFN 3 AINN 4 AINP 5 CLK and SCLK Sources OUT1 t14 OUT2 SYMBOL DESCRIPTION Difference between DRDY/DOUT s going LOW in multichannel systems. MIN MAX ±500 UNITS µs FIGURE 17. Example of the ADS1244 Running on a Single 5V Supply. t14 FIGURE 18. Example of Using Multiple ADS1244s in Parallel. 14 ADS1244 www.ti.com SBAS273 WEIGH SCALE SYSTEM Figure 19 shows an example of a weigh scale system. OPA1, OPA2, RG, and RF form a differential gain stage to amplify the load cell output. The gain is equal to (1 + 2 RF/RG). Depending on the load cell, the typical gain setting is from 100 to 250. RI and CI form a single-pole low-pass filter to band-limit the differential gain stage noise and reduce mechanical vibration noise from the load cell. The cutoff frequency of the low-pass filter should be as low as possible to minimize the overall system noise. The reference voltage is typically generated by dividing down the supply voltage (RVR1, RVR2). Use a bypass capacitor located as close to VREFP as possible. 5V EMI Filter 1µF RVR1 AVDD 0.1µF EMI Filter OPA1(1) 1.8V ~ 3.6V 0.1µF 0.1µF 1µF 0.1µF DVCC AVCC DVDD RVR2 VREFP AINP RI ADS1244 MSP430Fx41x Load Cell RF RG RF CI SCLK DRDY/ DOUT P1.2/TA1 P1.0/TA0 XIN 32.768kHz XOUT/TCLK EMI Filter OPA2(1) AINN RI CLK P1.1/TA0/MCLK VREFN EMI Filter GND AVSS DVSS NOTE: (1) OPA2335 or OPA2277 recommended. FIGURE 19. Weigh Scale System. ADS1244 SBAS273 www.ti.com 15 SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 MSB SCLK 1 24 22 21 0 LSB a. Data Retrieval. DRDY/DOUT 23 22 21 0 SCLK 1 24 25 b. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards. Data ready after cal. DRDY/DOUT 23 22 21 0 Begin cal. SCLK 1 24 25 26 c. Self-Calibration. Data ready. Sleep Mode DRDY/DOUT 23 22 21 0 Wakeup and start conversion. SCLK 1 24 d. Sleep Mode/Single Conversions. Data ready after wakeup and cal. Sleep Mode DRDY/DOUT 23 22 21 0 Wakeup and begin cal. SCLK 1 24 25 e. Sleep Mode/Single Conversions with Self-Calibration on Wakeup. FIGURE 20. Summary of Serial Interface Waveforms. 16 ADS1244 www.ti.com SBAS273 PACKAGE DRAWING DGS (S-PDSO-G10) 0,27 0,17 10 6 PLASTIC SMALL-OUTLINE PACKAGE 0,50 0,08 M 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 3,05 2,95 5 0°– 6° 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073272/B 08/01 NOTES: A. B. C. A. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 ADS1244 SBAS273 www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE ADS1244IDGSR ADS1244IDGST STATUS(1) ACTIVE ACTIVE PACKAGE TYPE VSSOP VSSOP PACKAGE DRAWING DGS DGS PINS 10 10 PACKAGE QTY 2500 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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