ADS131B02QPWRQ1

ADS131B02-Q1 SBASAA3 – SEPTEMBER 2021 ADS131B02-Q1 Automotive, 2-Channel, 32-kSPS, Simultaneous-Sampling, 24-Bit, Delta-Sigma ADC 1 Features 3 Description • The ADS131B02-Q1 is a two-channel, simultaneoussampling, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) that offers wide dynamic range, low power, and buffered analog inputs, making the device an excellent fit for automotive battery management systems (BMS). The ADC inputs can be directly interfaced to shunt resistors for bidirectional batterycurrent measurements, to resistor-divider networks for high-voltage measurements, or to temperature sensors (such as thermistors or analog output temperature sensors). • • • • • • • • • • • • • • AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA Functional Safety-Capable – Documentation available to aid functional safety system design 2 simultaneous-sampling, differential input ADCs Programmable data rate: Up to 32 kSPS Programmable gain: Up to 128 Noise performance: – 0.82 μVRMS at 1 kSPS, gain = 8 Global-chop mode to remove offset drift over temperature and time High-impedance analog inputs for direct sensor connection Integrated negative charge pump allows input signal measurements below ground Crosstalk between channels: –120 dB Low-drift internal reference: 1.2 V Precision internal oscillator CRC on communications and register map Analog and digital supplies: 2.7 V to 3.6 V Low power consumption: 3 mW at 3.3-V AVDD and DVDD 2 Applications • • • EV charging stations – DC e-metering Automotive battery management systems (BMS): – Current-shunt measurements – Voltage measurements using external resistor dividers – Temperature measurements using thermistors or analog output temperature sensors Energy storage systems (ESS) The individual ADC channels can be independently configured depending on the sensor input. A lownoise, programmable gain amplifier (PGA) provides gains ranging from 1 to 128 to amplify low-level signals. The device features a global-chop mode to remove offset drift over temperature and time. Additionally, this device integrates offset and gain calibration registers to help remove signal-chain errors. A low-drift, 1.2-V reference and precision oscillator are integrated into the device reducing printed circuit board (PCB) area. Optional cyclic redundancy checks (CRCs) on the data input, data output, and register map maintain communication integrity. The complete analog front-end (AFE) is offered in a 20-pin TSSOP package and is specified over the automotive temperature range of –40°C to +125°C. Device Information(1) PART NUMBER ADS131B02-Q1 (1) PACKAGE TSSOP (20) BODY SIZE (NOM) 6.50 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. AVDD DVDD 1.2-V Reference Oscillator Clock Selection CLKIN SYNC/RESET AIN0P + '6 ADC AIN0N Digital Filter ± Gain & Offset Calibration CS SCLK Control & Serial Interface DIN DOUT AIN1P + '6 ADC AIN1N ± AGND Digital Filter Gain & Offset Calibration DRDY DGND Simplified Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................5 6.4 Thermal Information ...................................................5 6.5 Electrical Characteristics ............................................6 6.6 Timing Requirements ................................................. 8 6.7 Switching Characteristics ...........................................8 6.8 Timing Diagrams......................................................... 9 6.9 Typical Characteristics.............................................. 10 7 Parameter Measurement Information.......................... 12 7.1 Noise Measurements................................................ 12 8 Detailed Description......................................................13 8.1 Overview................................................................... 13 8.2 Functional Block Diagram......................................... 13 8.3 Feature Description...................................................14 8.4 Device Functional Modes..........................................23 8.5 Programming............................................................ 27 8.6 Register Map.............................................................37 9 Application and Implementation.................................. 53 9.1 Application Information............................................. 53 9.2 Typical Application.................................................... 56 10 Power Supply Recommendations..............................59 10.1 CAP Pin Capacitor Requirement............................ 59 10.2 Power-Supply Sequencing......................................59 10.3 Power-Supply Decoupling.......................................59 11 Layout........................................................................... 59 11.1 Layout Guidelines................................................... 59 11.2 Layout Example...................................................... 60 12 Device and Documentation Support..........................61 12.1 Receiving Notification of Documentation Updates..61 12.2 Support Resources................................................. 61 12.3 Trademarks............................................................. 61 12.4 Electrostatic Discharge Caution..............................61 12.5 Glossary..................................................................61 13 Mechanical, Packaging, and Orderable Information.................................................................... 61 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE September 2021 2 REVISION * NOTES Initial Release Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 5 Pin Configuration and Functions AVDD 1 20 DVDD AGND 2 19 DGND AIN0P 3 18 CAP AIN0N 4 17 CLKIN AIN1N 5 16 DIN AIN1P 6 15 DOUT NC 7 14 SCLK NC 8 13 DRDY NC 9 12 CS NC 10 11 SYNC/RESET Not to scale Figure 5-1. PW Package, 20-Pin TSSOP, Top View Table 5-1. Pin Functions PIN NAME NO. DESCRIPTION(1) TYPE AGND 2 Supply AIN0N 4 Analog input Negative analog input 0 AIN0P 3 Analog input Positive analog input 0 AIN1N 5 Analog input Negative analog input 1 AIN1P 6 Analog input Positive analog input 1 AVDD 1 Supply CAP 18 Analog output CLKIN 17 Digital input External clock input CS 12 Digital input Chip select; active low DGND 19 Supply DIN 16 Digital input DOUT 15 Digital output Serial data output DRDY 13 Digital output Data ready; active low DVDD Analog ground Analog supply. Connect a 1-µF capacitor to AGND. Digital low-dropout (LDO) regulator output. Connect a 220-nF capacitor to DGND. Digital ground Serial data input 20 Supply 7, 8, 9, 10 - SCLK 14 Digital input Serial data clock SYNC/RESET 11 Digital input Conversion synchronization or system reset; active low NC (1) Digital I/O supply. Connect a 1-µF capacitor to DGND. Leave unconnected or connect to AGND See the Unused Inputs and Outputs section for details on how to connect unused pins. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 3 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings See (1) Power-supply voltage MIN MAX AVDD to AGND –0.3 3.9 AGND to DGND –0.3 0.3 DVDD to DGND –0.3 3.9 CAP to DGND –0.3 2.2 UNIT V Analog input voltage AINxP, AINxN AGND – 1.6 AVDD + 0.3 V Digital input voltage CS, CLKIN, DIN, SCLK, SYNC/RESET DGND – 0.3 DVDD + 0.3 V Input current Continuous, all pins except power-supply pins Temperature (1) –10 10 Junction, TJ 150 Storage, Tstg –60 150 mA °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 6.2 ESD Ratings VALUE V(ESD) (1) 4 Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM ESD classification level 2 Charged-device model (CDM), per AEC Q100-011 CDM ESD classification level C4B UNIT ±2000 Corner pins ±750 All other non-corner pins ±500 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX AVDD to AGND 2.7 3.3 3.6 AGND to DGND –0.3 0 0.3 DVDD to DGND 2.7 3.3 3.6 UNIT POWER SUPPLY Analog power supply Digital power supply V V ANALOG INPUTS(1) VAINxP, VAINxN Absolute input voltage VIN Differential input voltage Gain = 1, 2 AGND – 0.1 AVDD – 1.2 Gain = 4, 8, 16, 32, 64, 128 AGND – 0.3 AVDD – 2.4 VIN = VAINxP - VAINxN –VREF / Gain VREF / Gain V V EXTERNAL CLOCK SOURCE(2) fCLKIN External clock frequency High-resolution mode 0.3 8.192 8.2 Low-power mode 0.3 4.096 4.15 0.3 2.048 2.08 40% 50% 60% Very-low-power mode Duty cycle MHz DIGITAL INPUTS Input voltage DGND DVDD V –40 125 °C TEMPERATURE TA (1) (2) Operating ambient temperature The subscript "x" signifies the channel. For example, the positive analog input of channel 0 is named AIN0P. See the Pin Configuration and Functions section for the pin names. An external clock is not required when the internal oscillator is used. 6.4 Thermal Information ADS131B02-Q1 THERMAL METRIC(1) PW (TSSOP) UNIT 20 PINS RθJA 91.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.4 °C/W RθJB Junction-to-board thermal resistance 43.0 °C/W ΨJT Junction-to-top characterization parameter 2.0 °C/W ΨJB Junction-to-board characterization parameter 42.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) Junction-to-ambient thermal resistance For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 5 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.5 Electrical Characteristics minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3.3 V, DVDD = 3.3 V, external clock, fCLKIN = 8.192 MHz, high-resolution mode, all channels, all gains, data rate = 4 kSPS, all channels enabled, and global-chop mode disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Zin Global-chop disabled 25 Differential input impedance Global-chop enabled 300 All power modes, all data rates Absolute input current Differential input current MΩ See Table 8-2 Global-chop disabled, VAINxP = VAINxN = 0 V ±1 Global-chop enabled, VAINxP = VAINxN = 0 V ±1 Global-chop disabled, VAINxP = VAINxN = 0 V ±50 Global-chop enabled, VAINxP = VAINxN = 0 V ±30 nA pA ADC CHARACTERISTICS Resolution 24 Gain settings 1, 2, 4, 8, 16, 32, 64, 128 High-resolution mode, fCLKIN = 8.192 MHz fDATA Data rate Bits 250 32k Low-power mode, fCLKIN = 4.096 MHz 125 16k Very-low-power mode, fCLKIN = 2.048 MHz 62.5 8k SPS ADC PERFORMANCE INL Integral nonlinearity (best fit) Differential-ended input Offset error (input referred) Global-chop disabled –800 ±200 800 Global-chop enabled –4 ±0.4 4 Global-chop disabled, gain = 1 to 4 Offset drift Offset error long-term drift Gain error Gain drift Gain error long-term drift CMRR 6 Common-mode rejection ratio ppm of FSR 10 100 500 Global-chop disabled, gain = 8 to 128 50 200 Global-chop enabled 10 30 1000 hours at TA = 85°C, global-chop disabled 0.8 1000 hours at TA = 85°C, global-chop enabled 0.25 Including error of internal voltage reference, TA = 25°C µV nV/°C μV –0.7% ±0.2% 0.7% Including drift of internal voltage reference, TA = –40°C to +85°C, gain = 1 to 4 8 30 Including drift of internal voltage reference, TA = –40°C to +85°C, gain = 8 to 128 7 25 ppm/°C Including drift of internal voltage reference, TA = –40°C to +125°C 13 1000 hours at TA = 85°C, gain = 1, including drift of internal voltage reference 250 At dc, global-chop disabled, gain = 1 96 At dc, global-chop enabled, gain = 1 128 fCM = 50 Hz or 60 Hz, global-chop disabled, gain = 1 89 fCM = 50 Hz or 60 Hz, global-chop enabled, gain = 1 106 Submit Document Feedback 40 ppm dB Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.5 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3.3 V, DVDD = 3.3 V, external clock, fCLKIN = 8.192 MHz, high-resolution mode, all channels, all gains, data rate = 4 kSPS, all channels enabled, and global-chop mode disabled (unless otherwise noted) PARAMETER PSRR Power-supply rejection ratio Input-referred noise TEST CONDITIONS MIN AVDD at dc, global-chop disabled, gain = 1 81 AVDD at dc, global-chop enabled, gain = 1 116 DVDD at dc, global-chop disabled, gain = 1 109 DVDD at dc, global-chop enabled, gain = 1 117 Gain = 1 5.42 Gain = 8 1.29 All gains, all data rates MAX UNIT dB µVRMS See Table 7-1 During fast start-up Crosstalk TYP 1.5 fIN = 50 Hz or 60 Hz mVRMS –120 dB 1.2 V INTERNAL VOLTAGE REFERENCE VREF Internal reference voltage INTERNAL OSCILLATOR fOSC Frequency 8.192 Accuracy Frequency long-term drift –5% 1000 hours at TA = 85°C ±0.5% MHz 2.5% 0.2% DIGITAL INPUTS/OUTPUTS VIL Logic input level, low VIH Logic input level, high VOL Logic output level, low IOL = –1 mA VOH Logic output level, high IOH = 1 mA IIN Input current DGND < VDigital Input < DVDD DGND 0.2 DVDD V 0.8 DVDD DVDD V 0.2 DVDD V 0.8 DVDD V –1 1 µA POWER SUPPLY IAVDD Analog supply current IDVDD Digital supply current(1) High-resolution mode, gain = 1, 2 2.9 3.6 High-resolution mode, gain = 4 to 128 3.3 4.2 Low-power mode, gain = 1, 2 1.5 2 Low-power mode, gain = 4 to 128 1.7 Very-low-power mode, gain = 1, 2 0.8 Very-low-power mode, gain = 4 to 128 0.9 Standby mode 0.4 Internal oscillator 140 High-resolution mode 0.3 Low-power mode Very-low-power mode Standby mode(2) PD Power dissipation µA 0.4 0.15 0.2 0.1 0.14 1.2 mA µA 10.6 13.2 High-resolution mode, gain = 4 to 128 11.9 15.2 5.4 7.3 3 4.4 Very-low-power mode, gain = 1, 2 (1) (2) 1.2 High-resolution mode, gain = 1, 2 Low-power mode, gain = 1, 2 mA mW Currents measured with SPI idle. External clock stopped. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 7 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.6 Timing Requirements over operating ambient temperature range, and DOUT load = 20 pF || 100 kΩ (unless otherwise noted) MIN MAX UNIT 2.7 V ≤ DVDD ≤ 3.6 V tw(CLL) Pulse duration, CLKIN low 49 ns tw(CLH) Pulse duration, CLKIN high 49 ns tc(SC) SCLK period 40 ns tw(SCL) Pulse duration, SCLK low 20 ns tw(SCH) Pulse duration, SCLK high 20 ns tw(CSH) Pulse duration, CS high 15 ns td(CSSC) Delay time, first SCLK rising edge after CS falling edge 16 ns td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns tsu(DI) Setup time, DIN valid before SCLK falling edge 5 ns th(DI) Hold time, DIN valid after SCLK falling edge 8 ns tsu(SY) Setup time, SYNC/RESET valid before CLKIN rising edge tw(SYL) Pulse duration, SYNC/RESET low for synchronization tw(RSL) Pulse duration, SYNC/RESET low to generate device reset 10 ns 1 2047 2048 tMCLK tMCLK 6.7 Switching Characteristics over operating ambient temperature range, and DOUT load = 20 pF || 100 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.7 V ≤ DVDD ≤ 3.6 V tp(CSDO) Propagation delay time, CS falling edge to DOUT driven 50 ns tp(SCDO) Progapation delay time, SCLK rising edge to valid new DOUT 20 ns tp(CSDOZ) Propagation delay time, CS rising edge to DOUT high impedance 75 ns tw(DRH) Pulse duration, DRDY high 4 tMCLK tw(DRL) Pulse duration, DRDY low 4 tMCLK SPI timeout tPOR Power-on-reset time 32768 Measured from supplies at 90% to first DRDY rising edge tREGACQ Register default acquisition time 8 Submit Document Feedback tMCLK 250 µs 5 µs Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.8 Timing Diagrams tw(CLH) tw(CLL) CLKIN tw(DRL) DRDY tw(DRH) § CS tw(SCL) td(CSSC) td(SCCS) tc(SC) tw(SCH) tw(CSH) § SCLK tsu(DI) th(DI) § § DIN tp(CSDO) tp(SCDO) MSB - 1 tw(CSDOZ) § § MSB DOUT LSB + 1 LSB SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low. Figure 6-1. SPI Timing Diagram § CLKIN tsu(SY) tw(SYL) tw(RSL) § SYNC/RESET Figure 6-2. SYNC/RESET Timing Requirements Supplies 90% tPOR DRDY Figure 6-3. Power-On-Reset Timing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 9 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.9 Typical Characteristics at TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted) 4 Channel 0 Channel 1 200 100 0 -100 -200 -300 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 Offset Error (input referred) (V) Offset Error (input referred) (V) 300 3 2 1 0 -1 -2 -3 Channel 0 Channel 1 -4 -40 140 -20 Gain = 8, global-chop mode disabled 100 120 140 4 Gain = 1 Gain = 4 Gain = 8 Gain = 16 200 100 0 -100 -200 -20 0 20 40 60 80 Temperature (°C) 100 120 Offset Error (input referred) (PV) Offset Error (input referred) (PV) 40 60 80 Temperature (°C) Figure 6-5. Offset Error vs Temperature 300 3 2 1 0 -1 -2 Gain = 1 Gain = 4 Gain = 8 Gain = 16 -3 -4 -40 140 -20 0 Global-chop mode disabled 20 40 60 80 Temperature (°C) 100 120 140 Global-chop mode enabled Figure 6-6. Offset Error vs Temperature Figure 6-7. Offset Error vs Temperature 0 0.5 Gain = 1 Gain = 4 Gain = 8 Gain = 16 0.4 -50 Gain Error (ppm) 0.3 0.2 Gain Error (%) 20 Gain = 8, global-chop mode enabled Figure 6-4. Offset Error vs Temperature -300 -40 0 0.1 0 -0.1 -0.2 -100 -150 -200 -0.3 -250 -0.4 -0.5 -40 0 -20 0 20 40 60 80 Temperature (°C) 100 120 140 100 200 300 400 500 600 Time (hours) 700 800 900 1000 Gain = 1, including error of internal voltage reference Including error of internal voltage reference Figure 6-8. Gain Error vs Temperature 10 Figure 6-9. Gain Error Long-Term Drift Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted) Oscillator Frequency Error (%) 3 2 1 0 -1 -2 -3 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Gain = 8, global-chop mode disabled Figure 6-10. Input-referred Noise vs Temperature Figure 6-11. Oscillator Frequency Error vs Temperature 5 HR Mode LP Mode VLP Mode 4 3 2 1 0 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Analog Supply Current (mA) Analog Supply Current (mA) 5 HR Mode LP Mode VLP Mode 4 3 2 1 0 -40 Gain = 1, OSR = 1024, all two ADC channels enabled Figure 6-12. Analog Supply Current vs Temperature 20 40 60 80 Temperature (°C) 100 120 140 Figure 6-13. Analog Supply Current vs Temperature 6 HR Mode LP Mode VLP Mode 0.4 0.3 0.2 IAVDD IDVDD 5 Supply Current (PA) Digital Supply Current (mA) 0 Gain = 8, OSR = 1024, all two ADC channels enabled 0.6 0.5 -20 4 3 2 0.1 1 0 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 0 -40 -20 OSR = 1024 0 20 40 60 80 Temperature (°C) 100 120 140 Standby mode Figure 6-14. Digital Supply Current vs Temperature Figure 6-15. Supply Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 11 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 7 Parameter Measurement Information 7.1 Noise Measurements Adjust the data rate and gain to optimize the ADS131B02-Q1 noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS131B02-Q1 noise performance using the 1.2-V internal reference and a 3.3-V analog power supply. The data are representative of typical noise performance at TA = 25°C when fMCLK = 8.192 MHz. The modulator clock frequency fMOD = fMCLK / 2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the RMS noise for each reading. Table 7-2 shows the effective resolution calculated from the noise data. Equation 1 calculates effective resolution. In each case, VREF corresponds to the internal 1.2-V reference. In global-chop mode, noise is improved by a factor of √2. The noise performance scales with the oversampling rate (OSR) and gain settings, but is independent from the configured power mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the main clock frequency for the different power modes. § 2 u VREF · Effective Resolution = log2 ¨ ¸ © Gain u VRMS ¹ (1) Table 7-1. Noise (μVRMS) at TA = 25°C GAIN OSR DATA RATE (kSPS), fMCLK = 8.192 MHz 1 2 4 8 16 32 64 128 16384 0.25 1.78 1.59 1.58 0.44 0.43 0.42 0.42 0.42 8192 0.5 2.51 2.19 2.07 0.60 0.59 0.58 0.58 0.58 4096 1 3.41 2.97 2.84 0.82 0.81 0.80 0.80 0.80 2048 2 4.54 3.96 3.76 1.07 1.06 1.05 1.05 1.05 1024 4 5.42 4.74 4.52 1.29 1.28 1.27 1.27 1.27 512 8 8.15 6.91 6.50 1.82 1.81 1.80 1.80 1.80 256 16 13.02 10.33 9.37 2.61 2.56 2.53 2.53 2.53 128 32 23.12 16.45 13.64 4.02 3.73 3.63 3.63 3.63 Table 7-2. Effective Resolution at TA = 25°C 12 GAIN OSR DATA RATE (kSPS), fMCLK = 8.192 MHz 1 2 4 8 16 32 64 128 16384 0.25 20.4 19.5 18.5 19.4 18.4 17.4 16.4 15.4 8192 0.5 19.9 19.1 18.1 18.9 18.0 17.0 16.0 15.0 4096 1 19.4 18.6 17.7 18.5 17.5 16.5 15.5 14.5 2048 2 19.0 18.2 17.3 18.1 17.1 16.1 15.1 14.1 1024 4 18.8 17.9 17.0 17.8 16.8 15.8 14.8 13.8 512 8 18.2 17.4 16.5 17.3 16.3 15.3 14.3 13.3 256 16 17.5 16.8 16.0 16.8 15.8 14.9 13.9 12.9 128 32 16.7 16.2 15.4 16.2 15.3 14.3 13.3 12.3 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8 Detailed Description 8.1 Overview The ADS131B02-Q1 is a low-power, two-channel, simultaneous-sampling, 24-bit, delta-sigma (ΔΣ) analog-todigital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and power consumption are optimized for cost-sensitive applications requiring simultaneous sampling. The ADS131B02-Q1 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low as 0.3 V below AGND, which enables measurements of input signals varying around ground with a unipolar power supply. The digital power supply (DVDD – DGND) can operate between 2.7 V and 3.6 V. The device features a high input impedance programmable gain amplifier (PGA) with gains up to 128. The ADC receives its reference voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as the reference. Three power-scaling modes allow designers to trade power consumption for noise performance. Each channel on the ADS131B02-Q1 contains a digital decimation filter that demodulates the output of the ΔΣ modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. Offset and gain calibration registers can be programmed to automatically adjust output samples for measured offset and gain errors. The Functional Block Diagram provides a detailed diagram of the ADS131B02-Q1. The device communicates via a serial peripheral interface (SPI)-compatible interface. Several SPI commands and internal registers control the operation of the ADS131B02-Q1. Other devices can be added to the same SPI bus by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions between multiple ADS131B02-Q1 devices as well as to maintain synchronization with external events. 8.2 Functional Block Diagram AVDD DVDD 1.2-V Reference Oscillator Clock Selection CLKIN SYNC/RESET AIN0P + '6 ADC AIN0N Digital Filter ± Gain & Offset Calibration CS SCLK Control & Serial Interface DIN DOUT AIN1P + AIN1N ± '6 ADC Digital Filter Gain & Offset Calibration AGND DRDY DGND Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 13 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.3 Feature Description 8.3.1 Input ESD Protection Circuitry Basic electrostatic discharge (ESD) circuitry protects the ADS131B02-Q1 inputs from ESD and overvoltage events in conjunction with external circuits and assemblies. Figure 8-1 shows a simplified representation of the ESD circuit. The protection for input voltages exceeding AVDD can be modeled as a simple diode. AVDD AINnP To analog inputs AINnN AVDD Figure 8-1. Input ESD Protection Circuitry The ADS131B02-Q1 has an integrated negative charge pump that allows for input voltages below AGND with a unipolar supply. Consequently, shunt diodes between the inputs and AGND cannot be used to clamp excessive negative input voltages. Instead, the same diode that clamps overvoltage is used to clamp undervoltage at the reverse breakdown voltage. Take care to prevent input voltages or currents from exceeding the limits provided in the Absolute Maximum Ratings table. 8.3.2 Input Multiplexer Each channel of the ADS131B02-Q1 has a dedicated input multiplexer. The multiplexer controls which signals are routed to the ADC channels. Configure the input multiplexer using the MUXn[1:0] bits in the CHn_CFG register. The input multiplexer allows the following inputs to be connected to the ADC channel: • The analog input pins corresponding to the given channel • AGND, which is helpful for offset calibration • Positive dc test signal • Negative dc test signal See the Internal Test Signals section for more information about the test signals. Figure 8-2 shows a diagram of the input multiplexer on the ADS131B02-Q1. MUXn[1:0] = 00 SW To Positive PGA Input AINnP MUXn[1:0] = 10 SW MUXn[1:0] = 11 SW + DC Test Signal ± AGND SW SW MUXn[1:0] = 01 SW SW SW MUXn[1:0] = 01 MUXn[1:0] = 10 AINnN To Negative PGA Input MUXn[1:0] = 00 Figure 8-2. Input Multiplexer 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.3.3 Programmable Gain Amplifier (PGA) Each channel of the ADS131B02-Q1 features an integrated programmable gain amplifier (PGA) that provides gains of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINn bits for each channel in the GAIN register. Varying the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 2 describes the relationship between FSR and gain. Equation 2 uses the internal reference voltage, 1.2 V, as the scaling factor without accounting for gain error caused by tolerance in the reference voltage. FSR = ±1.2 V / Gain (2) Table 8-1 shows the corresponding full-scale ranges for each gain setting. Table 8-1. Full-Scale Range GAIN SETTING FSR 1 ±1.2 V 2 ±600 mV 4 ±300 mV 8 ±150 mV 16 ±75 mV 32 ±37.5 mV 64 ±18.75 mV 128 ±9.375 mV The input impedance of the ADS131B02-Q1 depends on three factors: the main clock frequency (fMCLK), the selected OSR setting, and the global-chop mode setting. Table 8-2 shows typical input impedance values for fMCLK = 8.192 MHz. The input impedance scales indirectly proportional with the MCLK frequency, which means that at fMCLK = 4.096 MHz, the impedance values in Table 8-2 increase by a factor of 2. Minimize the output impedance of the circuit that drives the ADS131B02-Q1 inputs to obtain the best possible gain error, INL, and distortion performance. Table 8-2. Input Impedance (1) OSR SETTING (1) INPUT IMPEDANCE GLOBAL-CHOP DISABLED GLOBAL-CHOP ENABLED 128 6 MΩ 40 MΩ 256 13 MΩ 75 MΩ 512 25 MΩ 150 MΩ 1024 25 MΩ 300 MΩ 2048 25 MΩ 600 MΩ 4096 25 MΩ ≥1 GΩ 8192 25 MΩ ≥1 GΩ 16384 25 MΩ ≥1 GΩ fMCLK = 8.192 MHz, default global-chop delay setting. 8.3.4 Voltage Reference The ADS131B02-Q1 uses an internally generated, low-drift, band-gap voltage to supply the reference for the ADC. The reference has a nominal voltage of 1.2 V, allowing the differential input voltage to swing from –1.2 V to 1.2 V at Gain = 1. The reference circuitry starts up very quickly to accommodate the fast start-up feature of this device. The device waits until after the reference circuitry is fully settled before generating conversion data. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 15 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.3.5 Internal Test Signals The ADS131B02-Q1 features an internal analog test signal that is useful for troubleshooting and diagnosis. A positive or negative dc test signal can be applied to the channel inputs through the input multiplexer. The multiplexer is controlled through the MUXn[1:0] bits in the CHn_CFG register. The test signals are created by internally dividing the reference voltage. The same signal is shared by all channels. The test signal is nominally 2 / 15 × VREF. The test signal automatically adjusts its voltage level with the gain setting such that the ADC always measures a signal that is 2 / 15 × VDiff Max. For example, at a gain of 1, this voltage equates to 160 mV. At a gain of 2, this voltage is 80 mV. 8.3.6 Clocking The ADS131B02-Q1 requires a main clock (MCLK) to operate. The main clock to the ADS131B02-Q1 is provided in one of two ways, as shown in Figure 8-3: an external clock on the CLKIN pin or the internal oscillator. The CLK_SEL bit in the CLOCK register selects the according main clock source for the device. PWR[1:0] CLK_SEL '6 ADC fOSC 8.192 MHz ÷ 1, 2 or 4 Internal Oscillator 0 fMOD MUX ÷2 fMCLK fMOD 1 CLKIN Figure 8-3. Main Clock Selection Diagram 8.3.6.1 External Clock Using CLKIN Pin By default, the ADS131B02-Q1 is configured to operate with an external clock, such as at power-up. An LVCMOS clock must be provided at the CLKIN pin continuously when the ADS131B02-Q1 is running in normal operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a trade-off between power consumption and noise performance. The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: high-resolution (HR), low-power (LP), or very-low-power (VLP). Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. Follow the guidance for the external clock frequency provided in the Recommended Operating Conditions table corresponding to the intended power mode in order for the device to perform according to the specification. 8.3.6.2 Internal Oscillator The internal oscillator can be selected as the MCLK source by setting the CLK_SEL bit in the CLOCK register. At device power-up, the internal oscillator is disabled by default. As shown in Figure 8-3 and Table 8-3, the internal oscillator frequency (fOSC) is scaled using a clock divider to provide the appropriate nominal main clock frequency (fMCLK) for the different power modes. Correspondingly, the modulator clock frequency (fMOD) scales as well because fMOD = fMCLK / 2. Table 8-3. Scaling of the Internal Oscillator Frequency Based on the Selected Power Mode 16 POWER MODE CLOCK DIVIDER SETTING fMCLK fMOD HR 1 8.192 MHz 4.096 MHz LP 2 4.096 MHz 2.048 MHz VLP 4 2.048 MHz 1.024 MHz Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 To switch between a running CLKIN and the internal oscillator as the MCLK source, put the device in standby mode to avoid creating glitches when switching the clock source because there are no clock sequencers in the device. Likewise, put the device in standby mode before changing power modes because a change in power mode changes the MCLK frequency based on the clock divider setting. When always using the internal oscillator as the MCLK source, tie the CLKIN pin to DGND. Tying the CLKIN pin to DGND avoids the need to enter standby mode when switching from an external clock to the internal oscillator at power-up or after a reset. 8.3.7 ΔΣ Modulator The ADS131B02-Q1 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times greater than the output data rate. The modulator frequency, fMOD, of the ADS131B02-Q1 is equal to half the main clock frequency (that is, fMOD = fMCLK / 2). The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization noise, allowing the device to provide excellent dynamic range. 8.3.8 Digital Filter The ΔΣ modulator bit-stream feeds into a digital filter. The digital filter is a linear phase, finite impulse response (FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is decimated and downsampled, to reduce the rate at which data come out of the modulator (fMOD) to the output data rate (fDATA). The decimation factor, defined as per Equation 3, is called the oversampling ratio (OSR). OSR = fMOD / fDATA (3) The OSR is configurable and is set by the OSR[2:0] bits in the CLOCK register. There are eight OSR settings in the ADS131B02-Q1, allowing eight different data rate settings for any given main clock frequency. Table 8-4 lists the OSR settings and their corresponding output data rates for the nominal MCLK frequencies mentioned. The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth results in lower noise, whereas higher bandwidth results in higher noise. See Table 7-1 for the noise specifications for various OSR settings. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 17 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 Table 8-4. OSR Settings and Data Rates for Nominal Main Clock Frequencies POWER MODE NOMINAL fMCLK HR fMOD 8.192 MHz LP 4.096 MHz 4.096 MHz VLP 2.048 MHz 2.048 MHz 1.024 MHz OSR OUTPUT DATA RATE 128 32 kSPS 256 16 kSPS 512 8 kSPS 1024 4 kSPS 2048 2 kSPS 4096 1 kSPS 8192 500 SPS 16384 250 SPS 128 16 kSPS 256 8 kSPS 512 4 kSPS 1024 2 kSPS 2048 1 kSPS 4096 500 SPS 8192 250 SPS 16384 125 SPS 128 8 kSPS 256 4 kSPS 512 2 kSPS 1024 1 kSPS 2048 500 SPS 4096 250 SPS 8192 125 SPS 16384 62.5 SPS 8.3.8.1 Digital Filter Implementation Figure 8-4 shows the digital filter implementation of the ADS131B02-Q1. The modulator bitstream feeds two parallel filter paths, a sinc3 filter, and a fast-settling filter path. OSR[2:0] Sinc3 Regular Filter Modulator Bitstream Power-up or Reset 0 MUX Fast-Settling Filter 265 ” 1024 Sinc1 Averager (OSR > 1024) 0 MUX OSR[2:0] 1 Global Chop Logic Calibration Logic, Gain scaling 1 PGA_GAINx[2:0] OSR = 1024 Figure 8-4. Digital Filter Implementation 8.3.8.1.1 Fast-Settling Filter When the ADCs start converting for the first time after power-up or a device reset, the ADS131B02-Q1 selects the fast-settling filter to allow for settled output data generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc1). After two conversions, the device switches to and remains in the sinc3 filter path until the next time the device is powered down or reset. The fast-settling filter exhibits wider bandwidth and less stop-band attenuation than the sinc3 filter. Consequently, the noise performance when using the fast-settling filter is not as high as with the sinc3 filter. The first two 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 samples available from the ADS131B02-Q1 after a supply ramp or reset have the noise performance and frequency response corresponding to the fast-settling filter as specified in the Electrical Characteristics table, whereas subsequent samples have the noise performance and frequency response consistent with the sinc3 filter. See the Fast Start-Up Behavior section for more details regarding the fast start-up capabilities of the ADS131B02-Q1. 8.3.8.1.2 SINC3 and SINC3 + SINC1 Filter The ADS131B02-Q1 selects the sinc3 filter path two conversions after power-up or device reset. For OSR settings of 128 to 1024, the sinc3 filter output directly feeds into the global-chop and calibration logic. For OSR settings of 2048 and higher, the sinc3 filter is followed by a sinc1 filter. As shown in Table 8-5, the sinc3 filter operates at a fixed OSR of 1024 in this case while the sinc1 filter implements the additional OSRs of 2 to 16. That means, when an OSR of 4096 (for example) is selected, the sinc3 filter operates at an OSR of 1024 and the sinc1 filter at an OSR of 4. The filter has infinite attenuation at integer multiples of the data rate except for integer multiples of fMOD. Like all digital filters, the digital filter response of the ADS131B02-Q1 repeats at integer multiples of the modulator frequency, fMOD. The data rate and filter notch frequencies scale with fMOD. When possible, plan frequencies for unrelated periodic processes in the application for integer multiples of the data rate such that any parasitic effect they have on data acquisition is effectively canceled by the notches of the digital filter. Avoid frequencies near integer multiples of fMOD whenever possible because tones in these bands can alias to the band of interest. The sinc3 and sinc3 + sinc1 filters for a given channel require time to settle after a channel is enabled, the channel multiplexer or gain setting is changed, or a resynchronization event occurs. Table 8-5 lists the settling times of the sinc3 and sinc3 + sinc1 filters for each OSR setting. The ADS131B02-Q1 does not gate unsettled data. Therefore, the host must account for the filter settling time and disregard unsettled data if any are read. The data at the next DRDY falling edge after the filter settling time listed in Table 8-5 has expired can be considered fully settled. Table 8-5. Digital Filter Settling Times OSR (Overall) OSR (SINC3) OSR (SINC1) SETTLING TIME (tMOD) 128 128 N/A 432 256 256 N/A 816 512 512 N/A 1584 1024 1024 N/A 3120 2048 1024 2 6192 4096 1024 4 10288 8192 1024 8 18480 16384 1024 16 34864 8.3.8.2 Digital Filter Characteristic Equation 4 calculates the z-domain transfer function of a sinc3 filter that is used for OSRs ranging from 128 to 1024: 3 H z 1 N1 Z Z N 1 (4) where: • N is the OSR Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 19 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 Equation 5 calculates the transfer function of a sinc3 filter in terms of the continuous-time frequency parameter f: Npf fMOD sin ½H(f)½ = N ´ sin 3 pf fMOD (5) where: • N is the OSR Figure 8-5 and Figure 8-6 show the digital filter response of the fast-settling filter and the sinc3 filter for OSRs ranging from 128 to 1024. Figure 8-7 and Figure 8-8 compare the digital filter responses of the sinc3 filter at an OSR of 1024 and sinc3 + sinc1 filter for an OSR of 4096. 0 0 -20 -1.5 -3 Magnitude (dB) Magnitude (dB) -40 -60 -80 -100 -7.5 -10.5 Fast-settling filter Sinc3 filter -140 Fast-settling filter Sinc3 filter -12 0 1 2 3 Frequency (fIN/fDATA) 4 5 Figure 8-5. Fast-Settling and Sinc3 Digital Filter Response 0 0 -100 -140 0.5 -4 -6 -8 -10 -120 0.4 -2 Magnitude (dB) -80 0.2 0.3 Frequency (fIN/fDATA) 0 -40 -60 0.1 Figure 8-6. Fast-Settling and Sinc3 Digital Filter Response, Pass-Band Detail Sinc3 filter (1024) Sinc3 + Sinc1 filter -20 Magnitude (dB) -6 -9 -120 Sinc3 filter (1024) Sinc3 + Sinc1 filter -12 0 1 2 3 4 5 6 7 8 Frequency (fIN/fDATA) 9 10 11 12 Figure 8-7. Digital Filter Response for OSR = 1024 and OSR = 4096 20 -4.5 0 0.1 0.2 0.3 Frequency (fIN/fDATA) 0.4 0.5 Figure 8-8. Digital Filter Response for OSR = 1024 and OSR = 4096, Pass-Band Detail Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.3.9 Calibration Registers The calibration registers allow for the automatic computation of calibrated ADC conversion results from preprogrammed values. The host can rely on the device to automatically correct for system gain and offset after the error correction terms are programmed into the corresponding device registers. The measured calibration coefficients must be store in external non-volatile memory and programmed into the registers each time the ADS131B02-Q1 powers up or resets because the ADS131B02-Q1 registers are volatile. The offset calibration registers are used to correct for system offset error, otherwise known as zero error. Offset error corresponds to the ADC output when the input to the system is zero. The ADS131B02-Q1 corrects for offset errors by subtracting the contents of the OCALn[23:0] register bits in the CHn_OCAL_MSB and CHn_OCAL_LSB registers from the conversion result for that channel before being output. There are separate CHn_OCAL_MSB and CHnOCAL_LSB registers for each channel, which allows separate offset calibration coefficients to be programmed for each channel. The contents of the OCALn[23:0] bits are interpreted by the device as 24-bit two's complement values, which is the same format as the ADC data. The gain calibration registers are used to correct for system gain error. Gain error corresponds to the deviation of gain of the system from its ideal value. The ADS131B02-Q1 corrects for gain errors by multiplying the ADC conversion result by the value given by the contents of the GCALn[23:0] register bits in the CHn_GCAL_MSB and CHn_GCAL_LSB registers before being output. There are separate CHn_GCAL_MSB and CHn_GCAL_LSB registers for each channel, which allows separate gain calibration coefficients to be programmed for each channel. The contents of the GCALn[23:0] bits are interpreted by the device as 24-bit unsigned values corresponding to linear steps ranging from gains of 0 to 2 – (1 / 223). Table 8-6 describes the relationship between the GCALn[23:0] bit values and the gain calibration factor. Table 8-6. GCALn[23:0] Bit Mapping GCALn[23:0] VALUE GAIN CALIBRATION FACTOR 000000h 0 000001h 1.19 × 10–7 800000h 1 FFFFFEh 2 – 2.38 × 10–7 FFFFFFh 2 – 1.19 × 10–7 The calibration registers do not need to be enabled because they are always in use. The OCALn[23:0] bits have a default value of 000000h resulting in no offset correction. Similarly, the GCALn[23:0] bits default to 800000h resulting in a gain calibration factor of 1. Figure 8-9 shows a block diagram illustrating the mechanics of the calibration registers on one channel of the ADS131B02-Q1. û Modulator Digital Filter To Interface Å 1 OCALn[23:0] 223 GCALn[23:0] Figure 8-9. Calibration Block Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 21 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.3.10 Register Map CRC The ADS131B02-Q1 performs a CRC on its own register map as a means to check for unintended changes to the registers. Enable the register map CRC by setting the REG_CRC_EN bit in the MODE register. When enabled, the device constantly calculates the register map CRC across the registers ranging from address 02h to 12h including the reserved registers. The CRC is calculated beginning with the MSB of register 02h and ending with the LSB of register 12h using the polynomial selected in the CRC_TYPE bit in the MODE register. Two types of CRC polynomials are available: CCITT CRC and ANSI CRC (CRC-16). See Table 8-8 for details on the CRC polynomials. The CRC calculation is initialized with the seed value of FFFFh. The calculated CRC is a 16-bit value and is stored in the REGMAP_CRC register. The calculation is done using one register map bit per MCLK period and constantly checks the result against the previous calculation. The REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes resulting from register writes. The REG_MAP bit is cleared by reading the STATUS register, or when the STATUS register is output as a response to the NULL command. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.4 Device Functional Modes Figure 8-10 shows a state diagram depicting the major functional modes of the ADS131B02-Q1 and the transitions between these modes. POR, pin reset, or RESET command Reset complete Reset STANDBY Standby Mode Continuous Conversion Mode WAKEUP && GC_EN STANDBY WAKEUP && GC_EN GC_EN GC_EN Global Chop Mode Figure 8-10. State Diagram Depicting Device Functional Modes 8.4.1 Power-Up and Reset The ADS131B02-Q1 is reset in one of three ways: by a power-on reset (POR), by the SYNC/RESET pin, or by a RESET command. After a reset occurs, the configuration registers are reset to the default values and the device begins generating conversion data as soon as a valid MCLK is provided. In all three cases a low to high transition on the DRDY pin indicates that the SPI interface is ready for communication. The device ignores any SPI communication before this point. 8.4.1.1 Power-On Reset Power-on reset (POR) is the reset that occurs when a valid supply voltage is first applied. The POR process requires tPOR to complete from when the supply voltages reach 90% of their nominal value to allow for the internal circuitry to power up. The DRDY pin transitions from low to high immediately after tPOR indicating the SPI interface is ready for communication. 8.4.1.2 SYNC/RESET Pin The SYNC/RESET pin is an active low, dual-function pin that generates a reset if the pin is held low for longer than tw(RSL). The device maintains a reset state until SYNC/RESET is returned high. The host must wait for at least tREGACQ after SYNC/RESET is brought high or for the DRDY rising edge before communicating with the device. 8.4.1.3 RESET Command The ADS131B02-Q1 can be reset via the SPI RESET command. The device communicates in frames of a fixed length. Four words are required to complete a frame on the ADS131B02-Q1. The RESET command is transmitted in the first word of the data frame on DIN, but the command is not latched and executed by the device until the entire frame is complete. Terminating the frame early causes the RESET command to be ignored. A device reset occurs immediately after the RESET command is latched. The host must wait for at least tREGACQ or for the DRDY rising edge before communicating with the device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 23 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.4.2 Fast Start-Up Behavior The ADS131B02-Q1 begins generating conversion data shortly after start-up as soon as a valid MCLK signal is provided to the ΔΣ modulators. Fast start-up is accomplished via two mechanisms. First, the device internal power-supply circuitry is designed specifically to enable fast start-up. Second, the digital decimation filter dynamically switches from a fast-settling filter to a sinc3 filter when the sinc3 filter has settled. After the supplies are ramped to 90% of their final values, the device requires tPOR for the internal circuitry to settle. The end of tPOR is indicated by a transition of DRDY from low to high. The transition of DRDY from low to high also indicates the SPI interface is ready to accept commands. The ΔΣ modulators of the ADS131B02-Q1 require CLKIN to toggle after tPOR to begin working, or alternatively, activate the internal oscillator by setting the CLK_SEL bit in the CLOCK register. The modulators begin sampling the input signal after an initial wait time delay of (256 + 44) × tMOD when MCLK begins toggling. Therefore, when using an external clock, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to achieve the fastest possible start-up time. The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the fast-settling filter and the sinc3 filter paths. The fast-settling filter requires only one data rate period to provide settled data. Meanwhile, the sinc3 filter requires three data rate periods to settle. The fast-settling filter generates the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while the sinc3 filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc3 filter path for the third and following samples. Figure 8-11 shows the behavior of the fast-start-up feature when using an external clock that is provided to the device right after the supplies have ramped. Table 8-7 shows the values for the various start-up and settling times relevant to the device start-up. Supplies 90% tSETTLE3 tPOR tDATA tSETTLE1 tDATA DRDY Fast-settling filter data ... CLKIN Sinc3 filter data Fast-settling filter data ... ... Sinc3 filter data ... Figure 8-11. Fast Start-Up Behavior and Settling Times Table 8-7. Fast Start-Up Settling Times for Default OSR = 1024 VALUE (DETAILS) (tMOD) VALUE (tMOD) VALUE AT fMCLK = 8.192 MHz (ms) tDATA = 1/fDATA 1024 1024 0.250 tSETTLE1 256 + 44 + 1024 1324 0.323 tSETTLE3 256 + 44 + 3 × 1024 3372 0.823 PARAMETER The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the sinc3 filter path, but allows the device to provide settled conversion data during the longer settling time of the more accurate sinc3 digital filter. If the level of precision provided by the fast-settling filter is insufficient even for the first samples immediately following start-up, ignore the first two instances of DRDY toggling from high to low and begin collecting data on the third instance. The start-up process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what occurs after power up. However there is no tPOR in the case of a command or pin reset because the supplies are already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × tMOD before providing modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples. Remember to enable the internal oscillator every time again after a reset in case the internal oscillator is to be used, because the device defaults to using an external clock. 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.4.3 Conversion Modes There are two ADC conversion modes on the ADS131B02-Q1: continuous-conversion and global-chop mode. Continuous-conversion mode is a mode where ADC conversions are generated constantly by the ADC at a rate defined by fMOD / OSR. Global-chop mode differs from continuous-conversion mode because global-chop periodically chops (or swaps) the inputs, which reduces system offset errors at the cost of settling time between the points when the inputs are swapped. In either continuous-conversion or global-chop mode, there are three power modes that provide flexible options to scale power consumption with bandwidth and dynamic range. The Power Modes section discusses these power modes in further detail. 8.4.3.1 Continuous-Conversion Mode Continuous-conversion mode is the mode in which ADC data are generated constantly at the rate of fDATA = fMOD / OSR. New data are indicated by a DRDY falling edge at this rate. Continuous-conversion mode is intended for measuring AC signals because this mode allows for higher output data rates than global-chop mode. 8.4.3.2 Global-Chop Mode The ADS131B02-Q1 incorporates a global-chop mode option to reduce offset error and offset drift inherent to the device resulting from mismatch in the internal circuitry to very low levels. When global-chop mode is enabled by setting the GC_EN bit in the GLOBAL_CHOP_CFG register, the device uses the conversion results from two consecutive internal conversions taken with opposite input polarity to cancel the device offset voltage. Conversion n is taken with normal input polarity. The device then reverses the internal input polarity for conversion n + 1. The average of two consecutive conversions (n and n + 1, n + 1 and n + 2, and so on) yields the final offset compensated result. Figure 8-12 shows a block diagram of the global-chop mode implementation. The combined PGA and ADC internal offset voltage is modeled as VOFS. Only this device inherent offset voltage is reduced by global-chop mode. Offset in the external circuitry connected to the analog inputs is not affected by global-chop mode. GC_EN Chop Switch VOFS + Digital Filter ADC AINnP PGA ADC Global-Chop Mode Control Conversion Output AINnN Figure 8-12. Global-Chop Mode Implementation The conversion period in global-chop mode differs from the conversion time when global-chop mode is disabled (tDATA = OSR × tMOD). Figure 8-13 shows the conversion timing for an ADC channel using global-chop mode. Global-chop delay Modulator sampling Conversion start xx Sampling n Data not settled Data not settled Sampling n Swap inputs, digital filter reset xx Sampling n tGC_FIRST CONVERSION Sampling n+1 Data not settled Data not settled Sampling n+1 st nd 1 global-chop conversion result Sampling n+1 x Sampling n+2 2 global-chop conversion result Sampling n+2 tGC_CONVERSION Sampling n+2 Sampling n+3 x x ADC overhead Sampling n+3 Sampling n+3 tDATA Figure 8-13. Conversion Timing With Global-Chop Mode Enabled Every time the device swaps the input polarity, the digital filter is reset. The ADC then always takes three internal conversions to produce one settled global-chop conversion result. The ADS131B02-Q1 provides a programmable delay (tGC_DLY) between the end of the previous conversion period and the beginning of the subsequent conversion period after the input polarity is swapped. This delay allows for external input circuitry to settle because the chopping switches interface directly with the analog Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 25 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 inputs. The GC_DLY[3:0] bits in the GLOBAL_CHOP_CFG register configure the delay after chopping the inputs. The global-chop delay is selected in terms of modulator clock periods from 2 to 65,536 × tMOD. The effective conversion period in global-chop mode follows Equation 6. A DRDY falling edge is generated each time a new global-chop conversion becomes available to the host. The conversion process of all ADC channels in global-chop mode is restarted in the following two conditions so that all channels start sampling at the same time: • Falling edge of SYNC/RESET pin • Change of OSR setting The conversion period of the first conversion after the ADC channels are reset is considerably longer than the conversion period of all subsequent conversions mentioned in Equation 6, because the device first must perform two fully settled internal conversions with the input polarity swapped. The conversion period for the first conversion in global-chop mode follows Equation 7. tGC_CONVERSION = tGC_DLY + 3 × OSR × tMOD (6) tGC_FIRST_CONVERSION = tGC_DLY + 3 × OSR × tMOD + tGC_DLY + 3 × OSR x tMOD + 44 × tMOD (7) Using global-chop mode reduces the ADC noise shown in Table 7-1 at a given OSR by a factor of √2 because two consecutive internal conversions are averaged to yield one global-chop conversion result. The dc test signal cannot be measured in global-chop mode. 8.4.4 Power Modes In both continuous-conversion and global-chop mode, there are three selectable power modes that allow scaling of power with bandwidth and performance: high-resolution (HR) mode, low-power (LP) mode, and very-lowpower (VLP) mode. The mode is selected by the PWR[1:0] bits in the CLOCK register. See the Clocking section for restrictions on the CLKIN frequency for each power mode in case an external clock source is used, or how the main clock frequency is scaled with each power mode in case the internal oscillator is enabled. 8.4.5 Standby Mode Standby mode is a low-power state in which all channels are disabled, and the reference, internal oscillator and other non-essential circuitry are powered down. This mode differs from completely powering down the device because the device retains its register settings. Enter standby mode by sending the STANDBY command. Stop toggling CLKIN when the device is in standby mode and an external clock is used to minimize device power consumption. See the Clocking section for recommendations on how to use standby mode when switching between internal and external clock generation. Exit standby mode by sending the WAKEUP command. 8.4.6 Synchronization Synchronization can be performed by the host to make sure the ADC conversions are synchronized to an external event. For example, synchronization can realign the data capture to the expected timing of the host if a glitch on the clock causes the host and device to become out of synchronization. The SYNC/RESET pin is a multifunction digital input pin that allows the host to synchronize conversions to an external event or to reset the device. See the SYNC/RESET Pin section for more details regarding how the device is reset. Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a MCLK period to trigger synchronization. The device internally compares the leading negative edge of the pulse to its internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin. If the negative edge on SYNC/RESET aligns with the internal data rate clock, the device is determined to be synchronized and therefore no action is taken. If there is misalignment, the digital filters on the device are reset to be synchronized with the SYNC/RESET pulse. In global-chop mode conversions are always immediately restarted at the falling edge of the SYNC/RESET pin. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5 Programming 8.5.1 Serial Interface The ADS131B02-Q1 uses an SPI-compatible interface to configure the device and retrieve conversion data. The device always acts as an SPI peripheral; SCLK and CS are inputs to the interface. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, the SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the controller and peripheral on SCLK falling edges. The interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The device includes the typical SPI signals: SCLK, CS, DIN (MOSI), and DOUT (MISO). In addition, there are two other digital pins that provide additional functionality. The DRDY pin serves as a flag to the host to indicate new conversion data are available. The SYNC/RESET pin is a dual-function pin that allows synchronization of conversions to an external event and allows for a hardware device reset. 8.5.1.1 Chip Select (CS) The CS pin is an active-low input signal that selects the device for communication. The device ignores any communication and DOUT is high impedance when CS is held high. Hold CS low for the duration of a communication frame to maintain proper communication. The interface is reset each time CS is taken high. 8.5.1.2 Serial Data Clock (SCLK) The SCLK pin is an input that serves as the serial clock for the interface. Output data on the DOUT pin transition on the rising edge of SCLK and input data on DIN are latched on the falling edge of SCLK. 8.5.1.3 Serial Data Input (DIN) The DIN pin is the serial data input pin for the device. Serial commands are shifted in through the DIN pin by the device with each SCLK falling edge when the CS pin is low. 8.5.1.4 Serial Data Output (DOUT) The DOUT pin is the serial data output pin for the device. The device shifts out command responses and ADC conversion data serially with each rising SCLK edge when the CS pin is low. This pin assumes a highimpedance state when CS is high. 8.5.1.5 Data Ready (DRDY) The DRDY pin is an active-low digital output that indicates when new conversion data are available for readout. Connect the DRDY pin to a digital input on the host to trigger periodic data retrieval in conversion mode. A high-to-low transition of the DRDY output indicates that new conversion data completed and are ready for readout. The period between DRDY falling edges is the data-rate period. A low level of the DRDY pin indicates that the latest conversion data have not yet been read. DRDY transitions high when the conversion data of the two ADC channels, including those of disabled channels, are shifted out of the device. DRDY stays low if the data read is incomplete, thus indicating that not all ADC data have been retrieved. In case conversion data are not read before the next conversion cycle completes, DRDY transitions high tw(DRH) ahead of the next DRDY falling edge. See the Collecting Data for the First Time or After a Pause in Data Collection section for more information about the behavior of DRDY when data are not consistently read. The DRDY high pulse is blocked when new conversions complete while conversion data are read. Therefore, avoid reading ADC data during the time where new conversions complete in order to achieve consistent DRDY behavior. The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not asserted. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 27 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.1.6 SPI Communication Frames SPI communication on the ADS131B02-Q1 is performed in frames. Each SPI communication frame consists of several words. The word size is configurable as either 16 bits, 24 bits, or 32 bits by programming the WLENGTH[1:0] bits in the MODE register. The interface is full duplex, meaning that the interface is capable of transmitting data on DOUT while simultaneously receiving data on DIN. The input frame that the host sends on DIN always begins with a command. The first word on the output frame that the device transmits on DOUT always begins with the response to the command that was written on the previous input frame. The number of words in a command depends on the command provided. For most commands, there are four words in a frame. On DIN, the host provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled, and two additional words of zeros. Simultaneously on DOUT, the device outputs the response from the previous frame command, two words of ADC data representing the two ADC channels, and a CRC word. Figure 8-14 shows a typical command frame structure. DRDY CS SCLK DIN DOUT Hi-Z Command CRC Response Channel 0 Data Channel 1 Data CRC Hi-Z Command CRC Response Channel 0 Data Figure 8-14. Typical Communication Frame There are some commands that require more or less than words. In the case of a read register (RREG) command where more than a single register is read, the response to the command contains the acknowledgment of the command followed by the register contents requested, which may require a longer frame depending on how many registers are read. See the RREG command section for more details on the RREG command. In the case of a write register (WREG) command where more than a single register is written, the frame extends to accommodate the additional data. See the WREG command section for more details on the WREG command. See the Commands section for a list of all valid commands and their corresponding responses on the ADS131B02-Q1. Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for more information about artificially shortening communication frames. 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.1.7 SPI Communication Words An SPI communication frame with the ADS131B02-Q1 is made of words. Words on DIN can contain commands, register settings during a register write, or a CRC of the input data. Words on DOUT can contain command responses, register settings during a register read, ADC conversion data, or CRC of the output data. Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register. The device defaults to a 24-bit word size. Commands, responses, CRC, and registers always contain 16 bits of actual data. These words are always most significant bit (MSB) aligned, and therefore the least significant bits (LSBs) are zero-padded to accommodate 24- or 32-bit word sizes. ADC conversion data are nominally 24 bits. The ADC truncates its eight LSBs when the device is configured for 16-bit communication. There are two options for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the MODE register. Either the ADC data can be LSB padded with zeros or the data can be MSB sign extended. Figure 8-15 through Figure 8-18 show the locations of the individual bits in an SPI frame for the different word size options using a WREG command frame for writing two registers as an example. CS DIN WREG 15 Register Data 0 0 DOUT 15 Response 15 Register Data 1 0 15 Channel 0 Data 0 15 CRC 0 15 0 Channel 1 Data 0 CRC 0 15 0 15 Figure 8-15. SPI Frame using 16-bit Word Size CS DIN WREG 23 DOUT Register Data 0 8 0 23 Response 23 Register Data 1 8 0 23 Channel 0 Data 8 0 23 CRC 8 0 23 Channel 1 Data 0 0 23 8 0 8 0 CRC 23 Figure 8-16. SPI Frame using 24-bit Word Size CS DIN WREG 31 DOUT Register Data 0 16 0 Response 31 31 Sign ext. 16 0 31 Register Data 1 16 0 Channel 0 Data 24 31 Sign ext. 0 31 CRC 16 0 31 Channel 1 Data 24 16 0 16 0 16 0 16 0 CRC 0 31 Figure 8-17. SPI Frame using 32-bit, sign-extended Word Size CS DIN WREG 31 DOUT Register Data 0 16 0 31 Response 31 Register Data 1 16 0 31 Channel 0 Data 16 0 31 CRC 16 0 31 Channel 1 Data 8 0 31 CRC 8 0 31 Figure 8-18. SPI Frame using 32-bit, zero-padded Word Size 8.5.1.8 Short SPI Frames The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and no ADC data are being output by the device. Read out all expected output data words from each sample period if the ADCs are enabled. Reading all of the data output with each frame provides predictable DRDY pin behavior. If reading out all the data on each output data period is not feasible, see the Collecting Data for the First Time or After a Pause in Data Collection section on how to begin reading data again after a pause from when the ADCs were last enabled. A short frame is not possible when using the RESET command. A full frame must be provided for a device reset to take place when sending the RESET command. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 29 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.1.9 Communication Cyclic Redundancy Check (CRC) The ADS131B02-Q1 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all words in the SPI frame where the CRC is enabled, including zero-padded or sign-extended bits. CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the MODE register. Input CRC is disabled by default. When the input CRC is enabled, the device checks the provided input CRC against the CRC generated based on the input data. A CRC error occurs if the CRC words do not match. The device does not execute any commands, except for the WREG command, if the input CRC check fails. A WREG command always executes even when the CRC check fails. The device sets the CRC_ERR bit in the STATUS register for all cases of a CRC error. The response on the output in the SPI frame following the frame where the CRC error occurred is that of a NULL command, which means the STATUS register plus the conversion data are output in the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is output. The output CRC cannot be disabled and always appears at the end of the output frame. The host can ignore the data if the output CRC is not used. There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE bit in the MODE register. Table 8-8 lists the details of the two CRC types. The CRC calculation is initialized with the seed value of FFFFh to detect errors in the event that DIN or DOUT are stuck low. Table 8-8. CRC Types CRC TYPE CCITT CRC ANSI CRC POLYNOMIAL x16 + x12 + x5 BINARY POLYNOMIAL +1 0001 0000 0010 0001 x16 + x15 + x2 + 1 1000 0000 0000 0101 8.5.1.10 SPI Timeout The ADS131B02-Q1 features an SPI timeout as a means to recover SPI communication, especially in situations where CS is permanently tied low. Enable the SPI timeout using the TIMEOUT bit in the MODE register. When enabled, the entire SPI frame (first SCLK to last SCLK) must complete in 215 MCLK cycles, otherwise the SPI logic will reset. When a timeout happens the device starts interpreting the data starting with the next SCLK as a new SPI frame. 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.2 ADC Conversion Data Format The device provides conversion data for each channel at the data rate. All data are available immediately following DRDY assertion. The conversion status of all channels is available as the DRDY[1:0] bits in the STATUS register. The STATUS register content is automatically output as the response to the NULL command. Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size. The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the setting of the WLENGTH[1:0] bits in the MODE register. Data are given in binary two's complement format. Use Equation 8 to calculate the size of one code (LSB). 1 LSB = (2.4 / Gain) / 224 = +FSR / 223 (8) A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFFFh and a negative full-scale input (VIN ≤ –FSR = –1.2 / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 8-9 summarizes the ideal output codes for different input signals. Table 8-9. Ideal Output Code versus Input Signal INPUT SIGNAL (VIN = VAINP – VAINN) IDEAL OUTPUT CODE ≥ FSR (223 – 1) / 223 7FFFFFh 223 FSR / 000001h 0 000000h –FSR / 223 FFFFFFh ≤ –FSR 800000h Figure 8-19 shows the mapping of the analog input signal to the output codes. 7FFFFFh 000001h 000000h FFFFFFh ¼ Output Code ¼ 7FFFFEh 800001h 800000h ¼ -FS 2 23 FS ¼ -1 -FS 2 0 Input Voltage VIN 23 2 23 FS 2 -1 23 Figure 8-19. Code Transition Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 31 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.3 Commands Table 8-10 contains a list of all valid commands, a short description of their functionality, their binary command word, and the expected response that appears in the following frame. Table 8-10. Command Definitions COMMAND NULL RESET (2) DESCRIPTION RESPONSE 0000 0000 0000 0000 STATUS register Reset the device 0000 0000 0001 0001 1111 1111 0100 0010 STANDBY Place the device into standby mode 0000 0000 0010 0010 0000 0000 0010 0010 WAKEUP Wake the device from standby mode to conversion mode 0000 0000 0011 0011 0000 0000 0011 0011 LOCK Lock the interface such that only the NULL, UNLOCK, and RREG commands are valid 0000 0101 0101 0101 0000 0101 0101 0101 Unlock the interface after the interface is locked 0000 0110 0101 0101 0000 0110 0101 0101 UNLOCK (1) COMMAND WORD No operation RREG Read nnn nnnn plus 1 registers beginning at address a aaaa a 101a aaaa annn nnnn dddd dddd dddd dddd or 111a aaaa annn nnnn (1) WREG Write nnn nnnn plus 1 registers beginning at address a aaaa a 011a aaaa annn nnnn 010a aaaa ammm mmmm (2) When nnn nnnn is 0, the response is the requested register data dddd dddd dddd dddd. When nnn nnnn is greater than 0, the response begins with 111a aaaa annn nnnn, followed by the register data. In this case, mmm mmmm represents the number of registers that are actually written minus one. This value may be less than nnn nnnn in some cases. 8.5.3.1 NULL (0000 0000 0000 0000) The NULL command is the no-operation command that results in no registers read or written, and the state of the device remains unchanged. The intended use case for the NULL command is to read out ADC conversion data. The command response for the NULL command is the contents of the STATUS register. Any invalid command also gives the NULL response. 8.5.3.2 RESET (0000 0000 0001 0001) The RESET command resets the ADC to its register defaults. The command is latched by the device at the end of the frame. A reset occurs immediately after the command is latched. The host must wait for tREGACQ after reset or for the DRDY rising edge before communicating with the device to make sure the registers have assumed their default settings. The device sends an acknowledgment of FF42h when the ADC is properly RESET. The device responds with 0011h if the command word is sent but the frame is not completed and therefore the device is not reset. See the RESET Command section for more information regarding the operation of the reset command. Figure 8-20 illustrates a properly sent RESET command frame. 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 CS SCLK DIN RESET CRC RESET command latched here DOUT Hi-Z Response 'RQ¶W &DUH 'RQ¶W &DUH 'RQ¶W &DUH Hi-Z Figure 8-20. RESET Command Frame 8.5.3.3 STANDBY (0000 0000 0010 0010) The STANDBY command places the device in a low-power standby mode. The command is latched by the device at the end of the frame. The device enters standby mode immediately after the command is latched. See the Standby Mode section for more information. This command has no effect when the device is already in standby mode. 8.5.3.4 WAKEUP (0000 0000 0011 0011) The WAKEUP command returns the device to conversion mode from standby mode. This command has no effect if the device is already in conversion mode. 8.5.3.5 LOCK (0000 0101 0101 0101) The LOCK command locks the interface, preventing the device from accidentally latching unwanted commands that can change the state of the device. When the interface is locked, the device only responds to the NULL, RREG, and UNLOCK commands. The device continues to output conversion data even when locked. 8.5.3.6 UNLOCK (0000 0110 0110 0110) The UNLOCK command unlocks the interface if previously locked by the LOCK command. 8.5.3.7 RREG (101a aaaa annn nnnn) The RREG is used to read the device registers. The binary format of the command word is 101a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin reading and nnn nnnn is the unsigned binary number of consecutive registers to read minus one. There are two cases for reading registers on the ADS131B02-Q1. When reading a single register (nnn nnnn = 000 0000b), the device outputs the register contents in the command response word of the following frame. If multiple registers are read using a single command (nnn nnnn > 000 0000b), the device outputs the requested register data sequentially in order of addresses. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 33 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.3.7.1 Reading a Single Register Read a single register from the device by specifying nnn nnnn as zero in the RREG command word. As with all SPI commands on the ADS131B02-Q1, the response occurs on the output in the frame following the command. Instead of a unique acknowledgment word, the response word is the contents of the register whose address is specified in the command word. Figure 8-21 shows an example of reading a single register. DRDY CS SCLK DIN DOUT Hi-Z RREG CRC Response Channel 0 Data Channel 1 Data CRC Command CRC Register Data Channel 0 Data Hi-Z Figure 8-21. Reading a Single Register 8.5.3.7.2 Reading Multiple Registers Multiple registers are read from the device when nnn nnnn is specified as a number greater than zero in the RREG command word. Like all SPI commands on the ADS131B02-Q1, the response occurs on the output in the frame following the command. Instead of a single acknowledgment word, the response spans multiple words in order to shift out all requested registers. Continue toggling SCLK to accommodate outputting the entire data stream. ADC conversion data are not output in the frame following an RREG command to read multiple registers. Figure 8-22 shows an example of reading multiple registers. CS SCLK DIN DOUT Hi-Z RREG CRC Response Channel 0 Data Channel 1 Data CRC Hi-Z Command CRC RREG ack 1st UHJLVWHU¶V data 2nd UHJLVWHU¶V data N-1th UHJLVWHU¶V data Nth UHJLVWHU¶V data CRC Hi-Z Figure 8-22. Reading Multiple Registers 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.5.3.8 WREG (011a aaaa annn nnnn) The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be written immediately following the command word. Write the intended contents of each register into individual words, MSB aligned. If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as they are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a register. An input CRC error during a WREG command sets the CRC_ERR bit in the STATUS register. The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them. The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm where mmm mmmm is the number of registers actually written minus one. This number can be checked by the host against nnn nnnn to make sure the expected number of registers are written. Figure 8-23 shows a typical WREG sequence. In this example, the number of registers to write is larger than the number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC word. Make sure all of the ADC data and output CRC are shifted out during each transaction where new data are available. Therefore, the frame must be extended beyond the number of words required to send the register data in some cases. DRDY CS SCLK DIN DOUT Hi-Z WREG 1st UHJLVWHU¶V data 2nd UHJLVWHU¶V data 3rd UHJLVWHU¶V data Response Channel 0 Data Channel 1 Data CRC 4th UHJLVWHU¶V data 5th UHJLVWHU¶V data 6th UHJLVWHU¶V data N-1th UHJLVWHU¶V data Nth UHJLVWHU¶V data 'RQ¶W &DUH CRC Hi-Z Command CRC Response Channel 0 Data Figure 8-23. Writing Registers 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection Take special precaution when collecting data for the first time or when beginning to collect data again after a pause. The internal mechanism that outputs data contains a first-in-first-out (FIFO) buffer that can store two samples of data per channel at a time. The DRDY flag for each channel in the STATUS register remains set until both samples for each channel are read from the device. This condition is not obvious under normal circumstances when the host is reading each consecutive sample from the device. In that case, the samples are cleared from the device each time new data are generated so the DRDY flag for each channel in the STATUS register is cleared with each read. However, both slots of the FIFO are full if a sample is missed or if data are not read for a period of time. Either strobe the SYNC/RESET pin to resynchronize conversions and clear the FIFOs, or quickly read two data packets when data are read for the first time or after a gap in reading data. This process maintains predictable DRDY pin behavior. See the Synchronization section for information about the synchronization feature. These methods do not need to be employed if each channel data was read for each output data period from when the ADC was enabled. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 35 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 Figure 8-24 shows an example of how to collect data after a period of the ADC running, but where no data are being retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the ADS131B02-Q1 output data with the host. Time where data is not being read DRDY SYNC / RESET SYNC Pulse CS SCLK DOUT Data Data Hi-Z CRC Status Data CRC Figure 8-24. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by reading two samples in quick succession. Figure 8-25 depicts this method. There is a very narrow pulse on DRDY immediately after the first set of data are shifted out of the device. This pulse may be too narrow for some microcontrollers to detect. Therefore, do not rely upon this pulse, but instead immediately read out the second data set after the first data set. DRDY transitions high after the second data set is read, which indicates that no other new data are available for readout. Time where data is not being read Narrow DRDY Pulse DRDY CS SCLK DOUT Data Data CRC Hi-Z Status Data CRC Status Data CRC Data is read a second time Figure 8-25. Collecting Data After a Pause in Data Collection by Reading Data Twice 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6 Register Map Table 8-11 lists the ADS131B02-Q1 registers. All register addresses not listed in Table 8-11 should be considered as reserved locations and the register contents should not be modified. Table 8-11. Register Map ADDRESS REGISTER RESET VALUE BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DEVICE SETTINGS AND STATUS INDICATORS (Read-Only Registers) 00h ID 42xxh 01h STATUS 0500h RESERVED CHANCNT[3:0] RESERVED LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET RESERVED WLENGTH[1:0] DRDY1 DRDY0 GLOBAL SETTINGS ACROSS CHANNELS 02h MODE RESERVED 0510h 03h CLOCK 038Eh 04h GAIN 0000h 05h RESERVED 06h GLOBAL_CHOP_ CFG 0600h 07h RESERVED 0000h 08h RESERVED 0000h REGCRC_EN RESERVED RX_CRC_EN CRC_TYPE TIMEOUT RESET RESERVED RESERVED CLK_SEL RESERVED OSR[2:0] WLENGTH[1:0] DRDY_HiZ RESERVED CH1_EN CH0_EN PWR[1:0] RESERVED RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0] RESERVED 0000h RESERVED RESERVED GC_DLY[3:0] GC_EN RESERVED RESERVED RESERVED RESERVED RESERVED CHANNEL-SPECIFIC SETTINGS 09h CH0_CFG 0000h 0Ah CH0_OCAL_MSB 0000h 0Bh CH0_OCAL_LSB 0000h 0Ch CH0_GCAL_MSB 8000h 0Dh CH0_GCAL_LSB 0000h 0Eh CH1_CFG 0000h 0Fh CH1_OCAL_MSB 0000h 10h CH1_OCAL_LSB 0000h 11h CH1_GCAL_MSB 8000h 12h CH1_GCAL_LSB 0000h RESERVED RESERVED MUX0[1:0] OCAL0_MSB[15:8] OCAL0_MSB[7:0] OCAL0_LSB[7:0] RESERVED GCAL0_MSB[15:8] GCAL0_MSB[7:0] GCAL0_LSB[7:0] RESERVED RESERVED RESERVED MUX1[1:0] OCAL1_MSB[15:8] OCAL1_MSB[7:0] OCAL1_LSB[7:0] RESERVED GCAL1_MSB[15:8] GCAL1_MSB[7:0] GCAL1_LSB[7:0] RESERVED REGISTER MAP CRC AND RESERVED REGISTERS 3Eh REGMAP_CRC 0000h 3Fh RESERVED 0000h REG_CRC[15:8] REG_CRC[7:0] RESERVED RESERVED Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 37 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 Table 8-12 shows the codes that are used for access types in this section. Table 8-12. Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n Value after reset or the default value 8.6.1 ID Register (Address = 00h) [reset = 42xxh] The ID register is shown in Figure 8-26 and described in Table 8-13. Return to the Summary Table. Figure 8-26. ID Register 15 14 7 13 12 11 10 RESERVED CHANCNT[3:0] R-0100b R-0010b 6 5 4 3 2 9 8 1 0 RESERVED R-xxxxxxxxb Table 8-13. ID Register Field Descriptions Bit Field Type Reset Description RESERVED R 0100b Reserved Always reads 0100b 11:8 CHANCNT[3:0] R 0010b Channel count Always reads 0010b 7:0 RESERVED R xxxxxxxxb Reserved Values are subject to change without notice 15:12 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.2 STATUS Register (Address = 01h) [reset = 0500h] The STATUS register is shown in Figure 8-27 and described in Table 8-14. Return to the Summary Table. Figure 8-27. STATUS Register 15 14 13 12 11 10 9 8 LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0] R-0b R-0b R-0b R-0b R-0b R-1b R-01b 7 6 5 4 3 2 1 0 RESERVED DRDY1 DRDY0 R-000000b R-0b R-0b Table 8-14. STATUS Register Field Descriptions Bit Field Type Reset Description 15 LOCK R 0b SPI interface lock indicator 0b = Unlocked 1b = Locked 14 F_RESYNC R 0b ADC resynchronization indicator Bit is set each time the ADC resynchronizes. 0b = No resynchronization 1b = Resynchronization occurred 13 REG_MAP R 0b Register map CRC fault indicator 0b = No change in the register map CRC 1b = register map CRC changed 12 CRC_ERR R 0b SPI input CRC error indicator 0b = No CRC error 1b = Input CRC error occured 11 CRC_TYPE R 0b CRC type indicator 0b = 16 bit CCITT 1b = 16 bit ANSI 10 RESET R 1b Reset status indicator 0b = No reset occurred 1b = Reset occurred 9:8 WLENGTH[1:0] R 01b Data word length indicator 00b = 16 bit 01b = 24 bits 10b = 32 bits: LSB zero padding 11b = 32 bits: MSB sign extension 7:2 RESERVED R 000000b Reserved Always reads 000000b 1 DRDY1 R 0b Channel 1 ADC data available indicator 0b = No new data available 1b = New data available 0 DRDY0 R 0b Channel 0 ADC data available indicator 0b = No new data available 1b = New data available Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 39 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.3 MODE Register (Address = 02h) [reset = 0510h] The MODE register is shown in Figure 8-28 and described in Table 8-15. Return to the Summary Table. Figure 8-28. MODE Register 15 14 13 12 11 RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0] R/W-00b R/W-0b R/W-0b R/W-0b R/W-1b R/W-01b 4 3 2 7 6 5 10 9 8 1 0 RESERVED TIMEOUT RESERVED DRDY_HiZ RESERVED R/W-000b R/W-1b R/W-00b R/W-0b R/W-0b Table 8-15. MODE Register Field Descriptions Bit Field Type Reset Description RESERVED R/W 00b Reserved Always write 00b 13 REG_CRC_EN R/W 0b Register map CRC enable 0b = Disabled 1b = Enabled 12 RX_CRC_EN R/W 0b SPI input CRC enable 0b = Disabled 1b = Enabled 11 CRC_TYPE R/W 0b SPI and register map CRC type selection 0b = 16 bit CCITT 1b = 16 bit ANSI 10 RESET R/W 1b Reset Write 0b to clear this bit in the STATUS register 0b = No reset occurred 1b = Reset occurred 9:8 WLENGTH[1:0] R/W 01b Data word length selection 00b = 16 bits 01b = 24 bits 10b = 32 bits: LSB zero padding 11b = 32 bits: MSB sign extension 7:5 RESERVED R/W 000b Reserved Always write 000b TIMEOUT R/W 1b SPI Timeout enable 0b = Disabled 1b = Enabled 3:2 RESERVED R/W 00b Reserved Always write 00b 1 DRDY_HiZ R/W 0b DRDY pin state selection when conversion data is not available 0b = Logic high 1b = High impedance 0 RESERVED R/W 0b Reserved Always write 0b 15:14 4 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.4 CLOCK Register (Address = 03h) [reset = 038Eh] The CLOCK register is shown in Figure 8-29 and described in Table 8-16. Return to the Summary Table. Figure 8-29. CLOCK Register 15 14 7 13 6 12 9 8 RESERVED CH1_EN CH0_EN R-000000b R/W-1b R/W-1b 5 4 11 3 10 2 1 0 CLK_SEL RESERVED OSR[2:0] PWR[1:0] R/W-1b R/W-00b R/W-011b R/W-10b Table 8-16. CLOCK Register Field Descriptions Bit Field Type Reset Description RESERVED R 000000b Reserved Always reads 000000b 9 CH1_EN R/W 1b Channel 1 ADC enable 0b = Disabled 1b = Enabled 8 CH0_EN R/W 1b Channel 0 ADC enable 0b = Disabled 1b = Enabled 7 CLK_SEL R/W 1b Clock source selection 0b = Internal oscillator 1b = External clock 6:5 RESERVED R/W 00b Reserved Always write 00b 4:2 OSR[2:0] R/W 011b Modulator oversampling ratio selection 000b = 128 001b = 256 010b = 512 011b = 1024 100b = 2048 101b = 4096 110b = 8192 111b = 16384 1:0 PWR[1:0] R/W 10b Power mode selection 00b = Very-low power 01b = Low power 10b = High resolution 11b = High resolution 15:10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 41 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.5 GAIN Register (Address = 04h) [reset = 0000h] The GAIN register is shown in Figure 8-30 and described in Table 8-17. Return to the Summary Table. Figure 8-30. GAIN Register 15 14 13 12 11 10 9 8 1 0 RESERVED R/W-00000000b 7 6 5 4 3 2 RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0] R/W-0b R/W-000b R/W-0b R/W-000b Table 8-17. GAIN Register Field Descriptions Field Type Reset Description 15:7 Bit RESERVED R/W 00000000 0b Reserved Always write 000000000b 6:4 PGAGAIN1[2:0] R/W 000b PGA gain selection for channel 1 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 RESERVED R/W 0b Reserved Always write 0b PGAGAIN0[2:0] R/W 000b PGA gain selection for channel 0 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 3 2:0 42 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.6 RESERVED Register (Address = 05h) [reset = 0000h] The RESERVED register is shown in Figure 8-33 and described in Table 8-20. Return to the Summary Table. Figure 8-31. RESERVED Register 15 14 13 12 11 10 9 8 2 1 0 RESERVED R/W-00000000b 7 6 5 4 3 RESERVED R/W-00000000b Table 8-18. RESERVED Register Field Descriptions Bit 15:0 Field Type Reset Description RESERVED R/W 00000000 00000000b Reserved Always write 0000000000000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 43 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.7 GLOBAL_CHOP_CFG Register (Address = 06h) [reset = 0600h] The GLOBAL_CHOP_CFG register is shown in Figure 8-32 and described in Table 8-19. Return to the Summary Table. Figure 8-32. GLOBAL_CHOP_CFG Register 15 14 13 12 11 10 9 8 RESERVED GC_DLY[3:0] GC_EN R/W-000b R/W-0011b R/W-0b 7 6 5 4 3 2 1 0 RESERVED R/W-00000000b Table 8-19. GLOBAL_CHOP_CFG Register Field Descriptions Field Type Reset Description 15:13 Bit RESERVED R/W 000b Reserved Always write 000b 12:9 GC_DLY[3:0] R/W 0011b Global chop delay selection Delay in modulator clock periods (tMOD) before measurement begins. 0000b = 2 0001b = 4 0010b = 8 0011b = 16 0100b = 32 0101b = 64 0110b = 128 0111b = 256 1000b = 512 1001b = 1024 1010b = 2048 1011b = 4096 1100b = 8192 1101b = 16484 1110b = 32768 1111b = 65536 GC_EN R/W 0b Global chop enable 0b = Disabled 1b = Enabled RESERVED R/W 00000000b Reserved Always write 00000000b 8 7:0 44 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.8 RESERVED Register (Address = 07h) [reset = 0000h] The RESERVED register is shown in Figure 8-33 and described in Table 8-20. Return to the Summary Table. Figure 8-33. RESERVED Register 15 14 13 12 11 10 9 8 2 1 0 9 8 1 0 RESERVED R/W-00000000b 7 6 5 4 3 RESERVED R/W-00000000b Table 8-20. RESERVED Register Field Descriptions Bit 15:0 Field Type Reset Description RESERVED R/W 00000000 00000000b Reserved Always write 0000000000000000b 8.6.9 RESERVED Register (Address = 08h) [reset = 0000h] The RESERVED register is shown in Figure 8-34 and described in Table 8-21. Return to the Summary Table. Figure 8-34. RESERVED Register 15 14 13 12 11 10 RESERVED R/W-00000000b 7 6 5 4 3 2 RESERVED RESERVED R-0000b R/W-0000b Table 8-21. RESERVED Register Field Descriptions Bit Field Type Reset Description 15:8 RESERVED R/W 00000000b Reserved Always write 00000000b 7:4 RESERVED R 0000b Reserved Always reads 0000b 3:0 RESERVED R/W 0000b Reserved Always write 0000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 45 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.10 CH0_CFG Register (Address = 09h) [reset = 0000h] The CH0_CFG register is shown in Figure 8-35 and described in Table 8-22. Return to the Summary Table. Figure 8-35. CH0_CFG Register 15 14 13 12 11 10 9 2 1 8 RESERVED R/W-00000000b 7 6 5 4 3 0 RESERVED RESERVED RESERVED MUX0[1:0] R/W-00b R-000b R/W-0b R/W-00b Table 8-22. CH0_CFG Register Field Descriptions Field Type Reset Description 15:6 Bit RESERVED R/W 00000000 00b Reserved Always write 0000000000b 5:3 RESERVED R 000b Reserved Always reads 000b 2 RESERVED R/W 0b Reserved Always write 0b MUX0[1:0] R/W 00b Channel 0 input selection 00b = AIN0P and AIN0N 01b = AIN0 disconnected, ADC inputs shorted 10b = Positive dc test signal 11b = Negative dc test signal 1:0 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.11 CH0_OCAL_MSB Register (Address = 0Ah) [reset = 0000h] The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-23. Return to the Summary Table. Figure 8-36. CH0_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL0_MSB[15:8] R/W-00000000b 7 6 5 4 3 OCAL0_MSB[7:0] R/W-00000000b Table 8-23. CH0_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL0_MSB[15:0] R/W 00000000 00000000b Channel 0 offset calibration register bits [23:8] Value provided in two's complement format 8.6.12 CH0_OCAL_LSB Register (Address = 0Bh) [reset = 0000h] The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-24. Return to the Summary Table. Figure 8-37. CH0_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL0_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-24. CH0_OCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 OCAL0_LSB[7:0] R/W 00000000b Channel 0 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved Always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 47 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.13 CH0_GCAL_MSB Register (Address = 0Ch) [reset = 8000h] The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-25. Return to the Summary Table. Figure 8-38. CH0_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL0_MSB[15:8] R/W-10000000b 7 6 5 4 3 GCAL0_MSB[7:0] R/W-00000000b Table 8-25. CH0_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description GCAL0_MSB[15:0] R/W 10000000 00000000b Channel 0 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 8.6.14 CH0_GCAL_LSB Register (Address = 0Dh) [reset = 0000h] The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-26. Return to the Summary Table. Figure 8-39. CH0_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL0_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-26. CH0_GCAL_LSB Register Field Descriptions Bit 48 Field Type Reset Description 15:8 GCAL0_LSB[7:0] R/W 00000000b Channel 0 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 7:0 RESERVED R 00000000b Reserved Always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.15 CH1_CFG Register (Address = 0Eh) [reset = 0000h] The CH1_CFG register is shown in Figure 8-40 and described in Table 8-27. Return to the Summary Table. Figure 8-40. CH1_CFG Register 15 14 13 12 11 10 9 2 1 8 RESERVED R/W-00000000b 7 6 5 4 3 0 RESERVED RESERVED RESERVED MUX1[1:0] R/W-00b R-000b R/W-0b R/W-00b Table 8-27. CH1_CFG Register Field Descriptions Field Type Reset Description 15:6 Bit RESERVED R/W 00000000 00b Reserved Always write 0000000000b 5:3 RESERVED R 000b Reserved Always reads 000b 2 RESERVED R/W 0b Reserved Always write 0b MUX1[1:0] R/W 00b Channel 1 input selection 00b = AIN1P and AIN1N 01b = AIN1 disconnected, ADC inputs shorted 10b = Positive dc test signal 11b = Negative dc test signal 1:0 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 49 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.16 CH1_OCAL_MSB Register (Address = 0Fh) [reset = 0000h] The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-28. Return to the Summary Table. Figure 8-41. CH1_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL1_MSB[15:8] R/W-00000000b 7 6 5 4 3 OCAL1_MSB[7:0] R/W-00000000b Table 8-28. CH1_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL1_MSB[15:0] R/W 00000000 00000000b Channel 1 offset calibration register bits [23:8] Value provided in two's complement format 8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h] The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-29. Return to the Summary Table. Figure 8-42. CH1_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL1_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-29. CH1_OCAL_LSB Register Field Descriptions Bit 50 Field Type Reset Description 15:8 OCAL1_LSB[7:0] R/W 00000000b Channel 1 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved Always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h] The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-30. Return to the Summary Table. Figure 8-43. CH1_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL1_MSB[15:8] R/W-10000000b 7 6 5 4 3 GCAL1_MSB[7:0] R/W-00000000b Table 8-30. CH1_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description GCAL1_MSB[15:0] R/W 10000000 00000000b Channel 1 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h] The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-31. Return to the Summary Table. Figure 8-44. CH1_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL1_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-31. CH1_GCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 GCAL1_LSB[7:0] R/W 00000000b Channel 1 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 7:0 RESERVED R 00000000b Reserved Always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 51 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 8.6.20 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h] The REGMAP_CRC register is shown in Figure 8-45 and described in Table 8-32. Return to the Summary Table. Figure 8-45. REGMAP_CRC Register 15 14 13 12 11 10 9 8 2 1 0 10 9 8 2 1 0 REG_CRC[15:8] R-00000000b 7 6 5 4 3 REG_CRC[7:0] R-00000000b Table 8-32. REGMAP_CRC Register Field Descriptions Bit 15:0 Field Type Reset Description REG_CRC[15:0] R 00000000 00000000b Register map CRC value 8.6.21 RESERVED Register (Address = 3Fh) [reset = 0000h] The RESERVED register is shown in Figure 8-46 and described in Table 8-33. Return to the Summary Table. Figure 8-46. RESERVED Register 15 14 13 12 11 RESERVED R/W-00000000b 7 6 5 4 3 RESERVED R/W-00000000b Table 8-33. RESERVED Register Field Descriptions Bit 15:0 52 Field Type Reset Description RESERVED R/W 00000000 00000000b Reserved Always write 0000000000000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Troubleshooting Table 9-1 lists common issues faced when designing with the ADS131B02-Q1 and the corresponding solutions. This list is not comprehensive. Table 9-1. Troubleshooting Common Issues Using the ADS131B02-Q1 ISSUE POSSIBLE ROOT CAUSE POSSIBLE SOLUTION The F_RESYNC bit is set in the STATUS word even though this bit was already cleared. The SYNC/RESET pin is being toggled asynchronously to CLKIN. The SYNC/RESET pin functions as a constant synchronization check, rather than a convert start pin. See the Synchronization section for more details on the intended usage of the SYNC/RESET pin. The same ADC conversion data are output twice before changing. The entire frame is not being sent to the device. The device does not recognize data as being read. Read all data words in the output data frame, including those for channels that are disabled. 9.1.2 Unused Inputs and Outputs Leave any unused analog inputs floating or connect them to AGND. Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused digital inputs to the appropriate levels, DVDD or DGND. Tie the CLKIN pin to DGND if the internal oscillator is used. Leave the DRDY pin unconnected if unused or connect it to DVDD using a weak pullup resistor. 9.1.3 Antialias Filter An analog low-pass filter is required in front of each of the ADC channel inputs to prevent out-of-band noise and interferers from coupling into the band of interest. Because the ADS131B02-Q1 is a delta-sigma ADC, the integrated digital filter provides substantial attenuation for frequencies outside of the band of interest up to the frequencies adjacent to fMOD. Therefore, a single-order RC filter with a cutoff frequency set at least two decades below the modulator frequency provides sufficient antialiasing protection in the vast majority of applications. Figure 9-1 shows a typical RC filter that yields a cutoff frequency of fC = 39.8 kHz, which is generally a good starting point for a design that uses fMOD = 4.096 MHz. Applications that only need to measure dc signals can use much lower filter-cutoff frequencies by increasing the resistor or capacitor values. Larger resistor values have the added benefit of limiting the current into the ADC inputs in case of an overvoltage event. 200 10 nF To ADC Inputs 200 Figure 9-1. Antialias Filter Example Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 53 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 9.1.4 Minimum Interface Connections Figure 9-2 depicts how the ADS131B02-Q1 can be configured for the minimum number of interface pins. This configuration is useful when using data isolation to minimize the number of isolation channels required or when the microcontroller (MCU) pins are limited. The CLKIN pin requires an LVCMOS clock that can be either generated by the MCU or created using a local LVCMOS output oscillator when the device is configured for use with an external clock. Otherwise tie the CLKIN pin to DGND if the internal oscillator is used. Tie the SYNC/RESET pin to DVDD in hardware if unused. The DRDY pin can be left floating if unused. Connect either SYNC/RESET or DRDY to the MCU to make sure the MCU stays synchronized to ADC conversions. If the MCU provides CLKIN, the CLKIN periods can be counted to determine the sample period rather than forcing synchronization using the SYNC/RESET pin or monitoring the DRDY pin. Synchronization cannot be regained if a bit error occurs on the clock and samples can be missed if the SYNC/RESET or DRDY pins are not used. CS can be tied low in hardware if the ADS131B02-Q1 is the only device on the SPI bus. Make sure the data input and output CRC are enabled and are used to guard against faulty register reads and writes if CS is tied low permanently. Local Oscillator DVDD OR CLKIN CLKOUT SYNC/RESET GPIO OR DRDY Device GPIO CS CS MCU OR SCLK SCLK DIN MOSI DOUT MISO DGND Figure 9-2. Minimum Connections Required to Operate the ADS131B02-Q1 54 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 9.1.5 Multiple Device Configuration Multiple ADS131B02-Q1 devices can be arranged to capture all signals simultaneously. The same clock must be provided to all devices and the SYNC/RESET pins must be strobed simultaneously at least one time to align the sample periods internally between devices. The devices can share the same SPI bus where only the CS pins for each device are unique. Each device can be addressed sequentially by asserting CS for the device that the host wishes to communicate with. The DOUT pin remains high impedance when the CS pin is high, allowing the DOUT lines to be shared between devices as long as no two devices sharing the bus simultaneously have their CS pins low. Figure 9-3 shows multiple devices configured for simultaneous data acquisition while sharing the same SPI bus. Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously. Device 1 SYNC/RESET GPIO CLKIN CLKOUT DRDY IRQ SCLK SCLK DIN MOSI DOUT MISO CS MCU CS1 CS2 ... CSn Device 2 SYNC/RESET CLKIN DRDY SCLK DIN DOUT CS Device n SYNC/RESET CLKIN DRDY SCLK DIN DOUT CS Figure 9-3. Multiple Device Configuration Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 55 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 9.2 Typical Application This section describes a typical battery management system (BMS) application circuit using the ADS131B02-Q1. The device serves the following primary functions in this BMS: • • • Measure battery current with high resolution and accuracy using a low-side current shunt sensor Measure peak currents and detect overcurrent or short-circuit conditions Measure battery-pack voltage using a high-voltage resistor divider Figure 9-4 shows the front-end for the battery management system circuit design. PACK+ AVDD = 3.3 V DVDD = 3.3 V AVDD DVDD 1 …F 1 …F ADS131B02-Q1 RH1 RH2 Battery Pack RH3 AIN0P Battery Pack Voltage Measurement RL AIN0N CLKIN DRDY CS SCLK DIN DOUT SYNC/RESET AIN1P AIN1N Current Shunt Measurement CAP 220 nF PACK- AGND DGND RSHUNT Figure 9-4. ADS131B02-Q1 in a Typical Battery Management System Application 9.2.1 Design Requirements Table 9-2. Design Requirements DESIGN PARAMETER VALUE Current measurement Current measurement range ±5 kA Current shunt value 35 μΩ Update rate 1 ms Battery-pack voltage measurement Voltage measurement range 56 0 V to 800 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 9.2.2 Detailed Design Procedure The following sections provide guidelines for selecting the external components and the configuration of the ADS131B02-Q1 for the various measurements in this application example. 9.2.2.1 Current Shunt Measurement In a typical BMS, the current through the shunt resistor must be measured in both directions for charging and discharging the battery pack. In an overcurrent or short-circuit condition, the current can be as high as I BAT_MAX = ±5 kA in this example application. Therefore, the maximum voltage drop across the shunt is up to VSHUNT = RSHUNT × IBAT_MAX = 35 μΩ × ±4 kA = ±140 mV. In order to measure this shunt voltage, channel 1 of the ADS131B02-Q1 is configured for gain = 8, which allows differential voltage measurements of VIN1 = VAIN1P – VAIN1N = ±VREF / 8 = ±1.2 V / 8 = ±150 mV. The integrated charge pump in the device allows voltage measurements 300 mV below AGND for gains of 4 and higher while using a unipolar analog power supply. This bipolar voltage measurement capability is important because one side of the shunt is connected to the same GND potential as the AGND pin of the ADS131B02-Q1, which means that the absolute voltage that the device must measure is up to 140 mV below AGND. To enable fast overcurrent detection within 1 ms while providing high accuracy and resolution, the ADS131B02Q1 is operated at 4 kSPS (OSR = 1024, high-resolution mode) using global-chop mode. Global-chop mode enables measurements with minimal offset error over temperature and time. The conversion time using these settings is 0.754 ms according to Equation 6. The input-referred noise is approximately 1.29 μVRMS / √2 = 0.91 μVRMS following the explanations in the Noise Measurements section. Thus, currents as small as 0.91 μVRMS / 35 μΩ = 26 mA can be resolved. The resolution can be further improved by averaging the conversion results over a longer period of time in the microcontroller that interfaces with the ADS131B02-Q1. 9.2.2.2 Battery Pack Voltage Measurement The 800-V battery-pack voltage is divided down to the voltage range of the ADS131B02-Q1 using a high-voltage resistor divider (RH1, RH2, RH3, and RL). Gain = 1 is used for channel 0 in this case to allow differential voltage measurements of VIN0 = VAIN0P – VAIN0N = ±1.2 V. The battery-pack voltage measurement is a unipolar, single-ended measurement. Thus, only the voltage range from 0 V to 1.2 V of the ADS131B02-Q1 is used. Equation 9 calculates the resistor divider ratio. VIN / VBAT_MAX = 1.2 V / 800 V = RL / (RL + RH1 + RH2 + RH3) (9) The leakage current drawn by the resistor divider should be less than 100 μA in this example to avoid unnecessarily draining the battery. The resistance of the divider must therefore be larger than RTOTAL ≥ VBAT_MAX / ILEAKAGE = 800 V / 100 μA = 8 MΩ. The resistor values are chosen as RH1 = RH2 = RH3 = 2.8 MΩ and RL = 12.4 kΩ. Thus, the maximum voltage across RL is 1.18 V at VBAT_MAX = 800 V, leaving some headroom to the maximum input voltage of 1.2 V of the ADS131B02-Q1. The maximum resistance of a single resistor that can be used in an automotive circuit design is often limited to a certain value. Also, the maximum voltage a single resistor can withstand is limited. These reasons are why the high-side resistor of the divider is split into multiple resistors (RH1, RH2, and RH3). Another reason is that in case a single resistor has a short-circuit fault, the remaining resistors still limit the current into the ADS131B02-Q1 analog input pin (AIN0P) to safe levels. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 57 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 9.2.3 Application Curves 40 0.4 30 0.3 20 0.2 Gain Error (%) Offset Current Error (mA) Figure 9-5 shows the measurement accuracy of the current measurement (ADC channel 1) over temperature for a 0-A current through the shunt. Figure 9-6 shows the gain error of the current measurement (ADC channel 1) over temperature excluding the error of the shunt. The offset and gain error are calibrated at 25°C. 10 0 -10 0 -0.1 -20 -0.2 -30 -0.3 -40 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Figure 9-5. Offset Current Error vs Temperature 58 0.1 -0.4 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Figure 9-6. Gain Error vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 10 Power Supply Recommendations 10.1 CAP Pin Capacitor Requirement The ADS131B02-Q1 core digital supply voltage of 1.8 V is created by an internal LDO from DVDD. The CAP pin outputs the LDO voltage created from the DVDD supply and requires an external bypass capacitor. Place a 220-nF capacitor on the CAP pin to DGND. 10.2 Power-Supply Sequencing The power supplies can be sequenced in any order but the analog and digital inputs must never exceed the respective analog or digital power-supply voltage limits. 10.3 Power-Supply Decoupling Good power-supply decoupling is important to achieve optimum performance. AVDD and DVDD must each be decoupled with a 1-µF capacitor. Place the bypass capacitors as close to the power-supply pins of the device as possible with low-impedance connections. Using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics are recommended for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins can offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. 11 Layout 11.1 Layout Guidelines For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. Route digital traces away from all analog inputs and associated components in order to minimize interference. Use C0G capacitors on the analog inputs. Use ceramic capacitors (for example, X7R grade) for the powersupply decoupling capacitors. High-K capacitors (Y5V) are not recommended. Place the required capacitors as close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance connections on the ground-side connections of the bypass capacitors. When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to noise within the conversion data. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 59 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 11.2 Layout Example Figure 11-1 shows an example layout of the ADS131B02-Q1 requiring a minimum of two PCB layers. In general, analog signals and planes are partitioned to the left and digital signals and planes to the right. +3.3 V Via to corresponding voltage plane or pour Via to ground plane or pour +3.3 V +3.3 V Place CAP and power supply decoupling capacitors close to pins 1: AVDD 20: DVDD 2: AGND 19: DGND 3: AIN0P 18: CAP 4: AIN0N 17: CLKIN Channel 0 5: AIN1N 16: DIN Device 6: AIN1P 15: DOUT 7: NC 14: SCLK 8: NC 13: DRDY 9: NC 12: CS 10: NC 11: SYNC/RST Channel 1 Differential RC-filter per channel Terminate long digital input lines with resistors to prevent reflection Figure 11-1. Layout Example 60 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 ADS131B02-Q1 www.ti.com SBASAA3 – SEPTEMBER 2021 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131B02-Q1 61 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS131B02QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 A131B02Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of