ADS131E08SPAGR

Order Now Product Folder Technical Documents Support & Community Tools & Software Reference Design ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 ADS131E08S Eight-Channel, 24-Bit, Analog Front-End With Fast Power-Up Time 1 Features 3 Description • • • The ADS131E08S is a multichannel, simultaneous sampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with built-in programmable gain amplifiers (PGAs), an internal reference, and an internal oscillator. The ADC wide dynamic range, scalable data rates, and internal fault detect monitors make the ADS131E08S very attractive in industrial power monitoring, control, and protection applications. Fast power-up time allows data to be available within 3 ms of power being applied to the device for line-powered power applications. True high-impedance inputs enable the ADS131E08S to directly interface with a resistor-divider network or a voltage transformer to measure line voltage, or a current transformer or Rogowski coil to measure line current. With high integration levels and exceptional performance, the ADS131E08S enables the creation of scalable industrial power systems at a significantly reduced size, power, and overall cost. Power-up time: 3 ms Eight differential simultaneous sampling inputs High performance: – Dynamic range at 1 kSPS: 118 dB – Crosstalk: –125 dB – THD: –100 dB at 50 Hz and 60 Hz Low power consumption: 2 mW/channel Data rates: 1, 2, 4, 8, 16, 32, and 64 kSPS Gain options: 1, 2, 4, 8, and 12 Internal voltage reference: 8 ppm/°C Drift Supply range: – Analog: – 2.7 V to 5.25 V (unipolar) – ±2.5 V (bipolar) – Digital: 1.7 V to 3.6 V Fault detection and device self-testing capability SPI™-compatible data interface and four GPIOs Package: 64-pin TQFP Operating temperature range: –40°C to +105°C 1 • • • • • • • • • 2 Applications • Industrial power applications: – Circuit breakers, protection relays, power monitoring Data acquisition systems • Power Application: Three-Phase Voltage and Current Connection Current Sensing Channel 1 PGA û ADC Voltage Sensing Channel 2 PGA û ADC Current Sensing Channel 3 PGA û ADC Channel 4 PGA û ADC Line A Line B Voltage Sensing EMI Filters and Input MUX Device Voltage Reference The complete analog front-end (AFE) solution is available in a 64-pin TQFP package and is specified over the industrial temperature range of –40°C to +105°C. Device Information(1) PART NUMBER ADS131E08S PACKAGE TQFP (64) BODY SIZE (NOM) 10.00 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Oscillator Control and SPI Interface Channel 5 PGA û ADC Voltage Sensing Channel 6 PGA û ADC Fault Detection Current Sensing Channel 7 PGA û ADC Test Channel 8 PGA û ADC Current Sensing The ADS131E08S has an individual input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and fault detection. Fault detection can be implemented internal to the device, using the integrated comparators with digital-to-analog converter (DAC)-controlled trigger levels. The ADS131E08S can operate at data rates as high as 64 kSPS. Line C Line N Voltage Sensing Op Amp 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison ............................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 1 1 1 2 4 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 8 Timing Requirements .............................................. 10 Switching Characteristics ........................................ 10 Typical Characteristics ............................................ 11 8 Parameter Measurement Information ................ 14 9 Detailed Description ............................................ 15 8.1 Noise Measurements .............................................. 14 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description ................................................ Device Functional Modes........................................ 15 16 17 26 9.5 Programming........................................................... 28 9.6 Register Map........................................................... 37 10 Application and Implementation........................ 47 10.1 Application Information.......................................... 47 10.2 Typical Application ................................................ 54 10.3 Initialization Set Up .............................................. 58 11 Power Supply Recommendations ..................... 59 11.1 11.2 11.3 11.4 Power-Up Timing .................................................. 59 Recommended External Capacitor Values ........... 60 Device Connections for Unipolar Power Supplies 60 Device Connections for Bipolar Power Supplies .. 61 12 Layout................................................................... 62 12.1 Layout Guidelines ................................................. 62 12.2 Layout Example .................................................... 63 13 Device and Documentation Support ................. 64 13.1 13.2 13.3 13.4 13.5 Documentation Support ........................................ Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 64 64 64 64 64 14 Mechanical, Packaging, and Orderable Information ........................................................... 64 4 Revision History Changes from Revision A (April 2018) to Revision B Page • Changed – to + in VCM parameter conditions of Recommended Operating Conditions table................................................ 7 • Changed falling edge to rising edge in tDISCK2ST and tDISCK2HT parameter names of Timing Requirements table................. 10 • Added 16-bit or to footnote of Daisy-Chain Interface Timing figure ..................................................................................... 10 • Changed effective number of bits to effective resolution and changed ENOB to effective resolution in Noise Measurements section.......................................................................................................................................................... 14 • Changed EFF RES columns in Input-Referred Noise, 3-V Analog Supply, and 2.4-V Reference and Input-Referred Noise, 5-V Analog Supply, and 4-V Reference tables ......................................................................................................... 14 • Changed CONFIG1 register reset value from D4h to 94h .................................................................................................. 37 • Changed CONFIG3 register reset value from E8h to E0h ................................................................................................... 37 • Changed DAISY_IN reset value from 1h to 0h in CONFIG1 register .................................................................................. 39 Changes from Revision A (January 2016) to Revision B Page • Changed – to + in VCM parameter conditions of Recommended Operating Conditions table................................................ 7 • Changed falling edge to rising edge in tDISCK2ST and tDISCK2HT parameter names of Timing Requirements table................. 10 • Added 16-bit or to footnote of Daisy-Chain Interface Timing figure ..................................................................................... 10 • Changed effective number of bits to effective resolution and changed ENOB to effective resolution in Noise Measurements section.......................................................................................................................................................... 14 • Changed EFF RES columns in Input-Referred Noise, 3-V Analog Supply, and 2.4-V Reference and Input-Referred Noise, 5-V Analog Supply, and 4-V Reference tables ......................................................................................................... 14 • Changed CONFIG1 register reset value from D4h to 94h .................................................................................................. 37 • Changed CONFIG3 register reset value from E8h to E0h ................................................................................................... 37 • Changed DAISY_IN reset value from 1h to 0h in CONFIG1 register .................................................................................. 39 2 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Changes from Original (October 2015) to Revision A • Page Released to production .......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 3 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 5 Device Comparison PRODUCT No. OF INPUTS REFERENCE OPTIONS RESOLUTION (Bits) POWER-UP TIME (ms) ADS130E08 8 Internal, external 16 128 ADS131E04 4 Internal, external 24 128 ADS131E06 6 Internal, external 24 128 ADS131E08 8 Internal, external 24 128 ADS131E08S 8 Internal only 24 3 6 Pin Configuration and Functions 59 DGND 50 DVDD 51 DGND 52 CLKSEL 53 AVSS1 54 AVDD1 55 VCAP3 56 AVDD 57 AVSS 58 AVSS 59 AVDD 60 OPAMPP 61 OPAMPN 62 NC IN8N 1 48 DVDD IN8P 2 47 DRDY IN7N 3 46 GPIO4 IN7P 4 45 GPIO3 IN6N 5 44 GPIO2 IN6P 6 43 DOUT IN5N 7 42 GPIO1 IN5P 8 41 DAISY_IN IN4N 9 40 SCLK Submit Documentation Feedback AVSS 32 RESV1 31 33 DGND VCAP2 30 IN1P 16 NC 29 34 DIN VCAP1 28 IN1N 15 NC 27 35 PWDN VCAP4 26 IN2P 14 VREFN 25 36 RESET VREFP 24 IN2N 13 AVSS 23 37 CLK AVDD 22 IN3P 12 AVDD 21 38 START AVSS 20 IN3N 11 AVDD 19 39 CS TESTN 18 IN4P 10 TESTP 17 4 63 OPAMPOUT 64 NC PAG Package 64-Pin TQFP Top View Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Pin Functions PIN NAME NO. TYPE DESCRIPTION AVDD 19, 21, 22, 56, 59 Supply Analog supply; decouple each AVDD pin to AVSS with a 1-µF capacitor AVDD1 54 Supply Charge pump analog supply; decouple AVDD1 to AVSS1 with a 1-µF capacitor AVSS 20, 23, 32, 57, 58 Supply Analog ground AVSS1 53 Supply Charge pump analog ground; decouple AVDD1 to AVSS1 with a 1-µF capacitor CS 39 Digital input Serial peripheral interface (SPI) chip select; active low CLK 37 Digital input Master clock input; connect to DGND if unused CLKSEL 52 Digital input Master clock select Daisy-chain input; connect to DGND if unused DAISY_IN 41 Digital input 33, 49, 51 Supply Digital ground DIN 34 Digital input SPI data input DOUT 43 Digital output SPI data output DRDY 47 Digital output Data ready; active low; connect to DGND with a 10-kΩ resistor if unused DVDD 48, 50 Supply GPIO1 42 Digital input/output General-purpose input/output pin 1; connect to DGND with a 10-kΩ resistor if unused GPIO2 44 Digital input/output General-purpose input/output pin 2; connect to DGND with a 10-kΩ resistor if unused GPIO3 45 Digital input/output General-purpose input/output pin 3; connect to DGND with a 10-kΩ resistor if unused GPIO4 46 Digital input/output General-purpose input/output pin 4; connect to DGND with a 10-kΩ resistor if unused IN1N (1) 15 Analog input Negative analog input 1 IN1P (1) 16 Analog input Positive analog input 1 IN2N (1) 13 Analog input Negative analog input 2 IN2P (1) 14 Analog input Positive analog input 2 (1) 11 Analog input Negative analog input 3 IN3P (1) 12 Analog input Positive analog input 3 IN4N (1) 9 Analog input Negative analog input 4 DGND IN3N IN4P (1) Digital power supply; decouple each DVDD pin to DGND with a 1-µF capacitor 10 Analog input Positive analog input 4 IN5N (1) 7 Analog input Negative analog input 5 IN5P (1) 8 Analog input Positive analog input 5 (1) 5 Analog input Negative analog input 6 IN6P (1) 6 Analog input Positive analog input 6 IN7N (1) 3 Analog input Negative analog input 7 IN7P (1) 4 Analog input Positive analog input 7 (1) 1 Analog input Negative analog input 8 IN8P (1) 2 Analog input Positive analog input 8 27, 29, 62, 64 — IN6N IN8N NC No connection, leave floating; can be connected to AVDD or AVSS with a 10-kΩ or higher resistor OPAMPN 61 Analog input OPAMPOUT 63 Analog output OPAMPP 60 Analog input Op amp noninverting input; leave floating if unused and power-down the op amp PWDN 35 Digital input Power-down; active low RESET 36 Digital input System reset; active low RESV1 31 Digital input Reserved for future use; must tie to logic low; connect to DGND SCLK 40 Digital input SPI clock (1) Op amp inverting input; leave floating if unused and power-down the op amp Op amp output; leave floating if unused and power-down the op amp Connect any unused or powered down analog input pins to AVDD. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 5 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Pin Functions (continued) PIN NAME NO. TYPE DESCRIPTION START 38 Digital input TESTN (1) 18 Analog input/output Start conversion Test signal, negative pin; connect to DGND with a 10-kΩ resistor if unused TESTP (1) 17 Analog input/output Test signal, positive pin; connect to DGND with a 10-kΩ resistor if unused VCAP1 28 Analog output Analog bypass capacitor; connect a 470-pF capacitor to AVSS VCAP2 30 Analog output Analog bypass capacitor; connect a 270-nF capacitor to AVSS VCAP3 55 Analog output Analog bypass capacitor; connect a 270-nF capacitor to AVSS VCAP4 26 Analog output Analog bypass capacitor; connect a 270-nF capacitor to AVSS VREFN 25 Analog input VREFP 24 Analog output Negative reference voltage; connect to AVSS Positive reference voltage output; connect a 330-nF capacitor to VREFN 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT AVDD to AVSS –0.3 5.5 V DVDD to DGND –0.3 3.9 V AVSS to DGND –3 0.2 V Analog input voltage AVSS – 0.3 AVDD + 0.3 V Digital input voltage DGND – 0.3 DVDD + 0.3 V Digital output voltage DGND – 0.3 DVDD + 0.3 V Continuous input current to any pin except supply pins (2) –10 10 mA Junction temperature, TJ –40 150 °C Storage temperature, Tstg –60 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current limited to 10 mA or less. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 or ANSI/ESDA/JEDEC JS-002 (2) ±500 UNIT V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY AVDD Analog power supply AVDD to AVSS 2.7 5.0 5.25 V DVDD Digital power supply DVDD to DGND 1.7 1.8 3.6 V Analog to digital supply AVDD to DVDD –2.1 3.6 V –VREF / Gain VREF / Gain V ANALOG INPUTS VIN Differential input voltage VIN = V(AINP) – V(AINN) VCM Common-mode input voltage VCM = (V(AINP) + V(AINN)) / 2 See the Input Common-Mode Range section V VOLTAGE REFERENCE INPUTS REFN Negative reference input AVSS V EXTERNAL CLOCK SOURCE fCLK Master clock rate CLKSEL pin = 0, (AVDD – AVSS) = 3 V 1.7 2.048 2.25 CLKSEL pin = 0, (AVDD – AVSS) = 5 V 1.0 2.048 2.25 MHz DIGITAL INPUTS Input voltage DGND – 0.1 DVDD + 0.1 V –40 105 °C TEMPERATURE RANGE TA Operating ambient temperature 7.4 Thermal Information ADS131E08S THERMAL METRIC (1) PAG (TQFP) UNIT 64 PINS RθJA Junction-to-ambient thermal resistance 46.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.8 °C/W RθJB Junction-to-board thermal resistance 19.6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 19.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 7 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 7.5 Electrical Characteristics Minimum and maximum specifications apply from TA = –40°C to +105°C. Typical specifications are at TA = 25°C. All specifications are at DVDD = 1.8 V, AVDD = 5 V, AVSS = 0 V, VREF = 4 V, external fCLK = 2.048 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Ci Input capacitance IIB Input bias current PGA output in normal range DC input impedance 20 pF 5 nA 200 MΩ PGA PERFORMANCE BW Gain settings 1, 2, 4, 8, 12 Bandwidth See Table 3 V/V ADC PERFORMANCE DR Data rate fCLK = 2.048 MHz Resolution DR = 1 kSPS, 2 kSPS, 4 kSPS, 8 kSPS, and 16 kSPS 1 24 DR = 32 kSPS and 64 kSPS 16 4 64 kSPS Bits CHANNEL PERFORMANCE (DC Performance) INL Integral nonlinearity Dynamic range Offset error (1) EO Full-scale, best fit 10 Data rate = 4 kSPS, gain = 1 Gain settings other than 1 Gain = 1 Gain error Excluding voltage reference error Gain drift Excluding voltage reference drift dB See the Noise Measurements section –100 Offset error drift (1) EG ppm 116 –450 –800 0.2 2.5 µV µV/°C 0.1% Gain match between channels 3 ppm/°C 0.2 % of FS CHANNEL PERFORMANCE (AC Performance) CMRR Common-mode rejection ratio fCM = 50 Hz or 60 Hz (2) PSRR Power-supply rejection ratio fPS = 50 Hz or 60 Hz –80 Crosstalk fIN = 50 Hz or 60 Hz –125 SNR THD Signal-to-noise ratio Total harmonic distortion –110 fIN = 50 Hz or 60 Hz, amplitude = –0.5 dBFS, normalized 108 fIN = 50 Hz or 60 Hz, amplitude = –15 dBFS, normalized 115 fIN = 50 Hz or 60 Hz, amplitude = –0.5 dBFS –102 fIN = 50 Hz or 60 Hz, amplitude = –15 dBFS –107 dB dB –113 dB dB dBc INTERNAL VOLTAGE REFERENCE VREF Output voltage (1) TA = 25°C, VREF = 2.4 V, VREF_4V = 0 TA = 25°C, VREF = 4 V, VREF_4V = 1 2.4 3.88 4 4.12 V Accuracy TA = 25°C Temperature drift TA = –40°C ≤ TA ≤ 105°C ±0.2% 8 ppm/°C Power-up time VCAP1 = 470 pF, VREFP = 330 nF, settled to 0.2% 1 ms INTERNAL OSCILLATOR Internal oscillator clock frequency Internal oscillator accuracy (1) 2.048 TA = 25°C –40°C ≤ TA ≤ +105°C Power-up time Internal oscillator power consumption (1) (2) 8 MHz ±1% ±3% 20 µs 120 µW Minimum and maximum values are specified by design and characterization data. CMRR is measured with a common-mode signal of (AVSS + 0.3 V) to (AVDD – 0.3 V). The values indicated are the minimum of the eight channels. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +105°C. Typical specifications are at TA = 25°C. All specifications are at DVDD = 1.8 V, AVDD = 5 V, AVSS = 0 V, VREF = 4 V, external fCLK = 2.048 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATIONAL AMPLIFIER Integrated noise 0.1 Hz to 250 Hz Noise density 2 kHz GBP Gain bandwidth product 50-kΩ || 10-pF load 100 kHz SR Slew rate 50-kΩ || 10-pF load 0.25 V/µs Load current THD Total harmonic distortion VCM Common-mode input range 9 µVRMS 120 nV/√Hz 50 fIN = 100 Hz µA 70 AVSS + 0.7 dB AVDD – 0.3 Quiescent current consumption V 20 µA ±30 mV FAULT DETECT AND ALARM Comparator threshold accuracy SYSTEM MONITORS Analog supply reading error 2% Digital supply reading error Device wake-up 2% From standby mode 31.25 µs TEMPERATURE SENSOR Offset voltage TA = 25°C (3) Temperature coefficient (3) 144 mV 400 µV/°C SELF-TEST SIGNAL fCLK / 221 Signal frequency Hz fCLK / 220 ±1 Signal voltage mV ±2 Accuracy ±2% DIGITAL INPUTS AND OUTPUTS High-level input voltage (1) VIH DVDD = 1.7 V to 1.8 V DVDD – 0.2 V DVDD = 1.8 V to 3.6 V 0.8 DVDD V DVDD = 1.7 V to 1.8 V VIL Low-level input voltage (1) VOH High-level output voltage (1) IOH = –500 µA VOL Low-level output voltage (1) IOL = 500 µA IIN Input current 0 V < VDigital_Input < DVDD DVDD = 1.8 V to 3.6 V DGND – 0.1 DVDD + 0.1 V DGND + 0.2 V 0.2 DVDD V 0.9 DVDD V –10 0.1 DVDD V 10 µA SUPPLY CURRENT (Operational Amplifier Turned Off) IAVDD Analog supply current IDVDD Digital supply current AVDD – AVSS = 3 V 5.1 AVDD – AVSS = 5 V 5.8 DVDD = 3.3 V 1 DVDD = 1.8 V 0.4 Normal mode, AVDD – AVSS = 3 V 16 Standby mode, AVDD – AVSS = 3 V 2 mA mA POWER DISSIPATION (8 Channels Powered Up) Power dissipation (3) Power-down mode, AVDD – AVSS = 3 V mW 10 Normal mode, AVDD – AVSS = 5 V (1) 29.7 Standby mode, AVDD – AVSS = 5 V 4.2 Power-down mode, AVDD – AVSS = 5 V 20 µW 32.9 mW µW See the Temperature Sensor (TempP, TempN) section for more information. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 9 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 7.6 Timing Requirements over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted) 2.7 V ≤ DVDD ≤ 3.6 V tCLK Master clock period tCSSC Delay time, first SCLK rising edge after CS falling edge tSCLK 1.7 V ≤ DVDD ≤ 2 V MIN MAX MIN MAX 444 588 444 588 UNIT ns 6 17 ns SCLK period 50 66.6 ns tSPWH, L Pulse duration, SCLK high or low 15 25 ns tDIST Setup time, DIN valid before SCLK falling edge 10 10 ns tDIHD Hold time, DIN valid after SCLK falling edge 10 11 ns tCSH Pulse duration, CS high 2 2 tCLK tSCCS Delay time, CS rising edge after final SCLK falling edge 4 4 tCLK tSDECODE Command decode time 4 4 tCLK tDISCK2ST Setup time, DAISY_IN valid before SCLK rising edge 10 10 ns tDISCK2HT Hold time, DAISY_IN valid after SCLK rising edge 10 10 ns 7.7 Switching Characteristics over operating ambient temperature range, DVDD = 1.7 V to 3.6 V, and load on DOUT = 20 pF || 100 kΩ (unless otherwise noted) 2.7 V ≤ DVDD ≤ 3.6 V PARAMETER MIN tCSDOD Propagation delay time, CS falling edge to DOUT driven tDOST Propagation delay time, SCLK rising edge to valid new DOUT tDOHD Hold time, SCLK falling edge to invalid DOUT tCSDOZ Propagation delay time, CS rising edge to DOUT high impedance 1.7 V ≤ DVDD ≤ 2.0 V MAX MIN 10 MAX 20 17 ns 32 10 10 10 UNIT ns ns 20 ns tCLK CLK t CSSC 1 2 8 3 t DIHD t DIST t SPWL t SPWH t SCLK SCLK t CSH t SDECODE CS 1 2 t SCCS 3 t DOHD 8 t DOST DIN t CSDOZ t CSDOD DOUT Hi-Z Hi-Z NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing tDISCK2ST DAISY_IN SCLK 1 tDISCK2HT LSB MSB 2 3 n n+1 n+2 n+3 tDOST DOUT (1) MSB LSB 0 MSB n = Number of channels × resolution + 24 bits. Number of channels is 8; resolution is 16-bit or 24-bit. Figure 2. Daisy-Chain Interface Timing 10 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 7.8 Typical Characteristics 10 2200 8 2000 6 1800 4 1600 Occurences 2 0 −2 −4 1400 1200 1000 800 600 −6 400 −8 200 −10 0 1 2 3 4 5 6 Time (s) 7 8 9 0 10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 Input-Referred Noise (µV) at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted) G003 Input−Referred Noise (µV) Data rate = 1 kSPS, gain = 1 G004 Data rate = 1 kSPS, gain = 1 Figure 3. Input-Referred Noise Figure 4. Noise Histogram -70 −90 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 12 −95 −105 THD (dB) CMRR (dB) −100 PGA Gain 1 2 4 -80 8 12 -85 -75 −110 −115 -90 -95 −120 -100 −125 -105 −130 10 100 Frequency (Hz) 1000 G005 -110 10 20 Data rate = 4 kSPS, VIN = AVDD – 0.3 V to AVSS + 0.3 V G=4 G=8 G = 12 Integral Nonlinearity (ppm) Power−Supply Rejection Ratio (dB) 110 G=1 G=2 100 95 90 85 80 10 100 Frequency (Hz) 1000 G007 500 700 1000 D006 Figure 6. Total Harmonic Distortion vs Frequency Figure 5. Common-Mode Rejection Ratio vs Frequency 105 30 40 50 70 100 200 300 Frequency (Hz) 14 12 10 8 6 4 2 0 −2 −4 −6 −8 −10 −12 −14 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 12 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 Input (Normalized to Full−Scale) Figure 7. PSRR vs Frequency 0.8 Product Folder Links: ADS131E08S G008 Figure 8. INL vs PGA Gain Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated 1 11 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted) 0 −40°C +105°C +25°C 16 -20 -40 8 Amplitude (dBFS) Integral Nonlinearity (ppm) 24 0 −8 −16 −24 -60 -80 -100 -120 -140 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 Input (Normalized to Full−Scale) 0.8 -160 1 -180 G009 0 100 200 300 Frequency (Hz) 400 500 D010 Gain = 1, THD = –101.5 dB, SNR = 111 dB, data rate = 1 kSPS, 16384 points Figure 10. THD FFT Plot 0 0 -20 -20 -40 -40 Amplitude (dBFS) Amplitude (dBFS) Figure 9. INL vs Temperature -60 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 400 800 1200 Frequency (Hz) 1600 0 2000 4000 8000 12000 16000 20000 24000 28000 32000 Frequency (Hz) D017 D011 Gain = 1, THD = –100 dB, SNR = 107 dB, data rate = 4 kSPS, 16384 points Gain = 1, THD = –100 dB, SNR = 76 dB, data rate = 64 kSPS, 16384 points Figure 11. THD FFT Plot Figure 12. FFT Plot 350 0.5 AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V 300 Offset Drift (uV/oC) Offset (mV) 0.4 0.3 0.2 250 200 150 100 0.1 50 0 0 1 2 3 4 5 6 7 PGA Gain 8 9 10 11 12 1 2 D012 Figure 13. Offset vs PGA Gain (Absolute Value) 12 Submit Documentation Feedback 3 4 5 6 7 PGA Gain 8 9 10 11 12 D013 Figure 14. Offset Drift vs PGA Gain Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted) 32 4.02 AVDD = 3 V AVDD = 5 V 28 4.015 4.01 4.005 20 Vref (V) Power (mW) 24 16 12 8 3.99 3.985 3.98 4 0 4 3.995 3.975 0 1 2 3 4 5 6 Number of Channels Disabled 7 8 G014 3.97 -40 -20 0 20 40 60 Temperature (oC) 80 100 120 D015 AVDD = 5 V, AVSS = 0 V, VREF = 4 V Figure 15. Channel Power Figure 16. Internal VREF vs Temperature Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 13 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 8 Parameter Measurement Information 8.1 Noise Measurements Adjust the data rate and PGA gain to optimize the ADS131E08S noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Increasing the PGA gain reduces the inputreferred noise, which is particularly useful when measuring low-level signals. Table 1 summarizes the ADS131E08S noise performance with a 3-V analog power supply. Table 2 summarizes the ADS131E08S noise performance with a 5-V analog power supply. Data are representative of typical noise performance at TA = 25°C. Data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS noise for each reading. For the two highest data rates, noise is limited by the ADC quantization noise and does not have a Gaussian distribution. Table 1 and Table 2 show measurements taken with an internal reference. Data are representative of the ADS131E08S noise performance shown in both effective resolution (EFF RES) and dynamic range when using a low-noise external reference (such as the REF5025). Effective resolution data in Table 1 and Table 2 are calculated using Equation 1 and dynamic range data in Table 1 and Table 2 are calculated using Equation 2. § 2 u VREF · Effective Resolution = log2 ¨ ¸ © Gain u VRMS ¹ Dynamic Range 20 u log10 (1) VREF 2 u VRMS _ Noise u Gain (2) Table 1. Input-Referred Noise, 3-V Analog Supply, and 2.4-V Reference PGA GAIN DR BITS (CONFIG1 Register) OUTPUT DATA RATE (kSPS) –3-dB BANDWIDTH (Hz) DYNAMIC RANGE (dB) 000 64 16768 74.1 001 32 8384 010 16 011 x1 x2 EFF RES DYNAMIC RANGE (dB) 12.81 74.1 89.6 15.39 4192 102.8 8 2096 100 4 101 110 x4 EFF RES DYNAMIC RANGE (dB) 12.80 74.0 89.6 15.38 17.57 102.3 108.2 18.5 1048 111.4 2 524 1 262 x8 EFF RES DYNAMIC RANGE (dB) 12.79 74.0 89.4 15.35 17.49 100.6 107.4 18.4 19.1 109.4 114.6 19.6 117.7 20.1 x12 EFF RES DYNAMIC RANGE (dB) EFF RES 1279 73.9 12.77 88.6 15.31 87.6 15.05 17.22 97.1 16.62 94.2 16.15 105.2 18.0 101.6 17.4 98.9 17.0 18.9 107.4 18.6 103.5 17.9 100.5 17.5 113.7 19.5 111.4 19.1 107.7 18.5 104.9 18.0 116.8 20.0 114.5 19.6 110.7 19.0 108.0 18.5 Table 2. Input-Referred Noise, 5-V Analog Supply, and 4-V Reference PGA GAIN DR BITS (CONFIG1 Register) OUTPUT DATA RATE (kSPS) –3-dB BANDWIDTH (Hz) DYNAMIC RANGE (dB) 000 64 16768 74.7 001 32 8384 010 16 011 14 x1 x2 EFF RES DYNAMIC RANGE (dB) 12.91 74.7 90.3 15.51 4192 104.3 8 2096 100 4 101 110 x4 EFF RES DYNAMIC RANGE (dB) 12.91 74.7 90.3 15.50 17.83 104.0 112.3 19.3 1048 116.0 2 524 1 262 x8 EFF RES DYNAMIC RANGE (dB) 12.91 74.7 90.2 15.49 17.78 103.1 111.6 19.1 19.8 115.2 119.1 20.3 122.1 20.9 x12 EFF RES DYNAMIC RANGE (dB) EFF RES 12.91 74.6 12.89 89.9 15.43 89.4 15.35 17.62 100.5 17.30 98.1 16.80 109.7 18.8 106.3 18.2 103.8 17.8 19.7 113.1 19.3 109.5 18.8 106.9 18.3 118.2 20.2 116.2 19.9 112.6 193 109.9 18.8 121.3 20.7 119.1 20.4 115.6 19.8 112.9 19.3 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9 Detailed Description 9.1 Overview The ADS131E08S is a low-power, 8-channel, simultaneously-sampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with an integrated programmable gain amplifier (PGA) and short start-up time. The analog device performance across a scalable data rate makes the device well-suited for smart-grid and other industrial power monitor, control, and protection applications. The ADS131E08S has a programmable multiplexer that allows for various internal monitoring signal measurements including temperature, supply, and input short for device noise testing. The PGA gain can be chosen from one of five settings: 1, 2, 4, 8, or 12. The ADCs in the device offer data rates of 1 kSPS, 2 kSPS, 4 kSPS, 8 kSPS, 16 kSPS, 32 kSPS, and 64 kSPS. The device communicates using a serial peripheral interface (SPI)-compatible interface. The device provides four general-purpose I/O (GPIO) pins for general use. Use multiple devices to easily add channels to the system and synchronize them with the START pins. Program the internal reference to either 2.4 V or 4 V. The internal oscillator generates a 2.048-MHz clock. Use the integrated comparators, with programmable trigger-points, for input overrange or underrange detection. A detailed diagram of the ADS131E08S is provided in the Functional Block Diagram section. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 15 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.2 Functional Block Diagram AVDD AVDD1 VREFP Test Signal Temperature Fault Detect Supply Check VREFN DVDD Reference DRDY IN1P EMI Filter û ADC1 PGA1 IN1N SPI IN2P EMI Filter PGA2 û ADC2 EMI Filter PGA3 û ADC3 PGA4 û ADC4 PGA5 û ADC5 CS SCLK DIN DOUT IN2N IN3P IN3N CLKSEL IN4P EMI Filter IN4N Control Oscillator CLK MUX GPIO1 IN5P EMI Filter GPIO2 GPIO3 IN5N GPIO4 IN6P PGA6 û ADC6 EMI Filter PGA7 û ADC7 EMI Filter PGA8 û ADC8 EMI Filter IN6N PWDN IN7P RESET IN7N START IN8P IN8N Operational Amplifier AVSS AVSS1 16 OPAMPOUT OPAMPN OPAMPP Submit Documentation Feedback DGND Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.3 Feature Description 9.3.1 Electromagnetic Interference (EMI) Filter An RC filter at the input functions as an EMI filter on all channels. The –3-dB filter bandwidth is approximately 3 MHz. 9.3.2 Input Multiplexer The ADS131E08S input multiplexers are very flexible and provide many configurable signal-switching options. Figure 17 shows a diagram of the multiplexer on a single channel of the device. INxP and INxN are separate for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration, and configuration. Switch settings for each channel are selected by writing the appropriate values to the CHnSET registers (see the CHnSET registers in the Register Map section for details). The output of each multiplexer is connected to the individual channel PGA. Device MUX INT_TEST TESTP INT_TEST MUX[2:0] = 101 TestP TempP MvddP(1) MUX[2:0] = 100 MUX[2:0] = 011 MUX[2:0] = 000 INxP MUX[2:0] = 001 (VREFP + VREFN) EMI Filter 2 MUX[2:0] = 000 INxN MvddN(1) TempN To PGA MUX[2:0] = 001 To PGA MUX[2:0] = 011 MUX[2:0] = 100 MUX[2:0] = 101 TestN INT_TEST TESTN INT_TEST (1) MVDD monitor voltage supply depends on channel number; see the Power-Supply Measurements (MVDDP, MVDDN) section. Figure 17. Input Multiplexer Block for One Channel Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 17 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Feature Description (continued) 9.3.2.1 Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(V(VREFP) + V(VREFN)) / 2] to both channel inputs. Use this setting to test inherent device noise in the user system. 9.3.2.2 Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at powerup. The test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls the switching frequency of the test signal. The test signals are multiplexed and transmitted out of the device at the TESTP and TESTN pins. The INT_TEST register bit (in the CONFIG2: Configuration Register 2 section) deactivates the internal test signals so that the test signal can be driven externally. This feature allows the test or calibration of multiple devices with the same signal. 9.3.2.3 Temperature Sensor (TempP, TempN) Setting CHnSET[2:0] = 100 sets the channel input to the temperature sensor. This sensor uses two internal diodes with one diode having a current density 16 times that of the other, as shown in Figure 18. The difference in diode current densities yields a difference in voltage that is proportional to absolute temperature. Temperature Sensor Monitor AVDD 1x 2x To MUX TempP To MUX TempN 8x 1x AVSS Figure 18. Temperature Sensor Implementation The internal device temperature tracks the PCB temperature closely because of the low thermal resistance of the package to the PCB. Self-heating of the ADS131E08S causes a higher reading than the temperature of the surrounding PCB. Setting the channel gain to 1 is recommended when the temperature measurement is taken. The scale factor of Equation 3 converts the temperature reading to °C. Before using this equation, the temperature reading code must first be scaled to μV. § VTemperature (PV) 144,000 PV · Temperature (q C) ¨¨ ¸¸ 400 PV / q C © ¹ (3) 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different device supply voltages. For channels 1, 2, 5, 6, 7, and 8 (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channels 3 and 4 (MVDDP – MVDDN) is DVDD / 4. Set the gain to 1 to avoid saturating the PGA when measuring power supplies. 18 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Feature Description (continued) 9.3.3 Analog Input The analog inputs to the device connect directly to an integrated low-noise, low-drift, high input impedance, programmable gain amplifier. The amplifier is located following the individual channel multiplexer. The ADS131E08S analog inputs are fully differential. The differential input voltage (VINxP – VINxN) can span from –VREF / gain to VREF / gain. See the Data Format section for an explanation of the correlation between the analog input and digital codes. There are two general methods of driving the ADS131E08S analog inputs: pseudodifferential or fully-differential, as shown in Figure 19, Figure 20, and Figure 21. VREF / Gain to VREF / Gain VREF / Gain Peak-to-Peak Device Device Common Voltage Common Voltage a) Psuedo-Differential Input VREF / Gain Peak-to-Peak b) Differential Input Figure 19. Methods of Driving the ADS131E08S: Pseudo-Differential or Fully Differential INxP INxN INxP VCM VCM INxN Figure 20. Pseudo-Differential Input Mode Figure 21. Fully-Differential Input Mode Hold the INxN pin at a common voltage, preferably at mid supply, to configure the fully differential input for a pseudo-differential signal. Swing the INxP pin around the common voltage –VREF / gain to VREF / gain and remain within the absolute maximum specifications. Verify that the differential signal at the minimum and maximum points meets the common-mode input specification discussed in the Input Common-Mode Range section. Configure the signals at INxP and INxN to be 180° out-of-phase centered around a common voltage to use a fully-differential input method. Both the INxP and INxN inputs swing from the common voltage + ½ VREF / gain to the common voltage – ½ VREF / gain. The differential voltage at the maximum and minimum points is equal to –VREF / gain to VREF / gain. Use the ADS131E08S in a differential configuration to maximize the dynamic range of the data converter. For optimal performance, the common voltage is recommended to be set at the midpoint of the analog supplies [(AVDD + AVSS) / 2]. If any of the analog input channels are not used, then power-down these pins using register bits to conserve power. See the SPI Command Definitions section for more information on how to power-down individual channels. Tie any unused or powered down analog input pins directly to AVDD. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 19 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.3.4 PGA Settings and Input Range Each channel has its own configurable programmable gain amplifier (PGA) following its multiplexer. The PGA is designed using two operational amplifiers in a differential configuration, as shown in Figure 22. Set the gain to one of five settings (1, 2, 4, 8, and 12) using the CHnSET registers for each individual channel (see the CHnSET registers in the Register Map section for details). The ADS131E08S has CMOS inputs and therefore has negligible current noise. Table 3 shows the typical small-signal bandwidth values for various gain settings. From Mux Amp R2 30 k R1 60 k (for Gain = 2) To ADC R2 30 k Amp From Mux Figure 22. PGA Implementation Table 3. PGA Gain versus Bandwidth GAIN NOMINAL BANDWIDTH AT TA = 25°C (kHz) 1 237 2 146 4 96 8 48 12 32 The PGA resistor string that implements the gain has 120 kΩ of resistance for a gain of 2. This resistance provides a current path across the PGA outputs in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input. 20 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.3.4.1 Input Common-Mode Range The usable input common-mode range of the analog front-end depends on various parameters, including the maximum differential input signal, supply voltage, and PGA gain. The common-mode range, VCM, is defined in Equation 4: AVDD - 0.3 V - Gain ´ VMAX_DIFF 2 > VCM > AVSS + 0.3 V + Gain ´ VMAX_DIFF 2 where: • • VMAX_DIFF = maximum differential signal at the PGA input and VCM = common-mode voltage (4) For example: If AVDD – AVSS = 3.3 V, gain = 2, and VMAX_DIFF = 1000 mV, Then 1.3 V < VCM < 2.0 V 9.3.5 ΔΣ Modulator Power Spectral Density (dB) Each ADS131E08S channel has its own delta-sigma (ΔΣ) ADC. The ΔΣ converters use second-order modulators optimized for low-power applications. The modulator samples the input signal at the modulator rate of (fMOD = fCLK / 2). As with any ΔΣ modulator, the ADS131E08S noise is shaped until fMOD / 2, as shown in Figure 23. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 0.001 0.01 0.1 Normalized Frequency (fIN/fMOD) 1 G001 Figure 23. Modulator Noise Spectrum Up to 0.5 × fMOD 9.3.6 Clock The ADS131E08S provides two different device clocking methods: internal and external. Internal clocking using the internal oscillator is ideally-suited for non-synchronized, low-power systems. The internal oscillator is trimmed for accuracy at room temperature. The accuracy of the internal oscillator varies over the specified temperature range; see the Electrical Characteristics table for details. External clocking is recommended when synchronizing multiple ADS131E08S devices or when synchronizing to an external event because the internal oscillator clock performance can vary over temperature. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit. Provide the external clock any time after the analog and digital supplies are present. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 21 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com The CLKSEL pin selects either the internal oscillator or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output on the CLK pin. A truth table for the CLKSEL pin and the CLK_EN bit is shown in Table 4. The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. During power-down, the external clock is recommended to be shut down to save power. Table 4. CLKSEL Pin and CLK_EN Bit CLKSEL PIN CLK_EN BIT CLOCK SOURCE CLK PIN STATUS 0 X External clock Input: external clock 1 0 Internal oscillator 3-state 1 1 Internal oscillator Output: internal oscillator 9.3.7 Digital Decimation Filter The digital filter receives the modulator output bit stream and decimates the data stream. The decimation ratio determines the number of samples taken to create the output data word, and is set by the modulator rate divided by the data rate (fMOD / fDR). By adjusting the decimation ratio, a tradeoff can be made between resolution and data rate: higher decimation allows for higher resolution (thus creating lower data rates) and lower decimation decreases resolution but enables wider bandwidths with higher data rates. Higher data rates are typically used in power applications that implement software re-sampling techniques to help with channel-to-channel phase adjustment for voltage and current. The digital filter on each channel consists of a third-order sinc filter. An input step change takes three conversion cycles for the filter to settle. Adjust the decimation ratio of the sinc3 filters using the DR[2:0] bits in the CONFIG1 register (see the Register Map section for details). The data rate setting is a global setting that sets all channels to the same data rate. The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. The sinc3 filter attenuates the high-frequency modulator noise, then decimates the data stream into parallel data. The decimation rate affects the overall converter data rate. Equation 5 shows the scaled sinc3 filter Z-domain transfer function. ½H(z)½ = 1 - Z-N 3 1 - Z-1 (5) The sinc3 filter frequency domain transfer function is shown in Equation 6. 3 sin H(f) = Npf fMOD N ´ sin pf fMOD where: • N = decimation ratio (6) 3 The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 24 illustrates the sinc filter frequency response and Figure 25 illustrates the sinc filter roll-off. Figure 26 and Figure 27 illustrate the filter transfer function until fMOD / 2 and fMOD / 16, respectively, at different data rates. Figure 28 illustrates the transfer function extended until 4 fMOD. Figure 28 illustrates that the ADS131E08S passband repeats itself at every fMOD. Note that the digital filter response and filter notches are proportional to the master clock frequency. 22 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) www.ti.com -60 -80 -1.5 -2 -100 -2.5 -120 -3 -140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 0.05 0.1 Figure 24. Sinc Filter Frequency Response 0 DR[2:0] = 110 0.25 0.3 0.35 DR[2:0] = 110 -20 DR[2:0] = 000 -40 DR[2:0] = 000 -40 Gain (dB) Gain (dB) 0.2 Figure 25. Sinc Filter Roll-Off 0 -20 0.15 Normalized Frequency (fIN/fDR) Normalized Frequency (fIN/fDR) -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.01 Normalized Frequency (fIN/fMOD) 0.03 0.04 0.05 0.06 0.07 Normalized Frequency (fIN/fMOD) Figure 26. Transfer Function of Decimation Filters Until fMOD / 2 10 0.02 DR[2:0] = 000 Figure 27. Transfer Function of Decimation Filters Until fMOD / 16 DR[2:0] = 110 -10 Gain (dB) -30 -50 -70 -90 -110 -130 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Frequency (fIN/fMOD) Figure 28. Transfer Function of Decimation Filters Until 4 fMOD for DR[2:0] = 000 and DR[2:0] = 110 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 23 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.3.8 Voltage Reference The ADS131E08S uses an internal voltage reference and does not provide the option of connecting an external reference voltage. Figure 29 shows a simplified block diagram of the internal reference. There are two internal reference voltage options generated with respect to AVSS: 2.4 V and 4 V. Connect VREFN to AVSS. 470 pF VCAP1 R1 (1) Bandgap 2.4 V or 4 V R3 VREFP (1) 330 nF R2 (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.4 V: R1 = 12.5 kΩ, R2 = 25 kΩ, and R3 = 25 kΩ. For VREF = 4 V: R1 = 10.5 kΩ, R2 = 15 kΩ, and R3 = 35 kΩ. Figure 29. Internal Reference Implementation The external band-limiting capacitors, connected to VCAP1 and between the VREFP and VREFN nodes, determine the amount of reference noise contribution. Although limiting the bandwidth through larger capacitor sizes helps keep noise at a minimum, using large capacitors increases the power-up time of the ADC. Using the capacitor values shown in Figure 29 is recommended to optimize the power-up time of the device. ADC Output (Code) The internal band gap (VCAP1 pin) used to create the internal reference voltage requires a capacitor to filter noise. As a result of limited drive strength, the size of the capacitor on VCAP1 sets the power-up time of the device. Figure 30 shows the accuracy of the first 200 conversion samples with different capacitors on VCAP1 following power-up. Larger capacitors on VCAP1 help filter broadband noise but add to the power-up time. To generate the plot of Figure 30, the ADC input voltage is fixed at 1 V during power-up and the ADC output conversion result is tracked to show the VCAP1 power-up time. 2122000 2121600 2121200 2120800 2120400 2120000 2119600 2119200 2118800 2118400 2118000 2117600 2117200 2116800 2116400 2116000 VCAP1 Value 330 nF 150 nF 2.2 uF 470 pF 0 20 40 60 80 100 120 ADC Sample 140 160 180 200 D016 Figure 30. VCAP1 Power-Up Time versus External Capacitor Value Use the VREF_4V bit in the CONFIG2 register to set the internal reference to either 4 V or 2.4 V. By default, the reference powers up as 4 V for a 5-V system (or ±2.5-V supplies). In a 3-V system (or ±1.5-V supplies), configure the internal reference to 2.4 V immediately following power-up. No damage occurs to the device when the ADS131E08S is set to a 4-V reference when using a 3-V supply system. The internal reference saturates until programmed to 2.4 V. 24 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.3.9 Input Out-of-Range Detection The ADS131E08S has integrated comparators to detect out-of-range conditions on the input signals. The basic principle is to compare the input voltage against a threshold voltage set by a 3-bit digital-to-analog converter (DAC) based off the analog power supply. The comparator trigger threshold level is set by the COMP_TH[2:0] bits in the FAULT register. If the ADS131E08S is powered from a ±2.5-V supply and COMP_TH[2:0] = 000 (95% and 5%), the high-side trigger threshold is set at 2.25 V [equal to AVSS + (AVDD – AVSS) × 95%] and the low-side threshold is set at –2.25 V [equal to AVSS + (AVDD – AVSS) × 5%]. The threshold calculation formula applies to unipolar as well as to bipolar supplies. A fault condition can be detected by setting the appropriate threshold level using the COMP_TH[2:0] bits. To determine which of the inputs is out of range, read the FAULT_STATP and FAULT_STATN registers individually or read the FAULT_STATx bits as part of the output data stream; see the Data Output (DOUT) section. 9.3.10 General-Purpose Digital I/O (GPIO) The ADS131E08S has a total of four general-purpose digital I/O (GPIO) pins available. Configure the digital I/O pins as either inputs or outputs through the GPIOC bits. The GPIOD bits in the GPIO register indicate the level of the pins. The GPIO logic high voltage level is set by the voltage level of DVDD. When reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output level. If configured as inputs, the GPIO pins must be driven to a defined state. The GPIO pins are set as inputs after power-up or after a reset. Figure 31 shows the GPIO pin structure. Connect unused GPIO pins directly to DGND through 10-kΩ resistors. GPIO Data (Read) GPIO Pin GPIO Data (Write) GPIO Control Figure 31. GPIO Pin Implementation Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 25 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.4 Device Functional Modes 9.4.1 Power-Down Power-down all on-chip circuitry by pulling the PWDN pin low. To exit power-down mode, take the PWDN pin high. The internal oscillator and reference require time to come out of power-down mode. During power-down, the external clock is recommended to be shut down to save power. 9.4.2 Reset There are two methods to reset the ADS131E08S: pull the RESET pin low, or send the RESET command. When using the RESET pin, driving the pin low forces the device into reset. Follow the minimum pulse duration timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge. After the device is reset, 18 tCLK cycles are required to complete initialization of the configuration registers to the default states and start the conversion cycle. 9.4.3 Conversion Mode Set the START pin high (for a minimum of 2 tCLK) or send the START command to begin conversions. When the START pin is held low, or if the START command is not sent, conversions are halted and the new data-ready indicator (the DRDY signal) does not issue. When using the START command to control conversions, hold the START pin low. In multiple device configurations, the START pin is used to synchronize devices (see the Multiple Device Configuration section for more details). 9.4.3.1 START Pin Low-to-High Transition or START Command Sent When the START pin is pulled high or when the START command is sent, the device ADCs begin converting the input signals and the data ready indicator, DRDY, is pulled high. The next DRDY falling edge indicates that data are ready. The settling time (tSETTLE) is the time required for the converter to output fully-settled data when the START signal is pulled high or the START command is issued. Figure 32 shows the timing diagram and Table 5 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Table 5 lists the settling time as a function of tCLK. START § § § § DIN START DRDY tSETTLE Figure 32. Settling Time for the Initial Conversion Table 5. Settling Time for Different Data Rates 26 DR[2:0] SETTLING TIME UNIT 000 152 tCLK 001 296 tCLK 010 584 tCLK 011 1160 tCLK 100 2312 tCLK 101 4616 tCLK 110 9224 tCLK Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.4.3.2 Input Signal Step When the device is converting and there is a step change on the input signal, a delay of 3 tDR is required for the output data to settle. Settled data are available on the fourth DRDY pulse. Data are available to read at each DRDY low transition prior to the 4th DRDY pulse, but are recommended to be ignored. Figure 33 shows the required wait time for complete settling for an input step or input transient event on the analog input. START Analog Input Input Transient DRDY 4 x tDR Figure 33. Settling Time for the Input Transient 9.4.3.3 Continuous Conversion Mode When the START pin is pulled high or the START command is issued, conversions continue indefinitely until the START pin is taken low or the STOP command is transmitted, as shown in Figure 34. When the START pin is pulled low or the STOP command is issued, the conversion in progress completes and the DRDY output transitions from high to low indicating that the latest data are available. Figure 35 and Table 6 illustrate the timing of where the START pin can be brought low or the STOP command can be sent relative to a completed conversion to halt further conversions. If the START pin is pulled low or if the STOP command is sent after the tDSHD time, then an additional conversion takes place and completes before further conversions are halted. To continuously run the converter without commands, tie the START pin high. START Pin or or (1) DIN (1) START Command STOP Command tDR tSETTLE DRDY (1) START and STOP commands take effect on the seventh SCLK falling edge. Figure 34. Continuous Conversion Mode tSDSU DRDY and DOUT tDSHD START Pin or STOP Opcode (1) STOP(1) STOP(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the transmission. Figure 35. START to DRDY Timing Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 27 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Table 6. Timing Characteristics for Figure 35 (1) MIN UNIT tSDSU Setup time; set the START pin low or send the STOP command before the DRDY falling edge to halt further conversions 16 tCLK tDSHD Delay time; set the START pin low or send the STOP command to complete the current conversion and halt further conversions 16 tCLK (1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the transmission. 9.5 Programming 9.5.1 SPI Interface The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface is used to read conversion data, read and write registers, and control the ADS131E08S operation. The DRDY output is used as a status signal to indicate when ADC data are ready for readback. DRDY goes low when new data are available. 9.5.1.1 Chip Select (CS) Chip select (CS) selects the ADS131E08S for SPI communication. CS must remain low for the duration of the serial communication. After the serial communication is finished, wait four or more tCLK cycles before taking CS high; see the Timing Requirements section. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored (SCLK clears DRDY even when CS is high; see Figure 38 for more details), and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low. 9.5.1.2 Serial Clock (SCLK) Use SCLK as the SPI serial clock to shift in commands and shift out data from the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT pins into and out of the ADS131E08S. Care must be taken to prevent glitches on SCLK when CS is low. Glitches as small as 1 ns in duration can be interpreted as a valid serial clock. An instruction on DIN is decoded every eight serial clocks. If instructions are suspected of being interrupted erroneously, toggle CS high and back low to reset the SPI interface, placing the device in normal operation. For a single device, the minimum speed needed for SCLK depends on the number of channels, number of bits of resolution, and output data rate. (For multiple cascaded devices, see the Standard Configuration section.) The SCLK rate limitation, as described by Equation 7, applies to RDATAC mode. tSCLK < (tDR – 4 tCLK) / (NBITS × 8 + 24) where • NBITS = resolution of data for the current data rate; 16 or 24 (7) For example, if the ADS131E08S is used with an 8-kSPS mode (24-bit resolution), the minimum SCLK speed is 1.755 MHz to shift out all the data. Data retrieval can be done either by putting the device in read data continuous mode (RDATAC mode) or reading on demand using the read data command (RDATA). The SCLK rate limitation, as described by Equation 7, applies to RDATAC mode. When using the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. This calculation assumes that there are no other commands issued in between data captures. There are two methods for transmitting SCLKs to the ADS131E08S to meet the decode timing specification (tSDECODE) illustrated in Figure 1 for multiple byte commands: 1. SCLK can be transmitted in 8-bit bursts with a gap between bursts to maintain the tSDECODE timing specification. The maximum SCLK frequency is specified in Figure 1. 2. A continuous SCLK stream can be sent when CS is low. Verify that the SCLK speed meets the tSDECODE timing requirement. This method is not to be confused with a free-running SCLK where SCLK also operates when CS is high. A free-running SCLK operation is not supported by this device. 28 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Programming (continued) 9.5.1.3 Data Input (DIN) Use the data input pin (DIN) along with SCLK to send commands and register data to the ADS131E08S. The device latches data on DIN on the SCLK falling edge. 9.5.1.4 Data Output (DOUT) Use the data output pin (DOUT) with SCLK to read conversions and register data from the ADS131E08S. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line can also be used to indicate when new data are available. If CS is low when new data are ready, a high-to-low transition on the DOUT line occurs synchronously with a high-to-low transition on DRDY, as shown in Figure 36. This feature can be used to minimize the number of connections between the device and system controller. CS DOUT Data DRDY Figure 36. Using DOUT as DRDY 9.5.1.5 Data Ready (DRDY) DRDY is an output signal that transitions from high to low to indicate that new conversion data are ready. DRDY behavior is determined by whether the device is in RDATAC mode or if the RDATA command is being used to read data on demand. See the RDATAC: Start Read Data Continuous Mode and RDATA: Read Data sections for further details. The CS signal has no effect on the data-ready signal. When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption. Figure 37 shows the relationship between DRDY, DOUT, and SCLK during data retrieval. DOUT transitions on the SCLK rising edge. DRDY goes high on the first SCLK falling edge regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. Data starts with the MSB of the status word and then proceeds to the ADC channel data in sequential order (channel 1, channel 2, and so forth). Data for powered down channels appear in the data stream as 0s and are to be ignored. CS DRDY SCLK DOUT MSB MSB-1 MSB-2 Figure 37. DRDY Behavior with Data Retrieval Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 29 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Programming (continued) The DRDY signal is cleared on the first SCLK falling edge regardless of the state of CS. This condition must be taken into consideration if the SPI bus is used to communicate with other devices on the same bus. Figure 38 shows a behavior diagram for DRDY when SCLKs are sent with CS high. Figure 38 shows that no data are clocked out, but the DRDY signal is cleared. CS DRDY SCLK Figure 38. DRDY and SCLK Behavior when CS is High 9.5.2 Data Retrieval Data retrieval can be accomplished in one of two methods. The read data continuous command (see the RDATAC: Start Read Data Continuous Mode section) can be used to set the device in a mode to read the data continuously without having to send a command. The read data command (see the RDATA: Read Data section) can be used to read only one data output from the device (see the SPI Command Definitions section for more details). Conversion data are read out serially on DOUT. The MSB of the status word is clocked out on the first SCLK rising edge, followed by the ADC channel data. DRDY returns to high on the first SCLK falling edge. DIN remains low for the entire read operation. 9.5.2.1 Status Word A status word precedes data readback and provides information on the state of the ADS131E08S. The status word is 24 bits long and contains the values for FAULT_STATP, FAULT_STATN, and the GPIO data bits. The content alignment is shown in Figure 39. FAULT_STATP[7:0] GPIO[7:4] FAULT_STATN[7:0] § § 0 § 0 § § 1 § 1 § § DOUT § SCLK Figure 39. Status Word Content NOTE The status word length is always 24 bits. The length does not change for 32-kSPS and 64-kSPS data rates. 9.5.2.2 Readback Length The number of bits in the data output depends on the number of channels and the number of bits per channel. The data format for each channel data are twos complement and MSB first. For the ADS131E08S with 32-kSPS and 64-kSPS data rates, the number of data bits is: 24 status bits + 16 bits per channel × 8 channels = 152 bits. For all other data rates, the number of data bits is: 24 status bits + 24 bits per channel × 8 channels = 216 bits. When channels are powered down using the user register setting, the corresponding channel output is set to 0. However, the sequence of channel outputs remains the same. 30 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Programming (continued) The ADS131E08S also provides a multiple data readback feature. Data can be read out multiple times by simply providing more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_IN bit in the CONFIG1 register must be set to 1 for multiple read backs. 9.5.2.3 Data Format The DR[2:0] bits in the CONFIG1 register sets the output resolution for the ADS131E08S. When DR[2:0] = 000 or 001, the 16 bits of data per channel are sent in binary twos complement format, MSB first. The size of one code (LSB) is calculated using Equation 8. 1 LSB = (2 × VREF / Gain) / 216 = FS / 215 (8) A positive full-scale input [VIN ≥ (FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 7 summarizes the ideal output codes for different input signals. Table 7. 16-Bit Ideal Output Code versus Input Signal INPUT SIGNAL, VIN V(INxP) - V(INxN) IDEAL OUTPUT CODE (1) ≥ FS (215 – 1) / 215 7FFFh FS / 215 0001h 0 0000h 15 (1) –FS / 2 FFFFh ≤ –FS 8000h Excludes the effects of noise, INL, offset, and gain errors. When DR[2:0] = 010, 011, 100, 101, or 110, the ADS131E08S outputs 24 bits of data per channel in binary twos complement format, MSB first. The size of one code (LSB) is calculated using Equation 9. 1 LSB = (2 × VREF / Gain) / 224 = FS / 223 (9) A positive full-scale input [VIN ≥ (FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFh and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 8 summarizes the ideal output codes for different input signals. Table 8. 24-Bit Ideal Output Code versus Input Signal INPUT SIGNAL, VIN V(INxP) - V(INxN) 23 ≥ FS (2 23 – 1) / 2 23 FS / 2 (1) IDEAL OUTPUT CODE (1) 7FFFFFh 000001h 0 000000h –FS / 223 FFFFFFh ≤ –FS 800000h Excludes the effects of noise, INL, offset, and gain errors. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 31 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.5.3 SPI Command Definitions The ADS131E08S provides flexible configuration control. The commands, summarized in Table 9, control and configure device operation. The commands are stand-alone, except for the register read and register write operations that require a second command byte to include additional data. CS can be taken high or held low between commands but must stay low for the entire command operation (including multibyte commands). System commands and the RDATA command are decoded by the ADS131E08S on the seventh SCLK falling edge. The register read and write commands are decoded on the eighth SCLK falling edge. Make sure to follow the SPI timing requirements when pulling CS high after issuing a command. Table 9. Command Definitions COMMAND DESCRIPTION FIRST BYTE SECOND BYTE SYSTEM COMMANDS WAKEUP Wake-up from standby mode 0000 0010 (02h) STANDBY Enter standby mode 0000 0100 (04h) RESET Reset the device 0000 0110 (06h) START Start or restart (synchronize) conversions 0000 1000 (08h) STOP Stop conversions 0000 1010 (0Ah) OFFSETCAL Channel offset calibration 0001 1010 (1Ah) DATA READ COMMANDS RDATAC Enable read data continuous mode. This mode is the default mode at power-up. (1) 0001 0000 (10h) SDATAC Stop read data continuous mode 0001 0001 (11h) RDATA Read data by command 0001 0010 (12h) REGISTER READ COMMANDS RREG Read n nnnn registers starting at address r rrrr 001r rrrr (2xh) (2) 000n nnnn (2) WREG Write n nnnn registers starting at address r rrrr 010r rrrr (4xh) (2) 000n nnnn (2) (1) (2) When in RDATAC mode, the RREG command is ignored. n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr = the starting register address for read and write commands. 9.5.3.1 WAKEUP: Exit STANDBY Mode The WAKEUP command exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode section. Be sure to allow enough time for all circuits in STANDBY mode to power-up (see the Electrical Characteristics table for details). There are no SCLK rate restrictions for this command and it can be issued at any time. Following the WAKEUP command, wait 4 tCLK cycles before sending another command. 9.5.3.2 STANDBY: Enter STANDBY Mode The STANDBY command enters low-power standby mode. All circuits in the device are powered down except for the reference section. The standby mode power consumption is specified in the Electrical Characteristics table. There are no SCLK rate restrictions for this command and it can be issued at any time. Do not send any other command other than the WAKEUP command after the device enters standby mode. 9.5.3.3 RESET: Reset Registers to Default Values The RESET command resets the digital filter and returns all register settings to their default values; see the Reset section for more details. There are no SCLK rate restrictions for this command and it can be issued at any time. 18 tCLK cycles are required to execute the RESET command. Do not send any commands during this time. 9.5.3.4 START: Start Conversions The START command starts data conversions. Tie the START pin low to control conversions by the START and STOP commands. If conversions are in progress, this command has no effect. The STOP command is used to stop conversions. If the START command is immediately followed by a STOP command, then there must be a gap of 4 tCLK cycles between the commands. The current conversion completes before further conversions are halted. There are no SCLK rate restrictions for this command and it can be issued at any time. 32 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.5.3.5 STOP: Stop Conversions The STOP command stops conversions. Tie the START pin low to control conversions by the START and STOP commands. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. 9.5.3.6 OFFSETCAL: Channel Offset Calibration The OFFSETCAL command is used to cancel the offset of each channel. The OFFSETCAL command is recommended to be issued every time there is a change in PGA gain settings. When the OFFSETCAL command is issued, the device configures itself to the lowest data rate (DR = 110, 1 kSPS) and performs the following steps for each channel: • Short the analog inputs of each channel together and connect them to mid-supply [(AVDD + AVSS) / 2) • Reset the digital filter (requires a filter settling time = 4 tDR) • Collect 16 data points for calibration = 15 tDR Total calibration time = (19 tDR × 8) + 1 ms = 153 ms. 9.5.3.7 RDATAC: Start Read Data Continuous Mode The RDATAC command enables read data continuous mode. In this mode, conversion data are retrieved from the device without the need to issue subsequent RDATA commands. This mode places the conversion data in the output register with every DRDY falling edge so that the data can be shifted out directly. Shift out all data from the device before data are updated with a new DRDY falling edge to avoid losing data. The read data continuous mode is the default mode of the device. Figure 40 shows the ADS131E08S data output protocol when using RDATAC mode. DRDY CS SCLK N SCLKS DOUT STAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 24-Bit N-Bit N-Bit N-Bit N-Bit N-Bit N-Bit N-Bit N-Bit DIN NOTE: X SCLKs = (N bits)(8 channels) + 24 bits. N-bit is dependent upon the DR[2:0] registry bit settings (N = 16 or 24). Figure 40. ADS131E08S SPI Bus Data Output (Eight Channels) Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 33 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com RDATAC mode is stopped by the stop read data continuous (SDATAC) command. If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device. There are no SCLK rate restrictions for this command. However, subsequent data retrieval SCLKs or the SDATAC command must wait at least 4 tCLK cycles for the command to execute. RDATAC timing is shown in Figure 41. There is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. If no data are retrieved from the device and CS is held low, a high-to-low DOUT transition occurs synchronously with DRDY. To retrieve data from the device after the RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 41 shows the recommended way to use the RDATAC command. Read data continuous mode is ideally-suited for applications such as data loggers or recorders where registers are set one time and do not need to be reconfigured. START DRDY tUPDATE(1) CS SCLK RDATAC DIN Hi-Z DOUT (1) Status Register + n-Channel Data Next Data tUPDATE = 4 / fCLK. Do not read data during this time. Figure 41. Reading Data in RDATAC Mode 9.5.3.8 SDATAC: Stop Read Data Continuous Mode The SDATAC command stops the read data continuous mode. There are no SCLK rate restrictions for this command, but wait at least 4 tCLK cycles before issuing any further commands. Use the read data (RDATA) command to read data when in SDATAC mode. 9.5.3.9 RDATA: Read Data Use the RDATA command to read conversion data when not in read data continuous mode. Issue this command after DRDY goes low to read the conversion result (in stop read data continuous mode). There are no SCLK rate restrictions for this command, and there is no wait time needed for subsequent commands or data retrieval SCLKs. To use the RDATA command, the device must be actively converting (the START pin must be held high or the START command must be issued). When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption. RDATA can be sent multiple times after new data are available, thus supporting multiple data readback. Figure 42 illustrates the recommended way to use the RDATA command. RDATA is best suited for systems where register settings must be read or the user does not have precise control over timing. Reading data using the RDATA command is recommended to avoid data corruption when the DRDY signal is not monitored. 34 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 START DRDY CS SCLK RDATA DIN DOUT RDATA Hi-Z Status Register + N-Channel Data (216 Bits) Figure 42. RDATA Usage 9.5.3.10 RREG: Read from Register The RREG command reads the contents of one or more device configuration registers. When the device is in read data continuous mode, an SDATAC command must be issued before the RREG command can be issued. The RREG command can be issued at any time. The RREG command is a two-byte command on DIN followed by the register data output on DOUT. The command is constructed as follows: First byte: 001r rrrr, where r rrrr is the starting register address. Second byte: 000n nnnn, where n nnnn is the number of registers to read – 1. The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 43. However, because this command is a multibyte command, there are SCLK rate restrictions depending on how the SCLKs are issued; see Figure 1. CS must be low for the entire command. CS 1 9 17 25 SCLK DIN BYTE 1 DOUT BYTE 2 REG DATA REG DATA + 1 Figure 43. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register) (BYTE 1 = 0010 0000, BYTE 2 = 0000 0001) Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 35 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.5.3.11 WREG: Write to Register The WREG command writes data to one or more device configuration registers. The WREG command is a twobyte command followed by the register data input. The command is constructed as follows: First byte: 010r rrrr, where r rrrr is the starting register address. Second byte: 000n nnnn, where n nnnn is the number of registers to write – 1. After the two command bytes, the register data follows (in MSB-first format), as shown in Figure 44. For multiple register writes across reserved registers (0Dh–11h), these registers must be included in the register count and the default setting of the reserved register must be written. The WREG command can be issued at any time. However, because this command is a multibyte command, there are SCLK rate restrictions depending on how the SCLKs are issued; see Figure 1. CS must be low for the entire command. CS 1 9 17 25 SCLK DIN BYTE 1 BYTE 2 REG DATA 1 REG DATA 2 DOUT Figure 44. WREG Command Example: Write Two Registers Starting from 00h (ID Register) (BYTE 1 = 0100 0000, BYTE 2 = 0000 0001) 9.5.3.12 Sending Multibyte Commands The ADS131E08S serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute each command. This timing requirement can place restrictions on the SCLK speed and operational modes. For example: Assuming CLK is 2.048 MHz, then tSDECODE (4 tCLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be transferred in 0.5 µs. This byte transfer time does not meet the tSDECODE specification; therefore, a delay of 1.46 µs (1.96 µs – 0.5 µs) must be inserted after the first byte and before the second byte. If SCLK is 4 MHz, one byte is transferred in 2 µs. Because this transfer time exceeds the tSDECODE specification (2 µs > 1.96 µs), the processor can send subsequent bytes without delay. 36 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.6 Register Map Table 10 describes the various ADS131E08S registers. Table 10. Register Map (1) ADDRESS REGISTER RESET VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 1 REV_ID 1 0 0 1 0 DEVICE SETTINGS (Read-Only Registers) 00h ID D2h GLOBAL SETTINGS ACROSS CHANNELS 01h CONFIG1 94h 1 DAISY_IN CLK_EN 1 0 02h CONFIG2 E0h 1 1 1 INT_TEST 0 TEST_AMP0 TEST_FREQ[1:0] 03h CONFIG3 E0h 1 1 VREF_4V 0 OPAMP_REF PDB_OPAMP 0 0 04h FAULT 00h 0 0 0 0 0 COMP_TH[2:0] DR[2:0] CHANNEL-SPECIFIC SETTINGS 05h CH1SET 10h PD1 GAIN1[2:0] 0 MUX1[2:0] 06h CH2SET 10h PD2 GAIN2[2:0] 0 MUX2[2:0] 07h CH3SET 10h PD3 GAIN3[2:0] 0 MUX3[2:0] 08h CH4SET 10h PD4 GAIN4[2:0] 0 MUX4[2:0] 09h CH5SET 10h PD5 GAIN5[2:0] 0 MUX5[2:0] 0Ah CH6SET 10h PD6 GAIN6[2:0] 0 MUX6[2:0] 0Bh CH7SET 10h PD7 GAIN7[2:0] 0 MUX7[2:0] 0Ch CH8SET 10h PD8 GAIN8[2:0] 0 MUX8[2:0] FAULT DETECT STATUS REGISTERS (Read-Only Registers) 12h FAULT_STATP 00h IN8P_FAULT IN7P_FAULT IN6P_FAULT IN5P_FAULT IN4P_FAULT IN3P_FAULT IN2P_FAULT IN1P_FAULT 13h FAULT_STATN 00h IN8N_FAULT IN7N_FAULT IN6N_FAULT IN5N_FAULT IN4N_FAULT IN3N_FAULT IN2N_FAULT IN1N_FAULT 0Fh GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 GPIO SETTINGS 14h (1) GPIO When using multiple register write commands, registers 0Dh, 0Eh, 0Fh, 10h, and 11h must be written to 00h. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 37 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.6.1 Register Descriptions 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = D2h] This register is programmed during device manufacture to indicate device characteristics. Figure 45. ID: ID Control Register 7 1 R-1h 6 1 R-1h 5 REV_ID R-1h 4 1 R-1h 3 0 R-0h 2 0 R-0h 1 1 R-1h 0 0 R-0h LEGEND: R = Read only; -n = value after reset Table 11. ID: ID Control Register Field Descriptions 38 Bit Field Type Reset Description 7-6 Reserved R 3h Reserved. Always reads 1. 5 REV_ID R 0h Device family identification. This bit indicates the device family. 0 = ADS131E08S 1 = Reserved 4 Reserved R 1h Reserved. Always reads 1. 3-2 Reserved R 0h Reserved. Always reads 0. 1 Reserved R 1h Reserved. Always reads 1. 0 Reserved R 0h Reserved. Always reads 0. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 94h] This register configures each ADC channel sample rate. Figure 46. CONFIG1: Configuration Register 1 7 1 R/W-1h 6 DAISY_IN R/W-0h 5 CLK_EN R/W-0h 4 1 R/W-1h 3 0 R/W-0h 2 1 DR[2:0] R/W-4h 0 LEGEND: R/W = Read/Write; -n = value after reset Table 12. CONFIG1: Configuration Register 1 Field Descriptions Bit Field Type Reset Description 7 Reserved R/W 1h Reserved. Must be set to 1. This bit reads high. 6 DAISY_IN R/W 0h Daisy-chain and multiple data readback mode. This bit determines which mode is enabled. 0 = Daisy-chain mode 1 = Multiple data readback mode 5 CLK_EN R/W 0h CLK connection (1). This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1. 0 = Oscillator clock output disabled 1 = Oscillator clock output enabled 4 Reserved R/W 1h Reserved. Must be set to 1. This bit reads high. 3 Reserved R/W 0h Reserved. Must be set to 0. This bit reads low. DR[2:0] R/W 4h Output data rate. These bits determine the output data rate and resolution; see Table 13 for details. 2-0 (1) Additional power is consumed when driving external devices. Table 13. Data Rate Settings (1) DR[2:0] RESOLUTION DATA RATE (kSPS) (1) 000 16-bit output 64 001 16-bit output 32 010 24-bit output 16 011 24-bit output 8 100 24-bit output 4 101 24-bit output 2 110 24-bit output 1 111 Do not use NA Where fCLK = 2.048 MHz. Data rates scale with master clock frequency. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 39 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = 00h] This register configures the test signal generation; see the Input Multiplexer section for more details. Figure 47. CONFIG2: Configuration Register 2 7 1 R/W-1h 6 1 R/W-1h 5 1 R/W-1h 4 INT_TEST R/W-0h 3 0 R/W-0h 2 TEST_AMP R/W-0h 1 0 TEST_FREQ[1:0] R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 14. CONFIG2: Configuration Register 2 Field Descriptions Bit Field Type Reset Description 7-5 Reserved R/W 1h Reserved. Must be set to 1. This bit reads high. 4 INT_TEST R/W 0h Test signal source. This bit determines the source for the test signal. 0 = Test signals are driven externally 1 = Test signals are generated internally 3 Reserved R/W 0h Reserved. Must be set to 0. This bit reads low. 2 TEST_AMP R/W 0h Test signal amplitude. These bits determine the calibration signal amplitude. 0 = 1 × –(V(VREFP) – V(VREFN)) / 2400 1 = 2 × –(V(VREFP) – V(VREFN)) / 2400 TEST_FREQ[1:0] R/W 0h Test signal frequency. These bits determine the test signal frequency. 00 = Pulsed at fCLK / 221 01 = Pulsed at fCLK / 220 10 = Not used 11 = At dc 1-0 40 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = E0h] This register configures the reference and internal amplifier operation. Figure 48. CONFIG3: Configuration Register 3 7 1 R/W-1h 6 1 R/W-1h 5 VREF_4V R/W-1h 4 0 R/W-0h 3 OPAMP_REF R/W-0h 2 PDB_OPAMP R/W-0h 1 0 R/W-0h 0 0 R-0h LEGEND: R/W = Read/Write; -n = value after reset Table 15. CONFIG3: Configuration Register 3 Field Descriptions Bit Field Type Reset Description 7-6 Reserved R/W 1h Reserved. Must be set to 1. This bit reads high. 5 VREF_4V R/W 1h Internal reference voltage. This bit determines the reference voltage, VREFP. 0 = VREFP is set to 2.4 V 1 = VREFP is set to 4 V 4 Reserved R/W 0h Reserved. Must be set to 0. This bit reads low. 3 OPAMP_REF R/W 0h Op amp reference. This bit determines whether the op amp noninverting input connects to the OPAMPP pin or to the internally-derived supply (AVDD + AVSS) / 2. 0 = Noninverting input connected to the OPAMPP pin 1 = Noninverting input connected to (AVDD + AVSS) / 2 2 PDB_OPAMP R/W 0h Op amp power-down. This bit powers down the op amp. 0 = Power-down op amp 1 = Enable op amp 1 Reserved R/W 0h Reserved. Must be set to 0. Reads back as 0. 0 Reserved R 0h Reserved. Reads back as either 1 or 0. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 41 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h] This register configures the fault detection operation. Figure 49. FAULT: Fault Detect Control Register 7 6 COMP_TH[2:0] R/W-0h 5 4 0 R/W-0h 3 0 R/W-0h 2 0 R/W-0h 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 16. FAULT: Fault Detect Control Register Field Descriptions 42 Bit Field Type Reset Description 7-5 COMP_TH[2:0] R/W 0h Fault detect comparator threshold. These bits determine the fault detect comparator threshold level setting. See the Input Out-of-Range Detection section for a detailed description. Comparator high-side threshold. 000 = 95% 001 = 92.5% 010 = 90% 011 = 87.5% 100 = 85% 101 = 80% 110 = 75% 111 = 70% Comparator low-side threshold. 000 = 5% 001 = 7.5% 010 = 10% 011 = 12.5% 100 = 15% 101 = 20% 110 = 25% 111 = 30% 4-0 Reserved R/W 00h Reserved. Must be set to 0. This bit reads low. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h] This register configures the power mode, PGA gain, and multiplexer settings for the channels; see the Input Multiplexer section for details. CHnSET are similar to CH1SET, corresponding to the respective channels (see Table 10). Figure 50. CHnSET (1): Individual Channel Settings 7 PDn R/W-0h 6 5 GAINn[2:0] R/W-1h 4 3 0 R/W-0h 2 1 MUXn[2:0] R/W-0h 0 LEGEND: R/W = Read/Write; -n = value after reset (1) n = 1 to 8. Table 17. CHnSET: Individual Channel Settings Field Descriptions Bit Field Type Reset Description 7 PDn R/W 0h Power-down (n = individual channel number). This bit determines the channel power mode for the corresponding channel. 0 = Normal operation 1 = Channel power-down GAINn[2:0] R/W 1h PGA gain (n = individual channel number). These bits determine the PGA gain setting. 000 = Do not use 001 = 1 010 = 2 011 = Do not use 100 = 4 101 = 8 110 = 12 111 = Do not use 3 Reserved R/W 0h Reserved. Must be set to 0. This bit reads low. 2-0 MUXn[2:0] R/W 0h Channel input (n = individual channel number). These bits determine the channel input selection. 000 = Normal input 001 = Input shorted to (AVDD + AVSS) / 2 (for offset or noise measurements) 010 = Do not use 011 = MVDD for supply measurement 100 = Temperature sensor 101 = Test signal 110 = Do not use 111 = Do not use 6-4 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 43 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h] This register stores the status of whether the positive input on each channel has a fault or not. Faults are determined by comparing the input pin to a threshold set by Table 16; see the Input Out-of-Range Detection section for details. Figure 51. FAULT_STATP: Fault Detect Positive Input Status 7 IN8P_FAULT R-0h 6 IN7P_FAULT R-0h 5 IN6P_FAULT R-0h 4 IN5P_FAULT R-0h 3 IN4P_FAULT R-0h 2 IN3P_FAULT R-0h 1 IN2P_FAULT R-0h 0 IN1P_FAULT R-0h LEGEND: R = Read only; -n = value after reset Table 18. FAULT_STATP: Fault Detect Positive Input Status Field Descriptions Bit 44 Field Type Reset Description 7 IN8P_FAULT R 0h IN8P threshold detect. 0 = Channel 8 positive input pin does not exceed threshold set 1 = Channel 8 positive input pin exceeds threshold set 6 IN7P_FAULT R 0h IN7P threshold detect. 0 = Channel 7 positive input pin does not exceed threshold set 1 = Channel 7 positive input pin exceeds threshold set 5 IN6P_FAULT R 0h IN6P threshold detect. 0 = Channel 6 positive input pin does not exceed threshold set 1 = Channel 6 positive input pin exceeds threshold set 4 IN5P_FAULT R 0h IN5P threshold detect. 0 = Channel 5 positive input pin does not exceed threshold set 1 = Channel 5 positive input pin exceeds threshold set 3 IN4P_FAULT R 0h IN4P threshold detect. 0 = Channel 4 positive input pin does not exceed threshold set 1 = Channel 4 positive input pin exceeds threshold set 2 IN3P_FAULT R 0h IN3P threshold detect. 0 = Channel 3 positive input pin does not exceed threshold set 1 = Channel 3 positive input pin exceeds threshold set 1 IN2P_FAULT R 0h IN2P threshold detect. 0 = Channel 2 positive input pin does not exceed threshold set 1 = Channel 2 positive input pin exceeds threshold set 0 IN1P_FAULT R 0h IN1P threshold detect. 0 = Channel 1 positive input pin does not exceed threshold set 1 = Channel 1 positive input pin exceeds threshold set Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h] This register stores the status of whether the negative input on each channel has a fault or not. Faults are determined by comparing the input pin to a threshold set by Table 16; see the Input Out-of-Range Detection section for details. Figure 52. FAULT_STATN: Fault Detect Negative Input Status 7 IN8N_FAULT R-0h 6 IN7N_FAULT R-0h 5 IN6N_FAULT R-0h 4 IN5N_FAULT R-0h 3 IN4N_FAULT R-0h 2 IN3N_FAULT R-0h 1 IN2N_FAULT R-0h 0 IN1N_FAULT R-0h LEGEND: R = Read only; -n = value after reset Table 19. FAULT_STATN: Fault Detect Negative Input Status Field Descriptions Bit Field Type Reset Description 7 IN8N_FAULT R 0h IN8N threshold detect. 0 = Channel 8 negative input pin does not exceed threshold set 1 = Channel 8 negative input pin exceeds threshold set 6 IN7N_FAULT R 0h IN7N threshold detect. 0 = Channel 7 negative input pin does not exceed threshold set 1 = Channel 7 negative input pin exceeds threshold set 5 IN6N_FAULT R 0h IN6N threshold detect. 0 = Channel 6 negative input pin does not exceed threshold set 1 = Channel 6 negative input pin exceeds threshold set 4 IN5N_FAULT R 0h IN5N threshold detect. 0 = Channel 5 negative input pin does not exceed threshold set 1 = Channel 5 negative input pin exceeds threshold set 3 IN4N_FAULT R 0h IN4N threshold detect. 0 = Channel 4 negative input pin does not exceed threshold set 1 = Channel 4 negative input pin exceeds threshold set 2 IN3N_FAULT R 0h IN3N threshold detect. 0 = Channel 3 negative input pin does not exceed threshold set 1 = Channel 3 negative input pin exceeds threshold set 1 IN2N_FAULT R 0h IN2N threshold detect. 0 = Channel 2 negative input pin does not exceed threshold set 1 = Channel 2 negative input pin exceeds threshold set 0 IN1N_FAULT R 0h IN1N threshold detect. 0 = Channel 1 negative input pin does not exceed threshold set 1 = Channel 1 negative input pin exceeds threshold set Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 45 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh] This register controls the format and state of the four GPIO pins. Figure 53. GPIO: General-Purpose IO Register 7 6 5 4 3 GPIOD[4:1] R/W-0h 2 1 0 GPIOC[4:1] R/W-Fh LEGEND: R/W = Read/Write; -n = value after reset Table 20. GPIO: General-Purpose IO Register Field Descriptions 46 Bit Field Type Reset Description 7-4 GPIOD[4:1] R/W 0h GPIO data. These bits are used to read and write data to the GPIO ports. When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are programmed as inputs or outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. 3-0 GPIOC[4:1] R/W Fh GPIO control (corresponding to GPIOD). These bits determine if the corresponding GPIOD pin is an input or output. 0 = Output 1 = Input Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information 10.1.1 Multiple Device Configuration The ADS131E08S provides configuration flexibility when multiple devices are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be operated on the same SPI bus. The number of signals needed to interface to N devices is 3 + N. 10.1.1.1 Synchronizing Multiple Devices When using multiple devices, the devices can be synchronized using the START signal. The delay time from the rising edge of the START signal to the falling edge of the DRDY signal is fixed for a given data rate (see the Conversion Mode section for more details on the settling times). Figure 54 shows the behavior of two devices when synchronized with the START signal. Device START CLK START1 DRDY DRDY1 CLK Device START2 DRDY DRDY2 CLK CLK START DRDY1 DRDY2 Figure 54. Synchronizing Multiple Converters To use the internal oscillator in a daisy-chain configuration, one device must be set as the master for the clock source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock must be brought out of the device by setting the CLK_EN register bit to 1. The master device clock is used as the external clock source for the other devices. There are two ways to connect multiple devices with an optimal number of interface pins: standard configuration and daisy-chain configuration. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 47 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Application Information (continued) 10.1.1.2 Standard Configuration Figure 55a shows a configuration with two ADS131E08s devices cascaded. Together, the devices create a system with 16 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT pin of this device is highimpedance. This structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the majority of applications where extra I/O pins are available. 10.1.1.3 Daisy-Chain Configuration Daisy-chain mode is enabled by setting the DAISY_IN bit in the CONFIG1 register. Figure 55b shows the daisychain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT pin of device 1 is connected to the DAISY_IN pin of device 0, thereby creating a daisy-chain for the data. Connect the DAISY_IN pin of device 1 to DGND if not used. The daisy-chain timing requirements for the SPI interface are illustrated in Figure 2. Data from the ADS131E08S device 0 appear first on DOUT, followed by a don’t care bit, and then the status and data words from the ADS131E08S device 1. The internal oscillator output cannot be enabled because all devices in the chain operate by sharing the same DIN pin, thus an external clock must be used. START(1) START CLK CLK DRDY CS INT GPO0 START(1) CLK START CLK DRDY CS INT GPO GPO1 Device 0 SCLK SCLK DIN MOSI DOUT MISO Device 0 DAISY_IN SCLK SCLK DIN MOSI DOUT MISO Host Processor START CLK Host Processor DOUT DRDY CS START SCLK CLK DIN Device 1 DRDY CS SCLK DIN DOUT Device 1 DAISY_IN b) Daisy-Chain Configuration a) Standard Configuration (1) To reduce pin count, set the START pin low and use the START command to synchronize and start conversions. Figure 55. Multiple Device Configurations There are several items to be aware of when using daisy-chain mode: 1. One extra SCLK must be issued between each data set (see Figure 56) 2. All devices are configured to the same register values because the CS signal is shared 3. Device register readback is only valid for device 0 in the daisy-chain. Only ADC conversion data can be read back from device 1 through device N, where N is the last device in the chain. 48 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Application Information (continued) The more devices in the chain, the more challenging adhering to setup and hold times becomes. A star-pattern connection of SCLK to all devices, minimizing the trace length of DOUT, and other printed circuit board (PCB) layout techniques helps to mitigate this challenge with signal delays. Placing delay circuits (such as buffers) between DOUT and DAISY_IN are options to help reduce signal delays. One other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Figure 56 shows a timing diagram for daisy-chain mode. DOUT MSB1 DAISY_IN CLKS DOUT 1 0 LSB1 2 3 n MSB0 n+1 LSB0 n+2 XX Data From First Device (ADS131E08S) MSB1 n+3 LSB1 Data From Second Device (ADS131E08S) NOTE: n = (number of channels) × (resolution) + 24 bits. The number of channels is 8. Resolution is 16 bits or 24 bits. Figure 56. Daisy-Chain Data Word The maximum number of devices that can be daisy-chained depends on the data rate that the devices are operated at. The maximum number of devices can be calculated with Equation 10. fSCLK NDEVICES = fDR (NBITS)(NCHANNELS) + 24 where: • • NBITS = device resolution (depends on DR[2:0] setting) NCHANNELS = number of channels powered up in the device (10) For example, when the ADS131E08S is operated in 24-bit, 8-kSPS data rate with fSCLK = 10 MHz, up to six devices can be daisy-chained together. 10.1.2 Power Monitoring Specific Applications All channels of the ADS131E08S are exactly identical, yet independently configurable, thus giving the user the flexibility of selecting any channel for voltage or current monitoring. An overview of a system configured to monitor voltage and current is illustrated in Figure 57. Also, the simultaneously sampling capability of the device allows the user to monitor both the current and the voltage at the same time. The full-scale differential input voltage of each channel is determined by the PGA gain setting (see the CHnSET: Individual Channel Settings section) for the respective channel and VREF (see the CONFIG3: Configuration Register 3 section). Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 49 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Application Information (continued) Neutral Phase C Phase B Phase A +1.5 V +1.8 V AVDD DVDD INP1 A N INN1 INP2 INN2 B INP3 INN3 N INP4 Device INN4 INP5 C INN5 N INP6 INN6 INN8 INN7 INP8 INP7 AVSS 1.5 V Figure 57. Overview of a Power-Monitoring System 50 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Application Information (continued) 10.1.3 Current Sensing Figure 58 illustrates a simplified diagram of typical configurations used for current sensing with a Rogowski coil, current transformer (CT), or an air coil that outputs a current or voltage. In the case of a current output transformer, the burden resistors (R1) are used for current-to-voltage conversion. The output of the burden resistors is connected to the ADS131E08S INxP and INxN inputs through an antialiasing RC filter for current sensing. In the case of a voltage output transformer for current sensing (such as certain types of Rogowski coils), the output terminals of the transformer are directly connected to the ADS131E08S INxP and INxN inputs through an antialiasing RC filter. The input network must be biased to mid-supply if using a unipolar-supply analog configuration (AVSS = 0 V, AVDD = 2.7 V to 5.5 V). The common-mode bias voltage [(AVDD + AVSS) / 2] can be obtained from the ADS131E08S by either configuring the internal op amp in a unity-gain configuration using the RF resistor and setting the OPAMP_REF bit of the CONFIG3 register to 1, or generated externally with a resistor divider network between the positive and negative supplies. Select the value of resistor R1 for the current output transformer and turns ratio of the transformer such that the ADS131E08S full-scale differential input voltage range is not exceeded. Likewise, select the output voltage for the voltage output transformer to not exceed the full-scale differential input voltage range. In addition, the selection of the resistors (R1 and R2) and turns ratio must not saturate the transformer over the full operating dynamic range. Figure 58a illustrates differential input current sensing and Figure 58b illustrates single-ended input voltage sensing. Use separate external op amps to source and sink current because the internal op amp has very limited current sink and source capability. Additionally, separate op amps for each channel help isolate individual phases from one another to limit crosstalk. 10.1.4 Voltage Sensing Figure 59 illustrates a simplified diagram of commonly-used differential and single-ended methods of voltage sensing. A resistor divider network is used to step down the line voltage to within the acceptable ADS131E08S input range and then connect to the inputs (INxP and INxN) through an antialiasing RC filter formed by resistor R3 and capacitor C. The common-mode bias voltage [(AVDD + AVSS) / 2] can be obtained from the ADS131E08S by either configuring the internal op amp in a unity-gain configuration using the RF resistor and setting the OPAMP_REF bit of the CONFIG3 register, or generated externally by using a resistor divider network between the positive and negative supplies. In either of the cases illustrated in Figure 59 (Figure 59a for a differential input and Figure 59b for a single-ended input), the line voltage is divided down by a factor of [R2 / (R1 + R2)]. Values of R1 and R2 must be carefully chosen so that the voltage across the ADS131E08S inputs (INxP and INxN) does not exceed the range of the ADS131E08S over the full operating dynamic range. Use separate external op amps to source and sink current because the internal op amp has very limited current sink and source capability. Additionally, separate op amps for each channel help isolate individual phases from one another to limit crosstalk. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 51 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com Application Information (continued) Device N L I R2 INxP R1 EMI Filter C To PGA R1 INxN R2 I + OPAMP_REF + OPAMPOUT - (AVDD + AVSS) 2 - Rf OPAMPN OPAMPP (a) Current Output CT with Differential Input Device N L Voltage Output CT R2 INxP EMI Filter C To PGA + OPAMPOUT - Rf + INxN OPAMP_REF (AVDD + AVSS) 2 OPAMPN OPAMPP (b) Voltage Output CT with Single-Ended Input Figure 58. Simplified Current-Sensing Connections 52 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Application Information (continued) Device N L R1 R3 INxP R2 EMI Filter C R2 INxN R3 OPAMPOUT + - + R1 To PGA OPAMP_REF (AVDD + AVSS) 2 - RF OPAMPN OPAMPP (a) Voltage Sensing with Differential Input Device N L R1 R3 R2 INxP EMI Filter C To PGA + OPAMPOUT - + INxN OPAMP_REF (AVDD + AVSS) 2 - RF OPAMPN OPAMPP (b) Voltage Sensing with Single-Ended Input Figure 59. Simplified Voltage-Sensing Connections Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 53 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 10.2 Typical Application Figure 60 shows the ADS131E08S being used as part of an electronic trip unit (ETU) in a circuit breaker or protection relay. Delta-sigma (ΔΣ), analog-to-digital converters (ADCs), such as the ADS131E08S, are ideal for this application because these devices provide a wide dynamic range. The fast power-up time of the ADS131E08S makes the device an ideal candidate for line-powered circuit breaker applications. The system measures voltages and currents output from a breaker enclosure. In this example, the first three inputs measure line voltage and the remaining five inputs measure line current from the secondary winding of a current transformer (CT). A voltage divider steps down the voltage from the output of the breaker. Several resistors are used to break up power consumption and are used as a form of fault protection against any potential resistor short-circuit. After the voltage step down, RC filters are used for antialiasing and diodes protect the inputs from overrange. -2.5 V RDiv1 RDiv1 RDiv1 RDiv1 RDiv1 2.5 V 2.5 V RFilt RDiv1 IN1P Voltage Output AVDD CCom RDiv2 CDif RDiv2 RFilt IN1N CCom -2.5 V 2.5 V Breaker Enclosure -2.5 V 2.5 V Device RFilt IN4P CCom Current Output RBurden RBurden CDif RFilt IN4N CCom -2.5 V 2.5 V AVSS -2.5 V Figure 60. ETU Block Diagram: High-Resolution and Fast Power-Up Analog Front-End for Air Circuit Breaker or Molded Case Circuit Breaker and Protection Relay 54 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 Typical Application (continued) 10.2.1 Design Requirements Table 21 summarizes the design requirements for the circuit breaker front-end application. Table 21. ETU Circuit Breaker Design Requirements DESIGN PARAMETER VALUE ADC power-up < 3 ms Number of voltage inputs 3 Voltage input range 10 V to 750 V Number of current inputs 5 Current input range 50 mA to 25 A Dynamic range with fixed gain > 500 Accuracy ±1% 10.2.2 Detailed Design Procedure The line voltage is stepped down to a voltage range within the measurable range of the ADC. The reference voltage determines the range in which the ADC can measure signals. The ADS131E08S has two integrated lowdrift reference voltage options: 2.4 V and 4 V. Equation 11 describes the transfer function for the voltage divider at the input in Figure 60. Using multiple series resistors, RDIV1, and multiple parallel resistors, RDIV2, allows for power and heat to be dissipated among several circuit elements and serves as protection against a potential short-circuit across a single resistor. The number of resistors trade off with nominal accuracy because each additional element introduces an additional source of tolerance. VIN § · 0.5 u RDiv2 VPhase u ¨ ¸ © 6 u RDiv1 0.5 u RDiv2 ¹ (11) The step-down resistor, RDiv2, dominates the measurement error produced by the resistor network. Using input PGAs on the ADS131E08S helps to mitigate this error source by allowing RDiv2 to be made smaller and then amplifying the signal to near full-scale using the ADS131E08S PGA. For this design, RDiv1 is set to 200 kΩ and RDiv2 is set to 2.4 kΩ to provide proper signal attenuation at a sufficient power level across each resistor. The input saturates at values greater than ±750 V when using the ADS131E08S internal 2.4-V reference and a PGA gain of 2. The ADS131E08S measures the line current by creating a voltage across the burden resistance (RBurden in Figure 60) in parallel with the secondary winding of a CT. As with the voltage measurement front-end, multiple resistors (RDiv1) that are used to step down a voltage share the duty of dissipating power. In this design, RBURDEN is set to 33 Ω. Used with a 1:500 turns ratio CT, the ADC input saturates with a line current over 25 A when the ADC is configured using the internal 2.4-V reference and a PGA gain of 2. Diodes protect the ADS131E08S inputs from overvoltage and current. Diodes on each input shunt to either supply if the input voltage exceeds the safe range for the device. On current inputs, a diode shunts the inputs if current on the secondary winding of the CT threatens to damage the device. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 55 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com The combination of RFilt, CCom, and CDif form the antialiasing filters for each of the inputs. The differential capacitor CDif improves the common-mode rejection of the system by sharing its tolerance between the positive and negative input. The antialiasing filter requirement is not strict because the nature of a ΔΣ converter (with oversampling and digital filter) attenuates a significant proportion of out-of-band noise. In addition, the input PGAs have intentionally low bandwidth to provide additional antialiasing. The component values used in this design are RFilt = 1 kΩ, CCom = 47 pF, and CDif = 0.015 μF. This first-order filter produces a relatively flat frequency response beyond 2 kHz, capable of measuring greater than 30 harmonics at a 50-Hz or 60-Hz fundamental frequency. The 3-dB cutoff frequency of the filter is 5.3 kHz for each input channel. The ETU in a circuit breaker or protection relay can be powered from the line. In this case, fast power-up is required to allow the ADC to begin making measurements shortly after power is restored. The ADS131E08S is designed to fully power-up and collect data in less than 3 ms. Each analog system block introduces errors from input to output. Protection CTs in the 5P accuracy class can introduce as much as ±1% current error from input to output. CTs in the 10P accuracy class can introduce as much as ±3% error. The burden resistor also introduces errors in the form of resistor tolerance and temperature drift. For the voltage input, error comes from the divider network in the form of resistor tolerance and temperature drift. Finally, the converter introduces errors in the form of offset error, gain error, and reference error. All of these specifications can drift over temperature. 10.2.3 Application Curves Accuracy is measured using a system designed in a similar way to that illustrated in Figure 60. The CT used for the current input is CT1231 (a 0.3 class, solid core, 5:2500 turns transformer). In each case, data are taken for three channels over one cycle of the measured waveform and the RMS input-referred signal is compared to the output to calculate the error. The equation used to derive the measurement error is shown in Equation 12. Data are taken using both the 2.4-V and 4-V internal reference voltages. In all cases, measured accuracy is within ±1%. § Measured Actual · Measurement Accuracy(%) ¨ ¸ u 100 Actual © ¹ (12) 0.35 0.22 0.18 Ch 1 Ch 2 Ch 3 0.325 Measurement Error (%) Measurement Error (%) 0.2 0.16 0.14 0.12 0.1 0.08 300 200 100 70 50 40 30 AC Input Voltage (V) 20 10 0.25 0.225 0.2 0.175 0.125 1000 700 500 D018 One 50-Hz line cycle , 4-kSPS data rate, 80 samples, gain = 2, VREF = 2.4 V, measurement accuracy is absolute value Figure 61. Input Voltage vs ADC Measurement Error: 2.4-V Reference 56 0.275 0.15 0.06 0.04 1000 700 500 0.3 Ch 1 Ch 2 Ch 3 300 200 100 70 50 40 30 AC Input Voltage (V) 20 10 D019 One 50-Hz line cycle , 4-kSPS data rate, 80 samples, gain = 2, VREF = 4 V, measurement accuracy is absolute value Figure 62. Input Voltage vs ADC Measurement Error: 4-V Reference Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 0.2 0.2 Ch 1 Ch 2 Ch 3 0 -0.1 -0.2 -0.3 -0.4 0 -0.1 -0.2 -0.3 -0.5 -0.6 2520 Ch 1 Ch 2 Ch 3 0.1 Measurement Error (%) Measurement Error (%) 0.1 10 87 6 5 4 3 2 1 0.7 0.5 0.3 0.2 AC Current Input (A) 0.1 0.04 -0.4 4030 20 D020 10 7 6 5 4 3 2 1 0.5 0.3 0.2 AC Current Input (A) 0.1 0.04 D020 One 50-Hz line cycle , 4-kSPS data rate, 80 samples, gain = 2, VREF = 2.4 V One 50-Hz line cycle , 4-kSPS data rate, 80 samples, gain = 2, VREF = 4 V Figure 63. Input Current vs ADC Measurement Error: 2.4-V Reference Figure 64. Input Current vs ADC measurement Error: 4-V Reference For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see HighResolution, Fast Start-Up, Delta-Sigma ADC-Based AFE for Air Circuit Breaker (ACB) Reference Design reference guide. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 57 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 10.3 Initialization Set Up 10.3.1 Setting the Device Up for Basic Data Capture This section outlines the procedure to configure the device to capture data. Follow the steps shown in Figure 65 to put the ADS131E08S in a configured state to acquire data within the specified 3-ms power-up time. For details on the timings for commands, see the appropriate sections in this document. The flow chart of Figure 65 details the initial ADS131E08S configuration and setup. Power-up Analog + Digital Supply SET /PWDN = 1 START = 1 If CLKSEL = 0 Provide CLK CLKSEL Pin State If CLKSEL = 1 Wait 20 µs for Oscillator power-up SET /RESET = 1 Yes tSTABLE wait time // Analog and Digital supply can come up together // Can come up with Power Supply // If external CLK, wait 50 µs before providing CLK // Can come up with Power Supply // Follow power-up timing Use Default Register Settings? No Set START = 0 Send SDATAC Command // Registers can be written during tSTABLE wait time // Device wakes up in RDATAC mode // Changing register settings can occur during tSTABLE wait time. Configure Registers using WREG command // Changing register settings can occur during tSTABLE wait time. Send RDATAC command Set START = 1 Capture Data // Put device back in RDATAC mode // Start conversions again // Changing register settings can occur during tSTABLE wait time. // Monitor for DRDY to shift data out Figure 65. Initial Flow at Power-Up 58 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 11 Power Supply Recommendations 11.1 Power-Up Timing Settled data from the ADS131E08S are available within 3 ms of power-up if a strict timing sequence is followed. Before device power-up, all digital and analog inputs must be held low. Provide the master clock 50 µs after the analog and digital supplies reach 90% of their nominal values, shown as tPCLK in Figure 66. Pull the RESET pin high following the tPRST timing to bring the ADC digital filters out of a reset state and to begin the conversion process. Settled data are available at the first DRDY falling edge, shown as tSETTLE in Figure 66. These data are from the settled digital filter; however, the first data set may not be a settled representation of the input because additional time is required for the reference and critical voltage nodes to settle to their final values. The tSTABLE timing adds the recommended wait time for settled data to be available at the ADC output. When the tSTABLE time has passed, the next DRDY falling edge indicates a valid conversion result of the input signal where both the digital filter and node voltages are settled. 90% AVDD tPCLK CLK tPRST § § RESET tSETTLE tSTABLE § § DRDY Figure 66. Power-Up Timing Diagram Table 22. Power-Up Sequence Timing MIN tPCLK tPRST Delay time, first external CLK rising edge after AVDD reaches 90% 50 Delay time, internal oscillator start-up after AVDD reaches 90% 20 MAX UNIT µs Delay time, RESET rising edge after first CLK rising edge 2 tCLK (1) 2312 tCLK 2.2 ms tSETTLE Settling time, first settled data after RESET rising edge tSTABLE Settling time, valid data after RESET rising edge (1) TYP Timing is for the 4-kSPS data rate; see Table 5 for digital filter settling times for different data rates. To deviate from the default register settings, write to the ADS131E08S registers after pulling the RESET pin high. Changes to any of the registers delay the tSETTLE start point until the register write is complete. If the data rate is changed following the RESET pin going high, the tSETTLE timing takes on the settling characteristics of Table 5 relative to the completion of the command. Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 59 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 11.2 Recommended External Capacitor Values The ADS131E08S power-up time is set by the time required for the critical voltage nodes to settle to their final values. The analog supplies (AVDD and AVSS), digital supply (DVDD), and internal node voltages (VCAPx pins) must be up and stable when the data converter samples are taken to ensure performance. The combined current sourcing capability of the supplies and size of the bypass capacitors dictate the ramp rate of AVDD, AVSS, and DVDD. The VCAPx voltages are charged internally using the supply voltages. Table 23 lists the internal node voltages, their function, and recommended capacitor values to optimize the power-up time. Table 23. Recommended External Capacitor Values PIN FUNCTION RECOMMENDED CAPACITOR VALUE 28 Band-gap voltage for the ADC 470 pF to AVSS VCAP2 30 Modulator common-mode 270 nF to AVSS VCAP3 55 PGA charge pump 270 nF to AVSS VCAP4 26 Reference common-mode 270 nF to AVSS VREFP 24 Reference voltage after the internal buffer 330 nF to AVSS 1 µF each to AVSS NAME NO. VCAP1 AVDD 19, 21, 22, 56, 59 Analog supply AVDD1 54 Internal PGA charge pump analog supply 1 µF to AVSS1 AVSS 20, 23, 32, 57, 58 Analog supply 1 µF each to AVDD AVSS1 53 Internal PGA charge pump analog supply 1 µF to AVDD1 DVDD 48, 50 Digital supply 1 µF each to DGND 11.3 Device Connections for Unipolar Power Supplies Figure 67 shows the ADS131E08S connected to a unipolar supply. In this example, the analog supply (AVDD) is referenced to the analog ground (AVSS) and the digital supply (DVDD) is referenced to the digital ground (DGND). The ADS131E08S supports an analog supply range of AVDD = 2.7 V to 5.25 V when operated in unipolar supply mode. 3V 3V 1.8 V 1 F 1 F 1 F AVSS AVSS1 AVDD1 AVDD DVDD VREFP VREFN 330 nF VCAP1 RESV1 VCAP2 Device VCAP3 VCAP4 AVSS1 AVSS DGND 270 nF 270 nF 270 nF 470 pF NOTE: Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible. Figure 67. Unipolar Power Supply Operation 60 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 11.4 Device Connections for Bipolar Power Supplies Figure 68 shows the ADS131E08S connected to a bipolar supply. In this example, the analog supply (AVDD) is referenced to the analog ground (AVSS) and the digital supply (DVDD) is referenced to the digital ground (DGND). The ADS131E08S supports an analog supply range of AVDD and AVSS = ±1.5 V to ±2.5 V when operated in bipolar supply mode. 2.5 V 2.5 V 1.8 V 1 F 1 F 0.1 F AVSS AVSS1 AVDD1 AVDD DVDD VREFP VREFN Device RESV1 VCAP1 330 nF -2.5 V VCAP2 VCAP3 VCAP4 AVSS1 AVSS DGND 270 nF 270 nF 270 nF 470 pF 2.5 V 2.5 V NOTE: Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible. Figure 68. Bipolar Power Supply Operation Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 61 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 12 Layout 12.1 Layout Guidelines Use a low-impedance connection for ground so that return currents flow undisturbed back to their respective sources. For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. Keep connections to the ground plane as short and direct as possible. When using vias to connect to the ground layer, use multiple vias in parallel to reduce impedance to ground. A mixed-signal layout sometimes incorporates separate analog and digital ground planes that are tied together at one location; however, separating the ground planes is not necessary when analog, digital, and power-supply components are properly placed. Proper placement of components partitions the analog, digital, and powersupply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog circuitry. If ground plane separation is necessary, then make the connection at the ADC. Connecting individual ground planes at multiple locations creates ground loops, and is not recommended. A single ground plane for analog and digital avoids ground loops. Bypass supply pins with a low-equivalent series resistance (ESR) ceramic capacitor. The placement of the bypass capacitors must be as close as possible to the supply pins using short, direct traces. For optimum performance, the ground-side connections of the bypass capacitors must also be low-impedance connections. The supply current flows through the bypass capacitor terminal first and then to the supply pin to make the bypassing most effective (also known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power-supply traces or dedicated power-supply planes to minimize the potential of crosstalk between ADCs. If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G capacitors have stable properties and low-noise characteristics. Ideally, route differential signals as pairs to minimize the loop area between the traces. Route digital circuit traces (such as clock signals) away from all analog pins. The internal reference output return shares the same pin as the AVSS power supply. To minimize coupling between the power-supply trace and reference return trace, route the two traces separately; ideally, as a star connection at the AVSS pin. Short, direct interconnections must be made on analog input lines and stray wiring capacitance must be avoided, particularly between the analog input pins and AVSS. These analog input pins are high-impedance and are extremely sensitive to extraneous noise. Treat the AVSS pin as a sensitive analog signal and connect directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the ADS131E08S if shielding is not implemented. Keep digital signals as far as possible from the analog input signals on the PCB. The SCLK input of the serial interface must be free from noise and glitches. Even with relatively slow SCLK frequencies, short digital signal rise and fall times can cause excessive ringing and noise. For best performance, keep the digital signal traces short, using termination resistors as needed, and make sure all digital signals are routed directly above the ground plane with minimal use of vias. Figure 69 shows the ideal placement of system components. Ground Fill or Ground Plane Supply Generation Interface Transceiver Microcontroller Device Optional: Split Ground Cut Signal Conditioning (RC Filters and Amplifiers) Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Connector or Antenna Ground Fill or Ground Plane Figure 69. System Component Placement 62 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S ADS131E08S www.ti.com SBAS705B – JUNE 2015 – REVISED APRIL 2020 12.2 Layout Example Figure 70 shows an example layout of the ADS131E08S requiring a minimum of two PCB layers. The example circuit is shown for either a unipolar analog supply connection or a bipolar analog supply connection. In this example, polygon pours are used as supply connections around the device. If a three- or four-layer PCB is used, the additional inner layers can be dedicated to route power traces. The PCB is partitioned with analog signals routed from the left, digital signals routed to the right, and power routed above and below the device. Via to AVSS pour or plane. DGND DVDD DGND CLKSEL AVSS1 AVDD1 AVSS AVSS VCAP3 AVDD AVDD OPAMPP OPAMPN NC OPAMPO UT NC Via to digital ground pour or plane. Input filtered with differential and common-mode capacitors. IN8N DVDD IN8P DRDY IN7N GPIO4 IN7P GPIO3 IN6N GPIO2 IN6P DOUT IN5N GPIO1 IN5P DAISY_IN ADS131E08S AVSS RESV1 VCAP2 NC VCAP1 NC VCAP4 VREFP VREFN DGND AVSS DIN IN1P AVDD PWDN IN1N AVDD RESET IN2P AVSS CLK IN2N TESTP START IN3P AVDD SCLK CS IN3N TESTN IN4N IN4P Long digital input lines terminated with resistors to prevent reflection. Reference, VCAP, and power-supply decoupling capacitors close to pins. Figure 70. ADS131E08S Layout Example Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S 63 ADS131E08S SBAS705B – JUNE 2015 – REVISED APRIL 2020 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: • Texas Instruments, ADS131E0x 4-, 6-, and 8-Channel, 24-Bit, Simultaneously-Sampling, Delta-Sigma ADC data sheet • Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet • Texas Instruments, High-Resolution, Fast Start-Up, Delta-Sigma ADC-Based AFE for Air Circuit Breaker (ACB) Reference Design reference guide 13.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.3 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 64 Submit Documentation Feedback Copyright © 2015–2020, Texas Instruments Incorporated Product Folder Links: ADS131E08S PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) ADS131E08SPAG ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 ADS131E08S ADS131E08SPAGR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 ADS131E08S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of