ADS1602IPFBTG4

ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com 16-Bit, 2.5MSPS Analog-to-Digital Converter Check for Samples: ADS1602 FEATURES DESCRIPTION • The ADS1602 is a high-speed, high-precision, delta-sigma (ΔΣ) analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1602 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs. Consequently, signal-to-noise ratio (SNR) is particularly improved. Total harmonic distortion (THD) is –101dB, and the spurious-free dynamic range (SFDR) is 103dB. 1 2 • • • High Speed: – Data Rate: 2.5MSPS – Bandwidth: 1.23MHz Outstanding Performance: – SNR: 91dB at fIN = 100kHz, –1dBFS – THD: –101dB at fIN = 100kHz, –6dBFS – SFDR: 103dB at fIN = 100kHz, –6dBFS Ease-of-Use: – High-Speed 3-Wire Serial Interface – Directly Connects to TMS320 DSPs – On-Chip Digital Filter Simplifies Antialias Requirements – Simple Pin-Driven Control—No On-Chip Registers to Program – Selectable On-Chip Voltage Reference – Simultaneous Sampling with Multiple ADS1602s Low Power: – 530mW at 2.5MSPS – Power-Down Mode APPLICATIONS • • • Sonar Vibration Analysis Data Acquisition VREFP VREFN VMID RBIAS VCAP AVDD DVDD IOVDD CLK SYNC Reference and Bias Circuits FSO FSO AINP AINN DS Modulator Linear Phase FIR Digital Filter Serial Interface SCLK SCLK DOUT DOUT OTR PD ADS1602 AGND REFEN DGND Optimized for power and performance, the ADS1602 dissipates only 530mW while providing a full-scale differential input range of ±3V. Having such a wide input range makes out-of-range signals unlikely. The OTR pin indicates if an analog input out-of-range condition does occur. The differential input signal is measured against the differential reference, which can be generated internally or supplied externally on the ADS1602. The ADS1602 uses an inherently stable advanced modulator with an on-chip decimation filter. The filter stop band extends to 38.6MHz, which greatly simplifies the antialiasing circuitry. The modulator samples the input signal up to 40MSPS, depending on fCLK, while the 16x decimation filter uses a series of four half-band FIR filter stages to provide 75dB of stop band attenuation and 0.001dB of passband ripple. Output data is provided over a simple 3-wire serial interface at rates up to 2.5MSPS, with a –3dB bandwidth of 1.23MHz. The output data or its complementary format directly connects to DSPs such as TI’s TMS320 family, FPGAs, or ASICs. A dedicated synchronization pin enables simultaneous sampling with multiple ADS1602s in multi-channel systems. Power dissipation is set by an external resistor that allows a reduction in dissipation when operating at slower speeds. All of the ADS1602 features are controlled by dedicated I/O pins, which simplify operation by eliminating the need for on-chip registers. The high performing, easy-to-use ADS1602 is especially suitable for demanding measurement applications in sonar, vibration analysis, and data acquisition. The ADS1602 is offered in a small, 7mm × 7mm TQFP-48 package and is specified from –40°C to +85°C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS1602 UNIT AVDD to AGND –0.3 to +6 V DVDD to DGND –0.3 to +3.6 V IOVDD to DGND –0.3 to +6 V –0.3 to +0.3 V Input current 100, momentary mA Input current 10, continuous mA Analog I/O to AGND –0.3 to AVDD + 0.3 V Digital I/O to DGND –0.3 to IOVDD + 0.3 V +150 °C Operating temperature range –40 to +105 °C Storage temperature range –60 to +150 °C AGND to DGND Maximum junction temperature (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Differential input voltage (VIN) (AINP – AINN) 0dBFS Common-mode input voltage (VCM) (AINP + AINN) / 2 Absolute input voltage (AINP or AINN with respect to AGND) ±VREF V 1.45 V –0.1 4.6 V Dynamic Specifications 2.5 Data rate fIN = 10kHz, –1dBFS Total harmonic distortion (THD) 92 dB 90 dB fIN = 10kHz, –6dBFS 84 87 dB 91 dB fIN = 100kHz, –3dBFS 87 89 dB fIN = 100kHz, –6dBFS 84 86 dB fIN = 800kHz, –1dBFS 91 dB fIN = 800kHz, –3dBFS 89 dB fIN = 800kHz, –6dBFS 86 dB fIN = 10kHz, –1dBFS –94 fIN = 10kHz, –3dBFS –106 –92 dB fIN = 10kHz, –6dBFS –108 –93 dB fIN = 100kHz, –1dBFS –90 fIN = 100kHz, –3dBFS –96 –90 dB fIN = 100kHz, –6dBFS –101 –92 dB fIN = 800kHz, –1dBFS –116 dB fIN = 800kHz, –3dBFS –114 dB fIN = 800kHz, –6dBFS –110 dB Aperture delay Copyright © 2004–2011, Texas Instruments Incorporated dB 89 dB 85 90 dB fIN = 10kHz, –6dBFS 82 87 dB 87 dB fIN = 100kHz, –3dBFS 85 88 dB fIN = 100kHz, –6dBFS 82 86 dB fIN = 800kHz, –1dBFS 91 dB fIN = 800kHz, –3dBFS 89 dB fIN = 800kHz, –6dBFS 86 dB fIN = 10kHz, –1dBFS 95 dB fIN = 10kHz, –3dBFS 90 107 dB fIN = 10kHz, –6dBFS 93 112 dB 91 dB fIN = 100kHz, –1dBFS Intermodulation distortion (IMD) dB fIN = 10kHz, –3dBFS fIN = 100kHz, –1dBFS Spurious-free dynamic range (SFDR) MSPS 87 fIN = 10kHz, –1dBFS Signal-to-noise + distortion (SINAD) CLK fIN = 10kHz, –3dBFS fIN = 100kHz, –1dBFS Signal-to-noise ratio (SNR) f ( 40MHz ) fIN = 100kHz, –3dBFS 90 96 dB fIN = 100kHz, –6dBFS 93 103 dB fIN = 800kHz, –1dBFS 120 dB fIN = 800kHz, –3dBFS 119 dB fIN = 800kHz, –6dBFS 114 dB f1 = 995kHz, –6dBFS f2 = 1005kHz, –6dBFS 94 dB 4 ns 3 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Filter Characteristics Passband 1.1 0 f ( 40MHz ) CLK ±0.001 Passband ripple fCLK 1.15 40MHz ( –0.1dB attenuation Passband transition 1.23 –3dB attentuation 1.4 Stop band Stop band attenuation dB ) MHz f ( 40MHz ) MHz CLK f ( 40MHz ) CLK 38.6 f ( 40MHz ) CLK MHz 75 dB 40MHz 10.4 fCLK ( Group delay Settling time MHz 20.4 Complete settling ) μs ( 40MHz ) f μs CLK Static Specifications Resolution 16 No missing codes Input-referred noise Integral nonlinearity Bits 16 0.5 –1dBFS signal Bits 0.85 LSB, rms 0.75 LSB Differential nonlinearity 0.25 LSB Offset error –0.1 %FSR –0.1 ppmFSR/°C Offset error drift 0.25 (1) % Excluding reference drift 10 ppm/°C Common-mode rejection At dc 75 dB Power-supply rejection At dc 65 dB Gain error Gain error drift Internal Voltage Reference REFEN = low VREF = (VREFP – VREFN) 2.75 3 3.25 V VREFP 3.5 4 4.3 V VREFN 0.5 1 1.3 V VMID 2.3 2.5 2.7 VREF drift Startup time External Voltage Reference VREF = (VREFP – VREFN) V 50 ppm/°C 15 ms REFEN = high 2 3 3.25 V VREFP 3.5 4 4.25 V VREFN 0.5 1 1.5 V VMID 2.3 2.5 2.6 V (1) 4 There is a constant gain error of 2.5% in addition to the variable gain error of ±0.25%. Therefore, the gain error is 2.5 ± 0.25%. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN fCLK = 40MHz 45 TYP MAX UNIT 40 MHz 55 % IOVDD V Clock Input Frequency (fCLK) Duty cycle Digital Input/Output VIH 0.7 × IOVDD VIL DGND 0.3 × IOVDD IOVDD – 0.5 V VOH IOH = 50μA VOL IOL = 50μA DGND + 0.5 V DGND < VDIGIN < IOVDD ±10 μA Input leakage V Power-Supply Requirements AVDD 4.75 5.25 V DVDD 2.7 3.3 V 2.7 5.25 V IOVDD AVDD current (IAVDD) IOH = 50μA REFEN = low 110 125 mA REFEN = high 88 98 mA DVDD current (IDVDD) IOVDD = 3V 25 30 mA IOVDD current (IIOVDD) IOVDD = 3V 8 10 mA AVDD = 5V, DVDD = 3V, IOVDD = 3V, REFEN = high 530 610 mW PD = low, CLK disabled 10 Power dissipation mW Temperature Range Specified –40 +85 °C Operating –40 +105 °C Storage –60 +150 °C Copyright © 2004–2011, Texas Instruments Incorporated 5 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com DEFINITIONS Absolute Input Voltage Intermodulation Distortion (IMD) Absolute input voltage, given in volts, is the voltage of each analog input (AINN or AINP) with respect to AGND. IMD, given in dB, is measured while applying two input signals of the same magnitude, but with slightly different frequencies. It is calculated as the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. Aperture Delay Aperture delay is the delay between the rising edge of CLK and the sampling of the input signal. Common-Mode Input Voltage Common-mode input voltage (VCM) is the average voltage of the analog inputs: Offset Error Offset Error, given in % of FSR, is the output reading when the differential input is zero. Offset Error Drift Differential Input Voltage Offset error drift, given in ppm of FSR/°C, is the drift over temperature of the offset error. The offset error is specified as the larger of the drift from ambient (T = +25°C) to the minimum or maximum operating temperatures. Differential input voltage (VIN) is the voltage difference between the analog inputs (AINP − AINN). Signal-to-Noise Ratio (SNR) (AINP + AINN) 2 DNL, given in least-significant bits of the output code (LSB), is the maximum deviation of the output code step sizes from the ideal value of 1LSB. SNR, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components below fCLK/2 (the Nyquist frequency) excluding the first six harmonics of the input signal and the dc component. Full-Scale Range (FSR) Signal-to-Noise and Distortion (SINAD) FSR is the difference between the maximum and minimum measurable input signals (FSR = 2VREF). SINAD, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components below fCLK/2 (the Nyquist frequency) including the harmonics of the input signal but excluding the dc component. Differential Nonlinearity (DNL) Gain Error Gain error, given in %, is the error of the full-scale input signal with respect to the ideal value. Gain Error Drift Gain error drift, given in ppm/°C, is the drift over temperature of the gain error. The gain error is specified as the larger of the drift from ambient (T = +25°C) to the minimum or maximum operating temperatures. Integral Nonlinearity (INL) Spurious-Free Dynamic Range (SFDR) SFDR, given in dB, is the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. Total Harmonic Distortion (THD) THD, given in dB, is the ratio of the sum of the rms value of the first six harmonics of the input signal to the rms value of the input signal. INL, given in least-significant bits of the output code (LSB), is the maximum deviation of the output codes from a best fit line. 6 Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com IOVDD AGND DGND CLK AVDD 48 47 46 45 44 43 42 AGND VREFN VCAP VMID VREFN VREFP VREFP PIN ASSIGNMENTS 41 40 39 38 37 AGND 1 36 AVDD 2 35 NC AGND 3 34 DVDD AINN 4 33 DGND AINP 5 32 FSO DGND AGND 6 AVDD 7 RBIAS 8 29 DOUT AGND 9 28 SCLK ADS1602 31 FSO 30 DOUT SCLK NC AVDD 12 25 NC NC DVDD OTR 21 22 23 24 DGND PD DVDD NC RPULLUP 20 NC 13 14 15 16 17 18 19 SYNC 27 26 DGND AVDD 10 AGND 11 REFEN TQFP PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL FUNCTION DESCRIPTION 1, 3, 6, 9, 11, 39, 41 Analog Analog ground 2, 7, 10, 12, 42 Analog Analog supply AINN 4 Analog input Negative analog input AINP 5 Analog input Positive analog input RBIAS 8 Analog REFEN 13 Digital input: active low 14, 16, 24–26, 35 Do not connect RPULLUP 15 Digital input PD 17 Digital input: active low DVDD 18, 23, 34 Digital Digital supply DGND 19, 22, 33, 36, 38 Digital Digital ground SYNC 20 Digital input Synchronization control input OTR 21 Digital output Indicates analog input signal is out of range. SCLK 28 Digital output Serial clock output SCLK 27 Digital output Serial clock output, complementary signal. DOUT 30 Digital output Data output DOUT 29 Digital output Data output, complementary signal. FSO 32 Digital output Frame synchronization output FSO 31 Digital output Frame synchronization output, complementary signal. IOVDD 37 Digital CLK 40 Digital input VCAP 43 Analog Terminal for external bypass capacitor connection to internal bias voltage. 44, 45 Analog Negative reference voltage 46 Analog Midpoint voltage 47, 48 Analog Positive reference voltage NAME NO. AGND AVDD NC VREFN VMID VREFP Copyright © 2004–2011, Texas Instruments Incorporated Terminal for external analog bias setting resistor. Internal reference enable. Internal pull-down resistor of 170kΩ to DGND. These terminals must be left unconnected. Pull-up to DVDD with 10kΩ resistor (see Figure 53). Power-down all circuitry. Internal pull-up resistor of 170kΩ to DGND. Digital I/O supply Clock input 7 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TIMING DIAGRAMS tC CLK tHSC tSSC SYNC tSYPW tSTL FSO Figure 1. Initialization Timing TIMING REQUIREMENTS For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V. SYMBOL tSYPW tC DESCRIPTION MIN SYNC positive pulse width TYP MAX 1 UNIT CLK period Clock period (CLK) 25 ns tSSC Setup time; SYNC rising edge to CLK rising edge 0.5 CLK period tHSC Hold time; CLK rising edge to SYNC falling edge 0.5 CLK period tSTL Settling time of the ADS1602; FSO falling edge to next FSO rising edge 833 CLK periods tCPW CLK tCPW tCS SCLK tCF tFPW tDH FSO tDS DOUT MSB BIT 14 BIT 1 LSB New Data Figure 2. Data Retrieval Timing TIMING REQUIREMENTS For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V. SYMBOL 8 MAX UNIT tCS DESCRIPTION Rising edge of CLK to rising edge of SCLK 15 ns tCF Rising edge of SCLK to rising edge of FSO 5 ns tCPW CLK positive or negative pulse width tFPW Frame sync output high pulse width tDS SCLK rising edge to new DOUT valid tDH SCLK falling edge to DOUT invalid MIN TYP 11.25 ns 1 CLK period 5 6 ns ns Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 Amplitude (dB) -40 -60 -80 -100 fIN = 10kHz, -6dBFS SNR = 87dB THD = -108dB SFDR = 112dB -20 -40 Amplitude (dB) fIN = 10kHz, -1dBFS SNR = 92dB THD = -94dB SFDR = 95dB -20 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 200 400 600 800 Frequency (kHz) 1000 0 1200 200 400 Figure 3. SPECTRAL RESPONSE 1200 SPECTRAL RESPONSE 0 -40 -60 -80 -100 fIN = 100kHz, -1dBFS SNR = 90dB THD = -90dB SFDR = 91dB -20 -40 Amplitude (dB) fIN = 10kHz, -10dBFS SNR = 83dB THD = -105dB SFDR = 110dB -20 Amplitude (dB) 1000 Figure 4. 0 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 200 400 600 800 Frequency (kHz) 1000 1200 0 200 400 Figure 5. 600 800 Frequency (kHz) 1000 1200 Figure 6. SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 -140 -160 fIN = 100kHz, -10dBFS SNR = 82dB THD = -100dB SFDR = 102dB -20 Amplitude (dB) fIN = 100kHz, -6dBFS SNR = 86dB THD = -101dB SFDR = 103dB -20 Amplitude (dB) 600 800 Frequency (kHz) -160 0 200 400 600 800 Frequency (kHz) Figure 7. Copyright © 2004–2011, Texas Instruments Incorporated 1000 1200 0 200 400 600 800 Frequency (kHz) 1000 1200 Figure 8. 9 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 Amplitude (dB) -40 -60 -80 -100 fIN = 504kHz, -6dBFS SNR = 86dB THD = -103dB SFDR = 103dB -20 -40 Amplitude (dB) fIN = 504kHz, -1dBFS SNR = 91dB THD = -119dB SFDR = 119dB -20 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 200 400 600 800 Frequency (kHz) 1000 0 1200 200 400 Figure 9. SPECTRAL RESPONSE 1000 1200 1000 1200 SPECTRAL RESPONSE -60 -80 -100 fIN = 799kHz, -1dBFS SNR = 91dB THD = -116dB SFDR = 120dB -20 -40 Amplitude (dB) fIN = 504kHz, -10dBFS SNR = 82dB THD = -96dB SFDR = 96dB -40 Amplitude (dB) 1200 0 -20 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 200 400 600 800 Frequency (kHz) 1000 1200 0 200 400 Figure 11. 600 800 Frequency (kHz) Figure 12. SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 fIN = 799kHz, -6dBFS SNR = 86dB THD = -110dB SFDR = 114dB -20 fIN = 799kHz, -10dBFS SNR = 82dB THD = -107dB SFDR = 112dB -20 -40 Amplitude (dB) -40 Amplitude (dB) 1000 Figure 10. 0 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 200 400 600 800 Frequency (kHz) Figure 13. 10 600 800 Frequency (kHz) 1000 1200 0 200 400 600 800 Frequency (kHz) Figure 14. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SNR, THD, AND SFDR vs INPUT SIGNAL AMPLITUDE SNR, THD, AND SFDR vs INPUT SIGNAL AMPLITUDE 120 Signal-to-Noise Ratio, Total Harmonic Distortion, Spurious-Free Dynamic Range (dB) Signal-to-Noise Ratio, Total Harmonic Distortion, Spurious-Free Dynamic Range (dB) 140 120 100 SFDR THD 80 SNR 60 40 fIN = 10kHz 20 -80 -70 -60 -50 -40 -30 -20 -10 110 100 SFDR 90 THD 80 SNR 70 60 50 40 30 fIN = 50kHz 20 0 -80 -70 Input Signal Amplitude, VIN (dB) -40 -30 -20 Figure 15. Figure 16. SNR, THD, AND SFDR vs INPUT SIGNAL AMPLITUDE SNR, THD, AND SFDR vs INPUT SIGNAL AMPLITUDE 0 -10 140 Signal-to-Noise Ratio, Total Harmonic Distortion, Spurious-Free Dynamic Range (dB) Signal-to-Noise Ratio, Total Harmonic Distortion, Spurious-Free Dynamic Range (dB) -50 Input Signal Amplitude, VIN (dB) 140 120 100 SFDR 80 THD SNR 60 40 fIN = 100kHz 120 100 SFDR THD 80 60 SNR 40 fIN = 500kHz 20 20 -80 -70 -60 -50 -40 -30 -20 -10 0 -80 Input Signal Amplitude, VIN (dB) -70 -60 -50 -40 -30 -20 0 -10 Input Signal Amplitude, VIN (dB) Figure 17. Figure 18. SNR, THD, AND SFDR vs INPUT SIGNAL AMPLITUDE SNR vs INPUT FREQUENCY 140 95 VIN = -1dB 120 90 VIN = -6dB 100 SFDR SNR (dB) Signal-to-Noise Ratio, Total Harmonic Distortion, Spurious-Free Dynamic Range (dB) -60 THD 80 85 VIN = -10dB 80 60 SNR 75 40 fIN = 800kHz 20 -80 -70 -60 -50 -40 -30 -20 Input Signal Amplitude, VIN (dB) Figure 19. Copyright © 2004–2011, Texas Instruments Incorporated -10 0 70 10k 100k 1M Input Frequency, fIN (Hz) Figure 20. 11 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. THD vs INPUT FREQUENCY SFDR vs INPUT FREQUENCY 130 -85 120 -90 VIN = -10dB VIN = -10dB 110 -95 SFDR (dB) Total Harmonic Distortion (dB) -80 -100 -105 90 -110 VIN = -1dB VIN = -6dB -115 -120 VIN = -6dB 100 80 VIN = -1dB 70 10k 100k 1M 10k 100k Input Frequency, fIN (Hz) Figure 21. Figure 22. SNR vs INPUT COMMON-MODE VOLTAGE THD vs INPUT COMMON-MODE VOLTAGE 93 fIN = 10kHz, VIN = -1dB Total Harmonic Distortion (dB) Signal-to-Noise Ratio (dB) -70 fIN = 100kHz, VIN = -1dB 92 91 90 89 88 87 86 fIN = 100kHz, VIN = -6dB fIN = 100kHz, VIN = -1dB -80 fIN = 10kHz, VIN = -1dB -90 -100 fIN = 100kHz, VIN = -6dB fIN = 10kHz, VIN = -6dB fIN = 10kHz, VIN = -6dB 85 -110 1 1.4 1.8 2.2 2.6 3 1 3.4 Figure 23. 1.8 2.2 2.6 3 3.4 Figure 24. SFDR vs INPUT COMMON-MODE VOLTAGE OFFSET DRIFT OVER TIME 110 3 fIN = 10kHz, VIN = -6dB 105 2 fIN = 100kHz, VIN = -6dB 100 Offset (LSB) Spurious-Free Dynamic Range (dB) 1.4 Input Common-Mode Voltage, VCM (V) Input Common-Mode Voltage, VCM (V) fIN = 10kHz VIN = -1dB 95 90 85 1 0 -1 -2 fIN = 100kHz, VIN = -1dB 80 -3 1 1.4 1.8 2.2 2.6 Input Common-Mode Voltage, VCM (V) Figure 25. 12 1M Input Frequency, fIN (Hz) 3 3.4 0 100 200 300 400 500 600 700 800 900 1000 Time Interval (s) Figure 26. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SNR vs CLOCK FREQUENCY THD vs CLOCK FREQUENCY 110 100 RBIAS = 30kW RBIAS = 37kW Total Harmonic Distortion (dB) VIN = -6dBFS, fIN = 10kHz 90 SNR (dB) 80 70 RBIAS RBIAS = 60kW = 100kW RBIAS = 140kW RBIAS = 210kW 60 50 RBIAS = 267kW 40 RBIAS = 37kW 100 90 80 70 RBIAS = 210kW 50 RBIAS = 140kW 40 VIN = -6dBFS, fIN = 10kHz 20 5 10 15 20 25 30 35 40 45 5 50 10 15 20 Figure 27. SFDR vs CLOCK FREQUENCY 60 RBIAS = 210kW RBIAS = 140kW 30 RBIAS = 30kW RBIAS = 100kW 50 40 RMS Noise (LSB) SFDR (dB) RBIAS = 60kW RBIAS = 267kW 40 45 50 NOISE vs DC INPUT VOLTAGE 90 70 35 1000 RBIAS = 37kW 80 30 Figure 28. 110 100 25 Clock Frequency, fCLK (MHz) Clock Frequency, fCLK (MHz) 100 10 1 VIN = -6dBFS, fIN = 10kHz 0.1 20 5 10 15 20 25 30 35 40 45 50 -3 -2 0 -1 1 2 3 Input DC Voltage (V) Clock Frequency, fCLK (MHz) Figure 29. Figure 30. NOISE HISTOGRAM POWER-SUPPLY CURRENT vs TEMPERATURE 120 1540 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 VIN = 0 IAVDD (REFEN = low) 100 Current (mA) Occurrences RBIAS = 30kW RBIAS = 100kW 60 30 30 RBIAS = 60kW RBIAS = 267kW IAVDD (REFEN = high) 80 60 40 IDVDD + IIOVDD 20 RBIAS = 37kW, fCLK = 40MHz 0 -4 -3 -2 -1 0 1 Output Code (LSB) Figure 31. Copyright © 2004–2011, Texas Instruments Incorporated 2 3 4 -40 -15 10 35 60 85 Temperature (°C) Figure 32. 13 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SUPPLY CURRENT vs CLOCK FREQUENCY VIN = -6dBFS fIN = 10kHz RBIAS = 37kW Supply Current (mA) 120 ANALOG SUPPLY CURRENT vs RBIAS 130 Analog Supply Current, IAVDD (mA) 140 IAVDD (REFEN = low) 100 80 IAVDD (REFEN = high) 60 40 IIOVDD + IDVDD 20 VIN = -6dBFS fIN = 10kHz fCLK = 40MHz 110 90 70 50 IAVDD (REFEN = low) 30 IAVDD (REFEN = high) 10 0 0 5 10 15 20 25 30 35 0 40 50 100 Clock Frequency, fCLK (MHz) Figure 33. 200 250 300 Figure 34. SNR vs TEMPERATURE THD vs TEMPERATURE 100 Total Harmonic Distortion (dB) -80 95 VIN = -1dB 90 SNR (dB) 150 RBIAS (kW) VIN = -6dB 85 VIN = -10dB 80 75 -85 -90 -95 -100 VIN = -1dB VIN = -6dB VIN = -10dB fIN = 100kHz 70 -105 -40 -15 10 35 60 85 -40 10 -15 35 Temperature (°C) Temperature (°C) Figure 35. Figure 36. 60 85 SFDR vs TEMPERATURE Spurious-Free Dynamic Range (dB) 120 115 110 105 VIN = -10dB 100 VIN = -6dB 95 90 VIN = -1dB 85 80 -40 -15 10 35 60 85 Temperature (°C) Figure 37. 14 Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com OVERVIEW The ADS1602 is a high-performance delta-sigma (ΔΣ) analog-to-digital converter (ADC). The modulator uses an inherently stable 2-1-1 multi-stage architecture incorporating proprietary circuitry that allows for very linear high-speed operation. The modulator samples the input signal at 40MSPS (when fCLK = 40MHz). A low-ripple linear phase digital filter decimates the modulator output by 16 to provide high resolution 16-bit output data. Conceptually, the modulator and digital filter measure the differential input signal, VIN = (AINP – AINN), against the scaled differential reference, VREF = (VREFP – VREFN), as shown in Figure 38. The voltage reference can either be generated internally or supplied externally. A three-wire serial interface, designed for direct connection to DSPs, outputs the data. A separate power supply for the I/O allows flexibility for interfacing to different logic families. Out-of-range conditions are indicated with a dedicated digital output pin. Analog power dissipation is controlled using an external resistor. This control allows reduced dissipation when operating at slower speeds. When not in use, power consumption can be dramatically reduced by setting the PD pin low to enter Power-Down mode. The ADS1602 supports a very wide range of input signals. For VREF = 3V, the full-scale input voltages are ±3V. Having such a wide input range makes out-of-range signals unlikely. However, should an out-of-range signal occur, the digital output OTR goes high. The analog inputs must be driven with a differential signal to achieve optimum performance. For the input signal: VCM = AINP + AINN 2 the recommended common-mode voltage is 1.5V. In addition to the differential and common-mode input voltages, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: –0.1V < (AINN or AINP) < 4.6V If either input is taken below –0.1V, ESD protection diodes on the inputs will turn on. Exceeding 4.6V on either input results in degradation in the linearity performance. ESD protection diodes will also turn on if the inputs are taken above AVDD (+5V). The recommended absolute input voltage is: ANALOG INPUTS (AINP, AINN) –0.1V < (AINN or AINP) < 4.2V The ADS1602 measures the differential signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The most positive measurable differential input is VREF, which produces the most positive digital output code of 7FFFh. Likewise, the most negative measurable differential input is –VREF, which produces the most negative digital output code of 8000h. Keeping the inputs within this range provides for optimum performance. VREFP VREFN IOVDD CLK S VREF AINP AINN S VIN SD Modulator Digital Filter Serial Interface FSO FSO SCLK SCLK DOUT DOUT Figure 38. Conceptual Block Diagram Copyright © 2004–2011, Texas Instruments Incorporated 15 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 INPUT CIRCUITRY The ADS1602 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of CLK. Figure 39 shows a conceptual diagram of these circuits. Switches S2 represent the net effect of the modulator circuitry in discharging the sampling capacitors; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 40. ADS1602 S1 www.ti.com drivers close to the inputs and use good capacitor bypass techniques on the supplies, such as a smaller high-quality ceramic capacitor in parallel with a larger capacitor. Keep the resistances used in the driver circuits low—thermal noise in the driver circuits degrades the overall noise performance. When the signal can be ac-coupled to the ADS1602 inputs, a simple RC filter can set the input common-mode voltage. The ADS1602 is a high-speed, high-performance ADC. Special care must be taken when selecting the test equipment and setup used with this device. Pay particular attention to the signal sources to ensure they do not limit performance when measuring the ADS1602. AINP S2 10pF 392W 8pF - VMID VIN 392W 40pF 392W OPA2822 2 0.01mF S1 AINN (1) S2 10pF 49.9W AINP (2) VCM 100pF 8pF 392W 1kW 1m F 392W (2) (1) VCM VMID AGND VIN 392W 40pF 392W OPA2822 100pF (3) ADS1602 (2) 1kW 2 Figure 39. Conceptual Diagram of Internal Circuitry Connected to the Analog Inputs 0.01mF (1) VCM 49.9W AINN (2) 100pF 392W 1m F AGND tSAMPLE = 1/fCLK On (1) Recommended VCM = 1.5V. Off (2) Optional ac-coupling circuit provides common-mode input voltage. S1 On S2 (3) Increase to 390pF when fIN ≤ 100kHz for improved SNR and THD. Off Figure 40. Timing for the Switches in Figure 39 Figure 41. Recommended Driver Circuit Using the OPA2822 22pF DRIVING THE INPUTS The external circuits driving the ADS1602 inputs must be able to handle the load presented by the switching capacitors within the ADS1602. The input switches S1 in Figure 39 are closed for approximately one-half of the sampling period, tSAMPLE, allowing only ≉ 11ns for the internal capacitors to be charged by the inputs when fCLK = 40MHz. Figure 41 and Figure 42 show the recommended circuits when using single-ended or differential op amps, respectively. The analog inputs must be driven differentially to achieve optimum performance. The external capacitors, between the inputs and from each input to AGND, improve linearity and should be placed as close to the pins as possible. Place the 16 24.9W AINP 392W 392W 100pF -VIN VCM THS4503 100pF ADS1602 +VIN 392W 392W 24.9W AINN 100pF 22pF Figure 42. Recommended Driver Circuit Using the THS4503 Differential Amplifier Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com REFERENCE INPUTS (VREFN, VREFP, VMID) EXTERNAL REFERENCE (REFEN = HIGH) The ADS1602 can operate from an internal or external voltage reference. In either case, the reference voltage VREF is set by the differential voltage between VREFN and VREFP: VREF = (VREFP – VREFN). VREFP and VREFN each use two pins, which should be shorted together. VMID equals approximately 2.5V and is used by the modulator. VCAP connects to an internal node and must also be bypassed with an external capacitor. To use an external reference, set the REFEN pin high. This deactivates the internal generators for VREFP, VREFN, and VMID, and saves approximately 25mA of current on the analog supply (AVDD). The voltages applied to these pins must be within the values specified in the Electrical Characteristics table. Typically, VREFP = 4V, VMID = 2.5V, and VREFN = 1V. The external circuitry must be capable of providing both a dc and a transient current. Figure 44 shows a simplified diagram of the internal circuitry of the reference when the internal reference is disabled. As with the input circuitry, switches S1 and S2 open and close as shown by the timing in Figure 40. INTERNAL REFERENCE (REFEN = LOW) To use the internal reference, set the REFEN pin low. This activates the internal circuitry that generates the reference voltages. The internal reference voltages are applied to the pins. Good bypassing of the reference pins is critical to achieve optimum performance and is done by placing the bypass capacitors as close to the pins as possible. Figure 43 shows the recommended bypass capacitor values. Use high-quality ceramic capacitors for the smaller values. Avoid loading the internal reference with external circuitry. If the ADS1602 internal reference is to be used by other circuitry, buffer the reference voltages to prevent directly loading the reference pins. ADS1602 S1 VREFP VREFP S2 300W VREFN VREFN 50pF S1 Figure 44. Conceptual Internal Circuitry for the Reference When REFEN = High ADS1602 10mF 0.1mF VREFP VREFP VMID 0.1mF 10mF 0.1mF Figure 45 shows the recommended circuitry for driving these reference inputs. Keep the resistances used in the buffer circuits low to prevent excessive thermal noise from degrading performance. Layout of these circuits is critical; be sure to follow good high-speed layout practices. Place the buffers, and especially the bypass capacitors, as close to the pins as possible. VCAP is unaffected by the setting on REFEN and must be bypassed when using the internal or an external reference. VREFN VREFN 10mF 0.1mF VCAP 0.1mF AGND Figure 43. Reference Bypassing When Using the Internal Reference Copyright © 2004–2011, Texas Instruments Incorporated 17 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 Table 1. Maximum Allowable Clock Source Jitter for Different Input Signal Frequencies and Amplitude 392W 0.001mF ADS1602 VREFP VREFP OPA2822 10mF 4V 0.1mF 392W 0.001mF 0.1mF VMID OPA2822 10mF 2.5V www.ti.com 0.1mF INPUT SIGNAL MAXIMUM FREQUENCY MAXIMUM AMPLITUDE MAXIMUM ALLOWABLE CLOCK SOURCE JITTER 1MHz –2dB 3.8ps 1MHz –20dB 28ps 500kHz –2dB 7.6ps 500kHz –20dB 57ps 100kHz –2dB 38ps 100kHz –20dB 285ps 392W DATA FORMAT 0.001mF VREFN VREFN OPA2822 1V 10mF 0.1mF VCAP 0.1mF AGND Figure 45. Recommended Buffer Circuit When Using an External Reference The 16-bit output data are in binary two’s complement format as shown in Table 2. When the input is positive out-of-range, exceeding the positive full-scale value of VREF, the output clips to all 7FFFh and the OTR output goes high. Likewise, when the input is negative out-of-range by going below the negative full-scale value of –VREF, the output clips to 8000h and the OTR output goes high. The OTR remains high while the input signal is out-of-range. Table 2. Output Code versus Input Signal CLOCK INPUT (CLK) The ADS1602 requires an external clock signal to be applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any high-speed data converter, a high quality clock is essential for optimum performance. Crystal clock oscillators are the recommended CLK source; other sources, such as frequency synthesizers, are usually inadequate. Make sure to avoid excess ringing on the CLK input; keeping the trace as short as possible helps. Measuring high-frequency, large amplitude signals requires tight control of clock jitter. The uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. This effect becomes more pronounced with higher frequency and larger magnitude inputs. Fortunately, the ADS1602 oversampling topology reduces clock jitter sensitivity over that of Nyquist rate converters such as pipeline and successive approximation converters by a factor of √16. In order to not limit the ADS1602 SNR performance, keep the jitter on the clock source below the values shown in Table 1. When measuring lower frequency and lower amplitude inputs, more CLK jitter can be tolerated. In determining the allowable clock source jitter, select the worst-case input (highest frequency, largest amplitude) that will be seen in the application. 18 INPUT SIGNAL (INP – INN) IDEAL OUTPUT CODE(1) OTR ≥ +VREF (> 0dB) 7FFFh 1 –VREF (0dB) 7FFFh 0 0001h 0 0000h 0 FFFFh 0 ) 8000h 0 ) 8000h 1 +VREF 2 15 -1 0 -VREF 2 -VREF 15 -1 2 ( 2 £ -VREF 15 2 ( 2 15 15 -1 15 -1 (1) Excludes effects of noise, INL, offset, and gain errors. OUT-OF-RANGE INDICATION (OTR) If the output code exceeds the positive or negative full-scale, the out-of-range digital output OTR will go high on the falling edge of SCLK. When the output code returns within the full-scale range, OTR returns low on the falling edge of SCLK. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com DATA RETRIEVAL STEP RESPONSE Data retrieval is controlled through a simple serial interface. The interface operates in a master fashion by outputting both a frame sync indicator (FSO) and a serial clock (SCLK). Complementary outputs are provided for the frame sync output (FSO), serial clock (SCLK), and data output (DOUT). When not needed, leave the complementary outputs unconnected. Figure 47 plots the normalized step response for an input applied at t = 0. The x-axis units of time are conversion cycles. It takes 51 cycles to fully settle; for fCLK = 40MHz, this corresponds to 20.4μs. 1.2 1.0 INITIALIZING THE ADS1602 After the power supplies have stabilized, you must initialize the ADS1602 by issuing a SYNC pulse as shown in Figure 1. This operation needs only to be done once after power-up and does not need to be performed when exiting the Power-Down mode. Note that the ADS1602 silicon was revised in June 2006. The digital interface timing specifications were modified slightly from the previous revision. This data sheet reflects behavior of the latest revision. Contact the factory for more information on the previous revision. Step Response 0.8 0.6 0.4 0.2 0 -0.2 0 ADS16021 SYNC CLK SYNC CLK FSO1 FSO DOUT1 DOUT 40 50 FREQUENCY RESPONSE The linear phase FIR digital filter sets the overall frequency response. Figure 48 shows the frequency response from dc to 20MHz for fCLK = 40MHz. The frequency response of the ADS1602 filter scales directly with CLK frequency. For example, if the CLK frequency is decreased by half (to 20MHz), the values on the x-axis in Figure 48 would need to be scaled by half, with the span becoming dc to 10MHz. Figure 49 shows the passband ripple from dc to 1200kHz (fCLK = 40MHz). Figure 50 shows a closer view of the passband transition by plotting the response from 900kHz to 1300kHz (fCLK = 40MHz). 20 fCLK = 40MHz 0 FSO2 FSO -20 DOUT2 DOUT Magnitude (dB) CLK 30 Figure 47. Step Response ADS16022 SYNC 20 Time (Conversion Cycles) SYNCHRONIZING MULTIPLE ADS1602s The SYNC input can be used to synchronize multiple ADS1602s to provide simultaneous sampling. All devices to be synchronized must use a common CLK input. With the CLK inputs running, pulse SYNC on the falling edge of CLK, as shown in Figure 46. Afterwards, the converters will be converting synchronously with the FSO outputs updating simultaneously. After synchronization, FSO is held low until the digital filter has fully settled. 10 CLK -40 -60 -80 -100 SYNC -120 tSTL FSO1 -140 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) FSO2 Figure 48. Frequency Response Figure 46. Synchronizing Multiple Converters Copyright © 2004–2011, Texas Instruments Incorporated 19 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com 0.001 20 fCLK = 40MHz 0.0008 0 -20 0.0004 Magnitude (dB) Magnitude (dB) 0.0006 0.0002 0 -0.0002 -0.0004 -40 -60 -80 -100 -0.0006 -0.0008 -120 fCLK = 40MHz -0.001 0 200 400 600 800 1000 1200 -140 0 Frequency (kHz) fCLK = 40MHz Magnitude (dB) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 900 1000 1100 60 80 100 120 Figure 51. Frequency Response Out to 120MHz 0.5 800 40 Frequency (MHz) Figure 49. Passband Ripple 0 20 1200 1300 Frequency (kHz) Figure 50. Passband Transition ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 52. The current is inversely proportional to the resistor value. Table 3 shows the recommended values of RBIAS for different CLK frequencies. Notice that the analog current can be reduced when using a slower frequency CLK input because the modulator has more time to settle. Avoid adding any capacitance in parallel to RBIAS because this interferes with the internal circuitry used to set the biasing. Please note that changing the RBIAS resistor value changes all internally-generated bias voltages, including the internal reference; therefore, the recommendations in Table 3 are only for when using an external reference. ANTIALIAS REQUIREMENTS Higher frequency, out-of-band signals must be eliminated to prevent aliasing with ADCs. Fortunately, the ADS1602 on-chip digital filter greatly simplifies this filtering requirement. Figure 51 shows the ADS1602 response out to 120MHz (fCLK = 40MHz). Since the stop band extends out to 38.6MHz, the antialias filter in front of the ADS1602 only needs to be designed to remove higher frequency signals than this, which can usually be accomplished with a simple RC circuit on the input driver. ADS1602 RBIAS RBIAS AGND Figure 52. External Resistor Used to Set Analog Power Dissipation Table 3. Recommended RBIAS Resistor Values for Different CLK Frequencies 20 fCLK DATA RATE RBIAS TYPICAL POWER DISSIPATION WITH REFEN HIGH 16MHz 1MSPS 140kΩ 200mW 24MHz 1.5MSPS 100kΩ 270mW 32MHz 2MSPS 60kΩ 390mW 40MHz 2.5MSPS 37kΩ 530mW Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com POWER DOWN (PD) POWER SUPPLIES When not in use, the ADS1602 can be powered down by taking the PD pin low. All circuitry is shut down, including the voltage reference. To minimize the digital current during power down, stop the clock signal supplied to the CLK input. There is an internal pull-up resistor of 170kΩ on the PD pin, but it is recommended that this pin be connected to IOVDD if not used. Make sure to allow time for the reference to start up after exiting power-down mode. The internal reference typically requires 15ms. After the reference has stabilized, allow at least 100 conversions for the modulator and digital filter to settle before retrieving data. Three supplies are used on the ADS1602: analog (AVDD), digital (DVDD), and digital I/O (IOVDD). Each supply must be suitably bypassed to achieve the best performance. It is recommended that a 1μF and 0.1μF ceramic capacitor be placed as close to each supply pin as possible. Connect each supply-pin bypass capacitor to the associated ground, as shown in Figure 53. Each main supply bus should also be bypassed with a bank of capacitors from 47μF to 0.1μF, as shown. The I/O and digital supplies (IOVDD and DVDD) can be connected together when using the same voltage. In this case, only one bank of 47μF to 0.1μF capacitors is needed on the main supply bus, though each supply pin must still be bypassed with a 1μF and 0.1μF ceramic capacitor. DVDD 47mF 4.7mF 1mF 0.1mF 47mF 4.7mF 1mF 0.1mF 47mF 4.7mF 1mF 0.1mF IOVDD CP CP 42 41 55 38 37 34 33 AGND AGND DGND IOVDD DVDD DGND 1 AGND CP AVDD AVDD DGND 36 CP 2 If using separate analog and digital ground planes, connect together on the ADS1602 PCB. AVDD 3 6 AGND 7 AVDD 9 AGND CP DGND AGND ADS1602 CP 10 AVDD 10kW 19 22 CP DVDD 18 DGND 15 DGND 12 AVDD DVDD CP RPULLUP 11 AGND 23 CP NOTE: CP = 1µF || 0.1µF. Figure 53. Recommended Power-Supply Bypassing Copyright © 2004–2011, Texas Instruments Incorporated 21 ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com LAYOUT ISSUES AND COMPONENT SELECTION The McBSP provides a host of functions including: • Full-duplex communication • Double-buffered data registers • Independent framing and clocking for reception and transmission of data The ADS1602 is a very high-speed, high-resolution data converter. In order to achieve maximum performance, the user must give very careful consideration to both the layout of the printed circuit board (PCB) in addition to the routing of the traces. Capacitors that are critical to achieve the best performance from the device should be placed as close to the pins of the device as possible. These include capacitors related to the analog inputs, the reference, and the power supplies. For critical capacitors, it is recommended that Class II dielectrics such as Z5U be avoided. These dielectrics have a narrow operating temperature, a large tolerance on the capacitance, and lose up to 20% of the rated capacitance over 10,000 hours. Rather, select capacitors with a Class I dielectric. C0G (also known as NP0), for example, has a tight tolerance less than ±30ppm/°C and is very stable over time. Should Class II capacitors be chosen because of the size constraints, select an X7R or X5R dielectric to minimize the variations of the capacitor’s critical characteristics. The resistors used in the circuits to drive the input and reference should be kept as low as possible to prevent excess thermal noise from degrading the system performance. The digital outputs from the device should always be buffered. This has a number of benefits: it reduces the loading of the internal digital buffers, which decreases noise generated within the device, and it also reduces device power consumption. APPLICATIONS INFORMATION Interfacing the ADS1602 to the TMS320 DSP family Since the ADS1602 communicates with the host via a serial interface, the most suitable method to connect to any of the TMS320 DSPs is via the multi-channel buffered serial port (McBSP). A typical connection to the TMS320 DSP is shown in Figure 54. 22 The sequence begins with a one-time synchronization of the serial port by the microprocessor. The ADS1602 recognizes the SYNC signal if it is high for at least one CLK period. Transfers are initiated by the ADS1602 after the SYNC signal is de-asserted by the microprocessor. The FSO signal from the ADS1602 indicates that data is available to be read, and is connected to the frame sync receive (FSR) pin of the DSP. The clock receiver (CLKR) is derived directly from the ADS1602 serial clock output to ensure continued synchronization of data with the clock. ADS1602 FSO TMS320 FSR SCLK CLKR DOUT DR SYNC FSX Figure 54. ADS1602—TMS320 Interface Connection An evaluation module (EVM) is available from Texas Instruments. The module consists of the ADS1602 and supporting circuits, allowing users to quickly assess the performance and characteristics of the ADS1602. The EVM easily connects to various microcontrollers and DSP systems. For more details, or to download a copy of the ADS1602EVM User’s Guide, visit the Texas Instruments web site at www.ti.com. Copyright © 2004–2011, Texas Instruments Incorporated ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2010) to Revision E • Page Added footnote to Electrical Characteristics table ................................................................................................................ 4 Changes from Revision C (September 2010) to Revision D Page • Changed tC minimum specification in Timing Requirements table for Figure 1 ................................................................... 8 • Changed tCPW minimum specification in Timing Requirements table for Figure 2 ............................................................... 8 • Changed tDH minimum specification in Timing Requirements table for Figure 2 .................................................................. 8 Copyright © 2004–2011, Texas Instruments Incorporated 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1602IPFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1602I ADS1602IPFBT ACTIVE TQFP PFB 48 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1602I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of